drm/radeon: use gart memory for DMA ring tests
Avoids HDP cache flush issues when using vram which can cause ring test failures on certain boards. Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: Alexander Fyodorov <halcy@yandex.ru> Cc: stable@vger.kernel.org
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4910403836
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adfed2b058
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@ -618,16 +618,19 @@ int cik_sdma_ring_test(struct radeon_device *rdev,
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{
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unsigned i;
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int r;
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void __iomem *ptr = (void *)rdev->vram_scratch.ptr;
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unsigned index;
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u32 tmp;
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u64 gpu_addr;
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if (!ptr) {
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DRM_ERROR("invalid vram scratch pointer\n");
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return -EINVAL;
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}
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if (ring->idx == R600_RING_TYPE_DMA_INDEX)
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index = R600_WB_DMA_RING_TEST_OFFSET;
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else
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index = CAYMAN_WB_DMA1_RING_TEST_OFFSET;
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gpu_addr = rdev->wb.gpu_addr + index;
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tmp = 0xCAFEDEAD;
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writel(tmp, ptr);
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rdev->wb.wb[index/4] = cpu_to_le32(tmp);
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r = radeon_ring_lock(rdev, ring, 5);
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if (r) {
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@ -635,14 +638,14 @@ int cik_sdma_ring_test(struct radeon_device *rdev,
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return r;
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}
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radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_WRITE, SDMA_WRITE_SUB_OPCODE_LINEAR, 0));
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radeon_ring_write(ring, rdev->vram_scratch.gpu_addr & 0xfffffffc);
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radeon_ring_write(ring, upper_32_bits(rdev->vram_scratch.gpu_addr));
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radeon_ring_write(ring, lower_32_bits(gpu_addr));
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radeon_ring_write(ring, upper_32_bits(gpu_addr));
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radeon_ring_write(ring, 1); /* number of DWs to follow */
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radeon_ring_write(ring, 0xDEADBEEF);
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radeon_ring_unlock_commit(rdev, ring, false);
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for (i = 0; i < rdev->usec_timeout; i++) {
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tmp = readl(ptr);
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tmp = le32_to_cpu(rdev->wb.wb[index/4]);
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if (tmp == 0xDEADBEEF)
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break;
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DRM_UDELAY(1);
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@ -241,16 +241,19 @@ int r600_dma_ring_test(struct radeon_device *rdev,
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{
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unsigned i;
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int r;
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void __iomem *ptr = (void *)rdev->vram_scratch.ptr;
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unsigned index;
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u32 tmp;
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u64 gpu_addr;
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if (!ptr) {
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DRM_ERROR("invalid vram scratch pointer\n");
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return -EINVAL;
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}
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if (ring->idx == R600_RING_TYPE_DMA_INDEX)
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index = R600_WB_DMA_RING_TEST_OFFSET;
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else
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index = CAYMAN_WB_DMA1_RING_TEST_OFFSET;
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gpu_addr = rdev->wb.gpu_addr + index;
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tmp = 0xCAFEDEAD;
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writel(tmp, ptr);
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rdev->wb.wb[index/4] = cpu_to_le32(tmp);
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r = radeon_ring_lock(rdev, ring, 4);
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if (r) {
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@ -258,13 +261,13 @@ int r600_dma_ring_test(struct radeon_device *rdev,
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return r;
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}
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radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_WRITE, 0, 0, 1));
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radeon_ring_write(ring, rdev->vram_scratch.gpu_addr & 0xfffffffc);
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radeon_ring_write(ring, upper_32_bits(rdev->vram_scratch.gpu_addr) & 0xff);
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radeon_ring_write(ring, lower_32_bits(gpu_addr));
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radeon_ring_write(ring, upper_32_bits(gpu_addr) & 0xff);
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radeon_ring_write(ring, 0xDEADBEEF);
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radeon_ring_unlock_commit(rdev, ring, false);
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for (i = 0; i < rdev->usec_timeout; i++) {
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tmp = readl(ptr);
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tmp = le32_to_cpu(rdev->wb.wb[index/4]);
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if (tmp == 0xDEADBEEF)
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break;
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DRM_UDELAY(1);
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@ -1132,6 +1132,8 @@ struct radeon_wb {
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#define R600_WB_EVENT_OFFSET 3072
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#define CIK_WB_CP1_WPTR_OFFSET 3328
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#define CIK_WB_CP2_WPTR_OFFSET 3584
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#define R600_WB_DMA_RING_TEST_OFFSET 3588
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#define CAYMAN_WB_DMA1_RING_TEST_OFFSET 3592
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/**
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* struct radeon_pm - power management datas
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