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coresight: etm4x: Fix enabling of cycle accurate tracing in perf. 

Using perf record 'cyclacc' option in cs_etm event was not setting up cycle
accurate trace correctly.

Corrects bit set in TRCCONFIGR to enable cycle accurate trace.
Programs TRCCCCTLR with a valid threshold value as required by ETMv4 spec.

Signed-off-by: Mike Leach <mike.leach@linaro.org>
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
zero-colors
Mike Leach 2017-01-23 10:41:23 -07:00 committed by Greg Kroah-Hartman
parent f094446390
commit ae3fabcda0
2 changed files with 6 additions and 2 deletions
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7
drivers/hwtracing/coresight/coresight-etm4x.c
View File

@ -216,8 +216,11 @@ static int etm4_parse_event_config(struct etmv4_drvdata *drvdata,
goto out;
/* Go from generic option to ETMv4 specifics */
if (attr->config & BIT(ETM_OPT_CYCACC))
config->cfg |= ETMv4_MODE_CYCACC;
if (attr->config & BIT(ETM_OPT_CYCACC)) {
config->cfg |= BIT(4);
/* TRM: Must program this for cycacc to work */
config->ccctlr = ETM_CYC_THRESHOLD_DEFAULT;
}
if (attr->config & BIT(ETM_OPT_TS))
config->cfg |= ETMv4_MODE_TIMESTAMP;

1
drivers/hwtracing/coresight/coresight-etm4x.h
View File

@ -146,6 +146,7 @@
#define ETM_ARCH_V4 0x40
#define ETMv4_SYNC_MASK 0x1F
#define ETM_CYC_THRESHOLD_MASK 0xFFF
#define ETM_CYC_THRESHOLD_DEFAULT 0x100
#define ETMv4_EVENT_MASK 0xFF
#define ETM_CNTR_MAX_VAL 0xFFFF
#define ETM_TRACEID_MASK 0x3f