Merge master.kernel.org:/home/rmk/linux-2.6-mmc
* master.kernel.org:/home/rmk/linux-2.6-mmc: [ARM] 3531/1: i.MX/MX1 SD/MMC ensure, that clock are stopped before new command and cleanups
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commit
ae83e25504
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@ -310,7 +310,7 @@ static void au1xmmc_data_complete(struct au1xmmc_host *host, u32 status)
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}
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else
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data->bytes_xfered =
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(data->blocks * (1 << data->blksz_bits)) -
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(data->blocks * data->blksz) -
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host->pio.len;
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}
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@ -575,7 +575,7 @@ static int
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au1xmmc_prepare_data(struct au1xmmc_host *host, struct mmc_data *data)
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{
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int datalen = data->blocks * (1 << data->blksz_bits);
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int datalen = data->blocks * data->blksz;
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if (dma != 0)
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host->flags |= HOST_F_DMA;
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@ -596,7 +596,7 @@ au1xmmc_prepare_data(struct au1xmmc_host *host, struct mmc_data *data)
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if (host->dma.len == 0)
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return MMC_ERR_TIMEOUT;
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au_writel((1 << data->blksz_bits) - 1, HOST_BLKSIZE(host));
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au_writel(data->blksz - 1, HOST_BLKSIZE(host));
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if (host->flags & HOST_F_DMA) {
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int i;
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@ -218,8 +218,10 @@ static int imxmci_busy_wait_for_status(struct imxmci_host *host,
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if(!loops)
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return 0;
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dev_info(mmc_dev(host->mmc), "busy wait for %d usec in %s, STATUS = 0x%x (0x%x)\n",
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loops, where, *pstat, stat_mask);
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/* The busy-wait is expected there for clock <8MHz due to SDHC hardware flaws */
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if(!(stat_mask & STATUS_END_CMD_RESP) || (host->mmc->ios.clock>=8000000))
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dev_info(mmc_dev(host->mmc), "busy wait for %d usec in %s, STATUS = 0x%x (0x%x)\n",
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loops, where, *pstat, stat_mask);
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return loops;
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}
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@ -333,6 +335,9 @@ static void imxmci_start_cmd(struct imxmci_host *host, struct mmc_command *cmd,
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WARN_ON(host->cmd != NULL);
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host->cmd = cmd;
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/* Ensure, that clock are stopped else command programming and start fails */
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imxmci_stop_clock(host);
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if (cmd->flags & MMC_RSP_BUSY)
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cmdat |= CMD_DAT_CONT_BUSY;
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@ -553,7 +558,7 @@ static int imxmci_cpu_driven_data(struct imxmci_host *host, unsigned int *pstat)
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int trans_done = 0;
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unsigned int stat = *pstat;
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if(host->actual_bus_width == MMC_BUS_WIDTH_4)
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if(host->actual_bus_width != MMC_BUS_WIDTH_4)
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burst_len = 16;
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else
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burst_len = 64;
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@ -591,8 +596,7 @@ static int imxmci_cpu_driven_data(struct imxmci_host *host, unsigned int *pstat)
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stat = MMC_STATUS;
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/* Flush extra bytes from FIFO */
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while(flush_len >= 2){
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flush_len -= 2;
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while(flush_len && !(stat & STATUS_DATA_TRANS_DONE)){
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i = MMC_BUFFER_ACCESS;
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stat = MMC_STATUS;
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stat &= ~STATUS_CRC_READ_ERR; /* Stupid but required there */
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@ -746,10 +750,6 @@ static void imxmci_tasklet_fnc(unsigned long data)
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data_dir_mask = STATUS_DATA_TRANS_DONE;
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}
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imxmci_busy_wait_for_status(host, &stat,
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data_dir_mask,
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50, "imxmci_tasklet_fnc data");
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if(stat & data_dir_mask) {
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clear_bit(IMXMCI_PEND_DMA_END_b, &host->pending_events);
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imxmci_data_done(host, stat);
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@ -865,7 +865,11 @@ static void imxmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
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imxmci_stop_clock(host);
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MMC_CLK_RATE = (prescaler<<3) | clk;
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imxmci_start_clock(host);
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/*
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* Under my understanding, clock should not be started there, because it would
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* initiate SDHC sequencer and send last or random command into card
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*/
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/*imxmci_start_clock(host);*/
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dev_dbg(mmc_dev(host->mmc), "MMC_CLK_RATE: 0x%08x\n", MMC_CLK_RATE);
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} else {
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@ -951,6 +951,7 @@ static void mmc_read_scrs(struct mmc_host *host)
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data.timeout_ns = card->csd.tacc_ns * 10;
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data.timeout_clks = card->csd.tacc_clks * 10;
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data.blksz_bits = 3;
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data.blksz = 1 << 3;
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data.blocks = 1;
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data.flags = MMC_DATA_READ;
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data.sg = &sg;
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@ -175,6 +175,7 @@ static int mmc_blk_issue_rq(struct mmc_queue *mq, struct request *req)
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brq.data.timeout_ns = card->csd.tacc_ns * 10;
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brq.data.timeout_clks = card->csd.tacc_clks * 10;
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brq.data.blksz_bits = md->block_bits;
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brq.data.blksz = 1 << md->block_bits;
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brq.data.blocks = req->nr_sectors >> (md->block_bits - 9);
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brq.stop.opcode = MMC_STOP_TRANSMISSION;
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brq.stop.arg = 0;
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@ -119,7 +119,7 @@ static void pxamci_setup_data(struct pxamci_host *host, struct mmc_data *data)
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nob = 0xffff;
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writel(nob, host->base + MMC_NOB);
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writel(1 << data->blksz_bits, host->base + MMC_BLKLEN);
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writel(data->blksz, host->base + MMC_BLKLEN);
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clks = (unsigned long long)data->timeout_ns * CLOCKRATE;
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do_div(clks, 1000000000UL);
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@ -283,7 +283,7 @@ static int pxamci_data_done(struct pxamci_host *host, unsigned int stat)
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* data blocks as being in error.
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*/
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if (data->error == MMC_ERR_NONE)
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data->bytes_xfered = data->blocks << data->blksz_bits;
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data->bytes_xfered = data->blocks * data->blksz;
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else
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data->bytes_xfered = 0;
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@ -662,14 +662,14 @@ static void wbsd_prepare_data(struct wbsd_host *host, struct mmc_data *data)
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unsigned long dmaflags;
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DBGF("blksz %04x blks %04x flags %08x\n",
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1 << data->blksz_bits, data->blocks, data->flags);
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data->blksz, data->blocks, data->flags);
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DBGF("tsac %d ms nsac %d clk\n",
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data->timeout_ns / 1000000, data->timeout_clks);
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/*
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* Calculate size.
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*/
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host->size = data->blocks << data->blksz_bits;
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host->size = data->blocks * data->blksz;
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/*
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* Check timeout values for overflow.
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@ -696,12 +696,12 @@ static void wbsd_prepare_data(struct wbsd_host *host, struct mmc_data *data)
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* Two bytes are needed for each data line.
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*/
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if (host->bus_width == MMC_BUS_WIDTH_1) {
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blksize = (1 << data->blksz_bits) + 2;
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blksize = data->blksz + 2;
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wbsd_write_index(host, WBSD_IDX_PBSMSB, (blksize >> 4) & 0xF0);
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wbsd_write_index(host, WBSD_IDX_PBSLSB, blksize & 0xFF);
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} else if (host->bus_width == MMC_BUS_WIDTH_4) {
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blksize = (1 << data->blksz_bits) + 2 * 4;
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blksize = data->blksz + 2 * 4;
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wbsd_write_index(host, WBSD_IDX_PBSMSB,
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((blksize >> 4) & 0xF0) | WBSD_DATA_WIDTH);
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@ -69,6 +69,7 @@ struct mmc_data {
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unsigned int timeout_ns; /* data timeout (in ns, max 80ms) */
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unsigned int timeout_clks; /* data timeout (in clocks) */
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unsigned int blksz_bits; /* data block size */
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unsigned int blksz; /* data block size */
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unsigned int blocks; /* number of blocks */
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unsigned int error; /* data error */
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unsigned int flags;
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