[MIPS] Malta: use tabs not spaces
This patch fixes all "use tabs not spaces" warnings reported by the checkpatch.pl script on the board-specific files. No functional changes introduced. Signed-off-by: Dmitri Vorobiev <dmitri.vorobiev@gmail.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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@ -47,7 +47,7 @@ static DEFINE_SPINLOCK(mips_irq_lock);
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static inline int mips_pcibios_iack(void)
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{
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int irq;
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u32 dummy;
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u32 dummy;
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/*
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* Determine highest priority pending interrupt by performing
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@ -58,7 +58,7 @@ static inline int mips_pcibios_iack(void)
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case MIPS_REVISION_SCON_ROCIT:
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case MIPS_REVISION_SCON_SOCITSC:
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case MIPS_REVISION_SCON_SOCITSCP:
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MSC_READ(MSC01_PCI_IACK, irq);
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MSC_READ(MSC01_PCI_IACK, irq);
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irq &= 0xff;
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break;
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case MIPS_REVISION_SCON_GT64120:
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@ -123,15 +123,15 @@ static void malta_hw0_irqdispatch(void)
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static void corehi_irqdispatch(void)
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{
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unsigned int intedge, intsteer, pcicmd, pcibadaddr;
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unsigned int pcimstat, intisr, inten, intpol;
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unsigned int pcimstat, intisr, inten, intpol;
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unsigned int intrcause, datalo, datahi;
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struct pt_regs *regs = get_irq_regs();
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printk(KERN_EMERG "CoreHI interrupt, shouldn't happen, we die here!\n");
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printk(KERN_EMERG "epc : %08lx\nStatus: %08lx\n"
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"Cause : %08lx\nbadVaddr : %08lx\n",
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regs->cp0_epc, regs->cp0_status,
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regs->cp0_cause, regs->cp0_badvaddr);
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"Cause : %08lx\nbadVaddr : %08lx\n",
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regs->cp0_epc, regs->cp0_status,
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regs->cp0_cause, regs->cp0_badvaddr);
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/* Read all the registers and then print them as there is a
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problem with interspersed printk's upsetting the Bonito controller.
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@ -139,29 +139,29 @@ static void corehi_irqdispatch(void)
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*/
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switch (mips_revision_sconid) {
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case MIPS_REVISION_SCON_SOCIT:
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case MIPS_REVISION_SCON_SOCIT:
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case MIPS_REVISION_SCON_ROCIT:
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case MIPS_REVISION_SCON_SOCITSC:
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case MIPS_REVISION_SCON_SOCITSCP:
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ll_msc_irq();
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break;
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case MIPS_REVISION_SCON_GT64120:
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intrcause = GT_READ(GT_INTRCAUSE_OFS);
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datalo = GT_READ(GT_CPUERR_ADDRLO_OFS);
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datahi = GT_READ(GT_CPUERR_ADDRHI_OFS);
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ll_msc_irq();
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break;
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case MIPS_REVISION_SCON_GT64120:
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intrcause = GT_READ(GT_INTRCAUSE_OFS);
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datalo = GT_READ(GT_CPUERR_ADDRLO_OFS);
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datahi = GT_READ(GT_CPUERR_ADDRHI_OFS);
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printk(KERN_EMERG "GT_INTRCAUSE = %08x\n", intrcause);
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printk(KERN_EMERG "GT_CPUERR_ADDR = %02x%08x\n",
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datahi, datalo);
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break;
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case MIPS_REVISION_SCON_BONITO:
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pcibadaddr = BONITO_PCIBADADDR;
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pcimstat = BONITO_PCIMSTAT;
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intisr = BONITO_INTISR;
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inten = BONITO_INTEN;
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intpol = BONITO_INTPOL;
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intedge = BONITO_INTEDGE;
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intsteer = BONITO_INTSTEER;
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pcicmd = BONITO_PCICMD;
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break;
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case MIPS_REVISION_SCON_BONITO:
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pcibadaddr = BONITO_PCIBADADDR;
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pcimstat = BONITO_PCIMSTAT;
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intisr = BONITO_INTISR;
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inten = BONITO_INTEN;
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intpol = BONITO_INTPOL;
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intedge = BONITO_INTEDGE;
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intsteer = BONITO_INTSTEER;
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pcicmd = BONITO_PCICMD;
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printk(KERN_EMERG "BONITO_INTISR = %08x\n", intisr);
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printk(KERN_EMERG "BONITO_INTEN = %08x\n", inten);
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printk(KERN_EMERG "BONITO_INTPOL = %08x\n", intpol);
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@ -170,11 +170,11 @@ static void corehi_irqdispatch(void)
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printk(KERN_EMERG "BONITO_PCICMD = %08x\n", pcicmd);
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printk(KERN_EMERG "BONITO_PCIBADADDR = %08x\n", pcibadaddr);
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printk(KERN_EMERG "BONITO_PCIMSTAT = %08x\n", pcimstat);
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break;
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}
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break;
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}
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/* We die here*/
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die("CoreHi interrupt", regs);
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/* We die here*/
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die("CoreHi interrupt", regs);
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}
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static inline int clz(unsigned long x)
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@ -300,17 +300,17 @@ void __init arch_init_irq(void)
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if (!cpu_has_veic)
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mips_cpu_irq_init();
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switch(mips_revision_sconid) {
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case MIPS_REVISION_SCON_SOCIT:
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case MIPS_REVISION_SCON_ROCIT:
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switch (mips_revision_sconid) {
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case MIPS_REVISION_SCON_SOCIT:
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case MIPS_REVISION_SCON_ROCIT:
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if (cpu_has_veic)
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init_msc_irqs(MIPS_MSC01_IC_REG_BASE, MSC01E_INT_BASE, msc_eicirqmap, msc_nr_eicirqs);
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else
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init_msc_irqs(MIPS_MSC01_IC_REG_BASE, MSC01C_INT_BASE, msc_irqmap, msc_nr_irqs);
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break;
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case MIPS_REVISION_SCON_SOCITSC:
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case MIPS_REVISION_SCON_SOCITSCP:
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case MIPS_REVISION_SCON_SOCITSC:
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case MIPS_REVISION_SCON_SOCITSCP:
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if (cpu_has_veic)
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init_msc_irqs(MIPS_SOCITSC_IC_REG_BASE, MSC01E_INT_BASE, msc_eicirqmap, msc_nr_eicirqs);
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else
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@ -34,7 +34,7 @@ static void msmtc_send_ipi_mask(cpumask_t mask, unsigned int action)
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*/
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static void __cpuinit msmtc_init_secondary(void)
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{
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void smtc_init_secondary(void);
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void smtc_init_secondary(void);
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int myvpe;
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/* Don't enable Malta I/O interrupts (IP2) for secondary VPEs */
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