Merge branch 'at91-3.4-base+pm_cleanup' of git://github.com/at91linux/linux-at91 into next/cleanup
* 'at91-3.4-base+pm_cleanup' of git://github.com/at91linux/linux-at91: ARM: at91: implement the standby function for pm/cpuidle ARM: at91: remove wait_for_interrupt definition ARM: at91: declare header name ARM: at91: coding style fixes
This commit is contained in:
Olof Johansson
commit
b01ee53dda
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@ -39,20 +39,15 @@ static int at91_enter_idle(struct cpuidle_device *dev,
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{
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struct timeval before, after;
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int idle_time;
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u32 saved_lpr;
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local_irq_disable();
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do_gettimeofday(&before);
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if (index == 0)
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/* Wait for interrupt state */
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cpu_do_idle();
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else if (index == 1) {
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asm("b 1f; .align 5; 1:");
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asm("mcr p15, 0, r0, c7, c10, 4"); /* drain write buffer */
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saved_lpr = sdram_selfrefresh_enable();
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cpu_do_idle();
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sdram_selfrefresh_disable(saved_lpr);
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}
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else if (index == 1)
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at91_standby();
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do_gettimeofday(&after);
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local_irq_enable();
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idle_time = (after.tv_sec - before.tv_sec) * USEC_PER_SEC +
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@ -198,7 +198,6 @@ extern u32 at91_slow_clock_sz;
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static int at91_pm_enter(suspend_state_t state)
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{
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u32 saved_lpr;
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at91_gpio_suspend();
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at91_irq_suspend();
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@ -254,16 +253,7 @@ static int at91_pm_enter(suspend_state_t state)
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* For ARM 926 based chips, this requirement is weaker
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* as at91sam9 can access a RAM in self-refresh mode.
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*/
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asm volatile ( "mov r0, #0\n\t"
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"b 1f\n\t"
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".align 5\n\t"
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"1: mcr p15, 0, r0, c7, c10, 4\n\t"
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: /* no output */
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: /* no input */
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: "r0");
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saved_lpr = sdram_selfrefresh_enable();
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wait_for_interrupt_enable();
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sdram_selfrefresh_disable(saved_lpr);
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at91_standby();
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break;
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case PM_SUSPEND_ON:
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@ -1,3 +1,16 @@
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/*
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* AT91 Power Management
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*
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* Copyright (C) 2005 David Brownell
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#ifndef __ARCH_ARM_MACH_AT91_PM
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#define __ARCH_ARM_MACH_AT91_PM
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#ifdef CONFIG_ARCH_AT91RM9200
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#include <mach/at91rm9200_mc.h>
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@ -11,18 +24,25 @@
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* still in self-refresh is "not recommended", but seems to work.
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*/
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static inline u32 sdram_selfrefresh_enable(void)
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static inline void at91rm9200_standby(void)
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{
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u32 saved_lpr = at91_sys_read(AT91_SDRAMC_LPR);
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u32 lpr = at91_sys_read(AT91_SDRAMC_LPR);
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at91_sys_write(AT91_SDRAMC_LPR, 0);
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at91_sys_write(AT91_SDRAMC_SRR, 1);
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return saved_lpr;
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asm volatile(
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"b 1f\n\t"
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".align 5\n\t"
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"1: mcr p15, 0, %0, c7, c10, 4\n\t"
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" str %0, [%1, %2]\n\t"
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" str %3, [%1, %4]\n\t"
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" mcr p15, 0, %0, c7, c0, 4\n\t"
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" str %5, [%1, %2]"
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:
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: "r" (0), "r" (AT91_BASE_SYS), "r" (AT91_SDRAMC_LPR),
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"r" (1), "r" (AT91_SDRAMC_SRR),
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"r" (lpr));
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}
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#define sdram_selfrefresh_disable(saved_lpr) at91_sys_write(AT91_SDRAMC_LPR, saved_lpr)
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#define wait_for_interrupt_enable() asm volatile ("mcr p15, 0, %0, c7, c0, 4" \
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: : "r" (0))
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#define at91_standby at91rm9200_standby
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#elif defined(CONFIG_ARCH_AT91SAM9G45)
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#include <mach/at91sam9_ddrsdr.h>
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@ -30,14 +50,12 @@ static inline u32 sdram_selfrefresh_enable(void)
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/* We manage both DDRAM/SDRAM controllers, we need more than one value to
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* remember.
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*/
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static u32 saved_lpr1;
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static inline u32 sdram_selfrefresh_enable(void)
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static inline void at91sam9g45_standby(void)
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{
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/* Those tow values allow us to delay self-refresh activation
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/* Those two values allow us to delay self-refresh activation
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* to the maximum. */
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u32 lpr0, lpr1;
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u32 saved_lpr0;
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u32 saved_lpr0, saved_lpr1;
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saved_lpr1 = at91_ramc_read(1, AT91_DDRSDRC_LPR);
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lpr1 = saved_lpr1 & ~AT91_DDRSDRC_LPCB;
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@ -51,15 +69,13 @@ static inline u32 sdram_selfrefresh_enable(void)
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at91_ramc_write(0, AT91_DDRSDRC_LPR, lpr0);
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at91_ramc_write(1, AT91_DDRSDRC_LPR, lpr1);
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return saved_lpr0;
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cpu_do_idle();
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at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr0);
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at91_ramc_write(1, AT91_DDRSDRC_LPR, saved_lpr1);
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}
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#define sdram_selfrefresh_disable(saved_lpr0) \
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do { \
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at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr0); \
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at91_ramc_write(1, AT91_DDRSDRC_LPR, saved_lpr1); \
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} while (0)
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#define wait_for_interrupt_enable() cpu_do_idle()
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#define at91_standby at91sam9g45_standby
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#else
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#include <mach/at91sam9_sdramc.h>
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@ -72,18 +88,23 @@ static inline u32 sdram_selfrefresh_enable(void)
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#warning Assuming EB1 SDRAM controller is *NOT* used
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#endif
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static inline u32 sdram_selfrefresh_enable(void)
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static inline void at91sam9_standby(void)
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{
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u32 saved_lpr, lpr;
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saved_lpr = at91_ramc_read(0, AT91_SDRAMC_LPR);
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lpr = saved_lpr & ~AT91_SDRAMC_LPCB;
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at91_ramc_write(0, AT91_SDRAMC_LPR, lpr | AT91_SDRAMC_LPCB_SELF_REFRESH);
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return saved_lpr;
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at91_ramc_write(0, AT91_SDRAMC_LPR, lpr |
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AT91_SDRAMC_LPCB_SELF_REFRESH);
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cpu_do_idle();
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at91_ramc_write(0, AT91_SDRAMC_LPR, saved_lpr);
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}
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#define sdram_selfrefresh_disable(saved_lpr) at91_ramc_write(0, AT91_SDRAMC_LPR, saved_lpr)
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#define wait_for_interrupt_enable() cpu_do_idle()
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#define at91_standby at91sam9_standby
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#endif
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#endif
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