[PATCH] x86: don't use cpuid.2 to determine cache info if cpuid.4 is supported
Don't use cpuid.2 to determine cache info if cpuid.4 is supported. The exception is P4 trace cache. We always use cpuid.2 to get trace cache under P4. Signed-off-by: Shaohua Li <shaohua.li@intel.com> Cc: Andi Kleen <ak@muc.de> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
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0806903316
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@ -225,11 +225,19 @@ unsigned int __cpuinit init_intel_cacheinfo(struct cpuinfo_x86 *c)
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}
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}
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}
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if (c->cpuid_level > 1) {
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/*
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* Don't use cpuid2 if cpuid4 is supported. For P4, we use cpuid2 for
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* trace cache
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*/
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if ((num_cache_leaves == 0 || c->x86 == 15) && c->cpuid_level > 1) {
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/* supports eax=2 call */
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int i, j, n;
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int regs[4];
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unsigned char *dp = (unsigned char *)regs;
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int only_trace = 0;
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if (num_cache_leaves != 0 && c->x86 == 15)
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only_trace = 1;
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/* Number of times to iterate */
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n = cpuid_eax(2) & 0xFF;
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@ -251,6 +259,8 @@ unsigned int __cpuinit init_intel_cacheinfo(struct cpuinfo_x86 *c)
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while (cache_table[k].descriptor != 0)
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{
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if (cache_table[k].descriptor == des) {
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if (only_trace && cache_table[k].cache_type != LVL_TRACE)
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break;
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switch (cache_table[k].cache_type) {
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case LVL_1_INST:
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l1i += cache_table[k].size;
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@ -276,43 +286,46 @@ unsigned int __cpuinit init_intel_cacheinfo(struct cpuinfo_x86 *c)
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}
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}
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}
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if (new_l1d)
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l1d = new_l1d;
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if (new_l1i)
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l1i = new_l1i;
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if (new_l2) {
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l2 = new_l2;
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#ifdef CONFIG_SMP
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cpu_llc_id[cpu] = l2_id;
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#endif
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}
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if (new_l3) {
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l3 = new_l3;
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#ifdef CONFIG_SMP
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cpu_llc_id[cpu] = l3_id;
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#endif
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}
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if ( trace )
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printk (KERN_INFO "CPU: Trace cache: %dK uops", trace);
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else if ( l1i )
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printk (KERN_INFO "CPU: L1 I cache: %dK", l1i);
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if ( l1d )
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printk(", L1 D cache: %dK\n", l1d);
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else
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printk("\n");
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if ( l2 )
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printk(KERN_INFO "CPU: L2 cache: %dK\n", l2);
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if ( l3 )
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printk(KERN_INFO "CPU: L3 cache: %dK\n", l3);
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c->x86_cache_size = l3 ? l3 : (l2 ? l2 : (l1i+l1d));
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}
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if (new_l1d)
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l1d = new_l1d;
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if (new_l1i)
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l1i = new_l1i;
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if (new_l2) {
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l2 = new_l2;
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#ifdef CONFIG_SMP
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cpu_llc_id[cpu] = l2_id;
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#endif
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}
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if (new_l3) {
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l3 = new_l3;
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#ifdef CONFIG_SMP
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cpu_llc_id[cpu] = l3_id;
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#endif
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}
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if (trace)
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printk (KERN_INFO "CPU: Trace cache: %dK uops", trace);
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else if ( l1i )
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printk (KERN_INFO "CPU: L1 I cache: %dK", l1i);
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if (l1d)
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printk(", L1 D cache: %dK\n", l1d);
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else
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printk("\n");
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if (l2)
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printk(KERN_INFO "CPU: L2 cache: %dK\n", l2);
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if (l3)
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printk(KERN_INFO "CPU: L3 cache: %dK\n", l3);
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c->x86_cache_size = l3 ? l3 : (l2 ? l2 : (l1i+l1d));
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return l2;
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}
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