drm/i915/guc: Refactor the concept "GuC context descriptor" into "GuC stage descriptor"
A GuC context and a HW context are in no way related, so the name "GuC context descriptor" is very unfortunate, because a new reader of the code gets overwhelmed very quickly with a lot of things called "context" that refer to different things. We can improve legibility a lot by simply renaming a few objects in the GuC code. v2: - Rebased - s/ctx_desc_pool/stage_desc_pool - Move some explanations to the definition of the guc_stage_desc struct (Chris) v3: - Calculate gemsize with less intermediate steps (Joonas) - Use BIT() macro (Joonas) Signed-off-by: Oscar Mateo <oscar.mateo@intel.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Signed-off-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
This commit is contained in:
parent
397fce887a
commit
b09935a60d
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@ -2471,8 +2471,8 @@ static void i915_guc_client_info(struct seq_file *m,
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enum intel_engine_id id;
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uint64_t tot = 0;
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seq_printf(m, "\tPriority %d, GuC ctx index: %u, PD offset 0x%x\n",
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client->priority, client->ctx_index, client->proc_desc_offset);
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seq_printf(m, "\tPriority %d, GuC stage index: %u, PD offset 0x%x\n",
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client->priority, client->stage_id, client->proc_desc_offset);
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seq_printf(m, "\tDoorbell id %d, offset: 0x%lx, cookie 0x%x\n",
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client->doorbell_id, client->doorbell_offset, client->doorbell_cookie);
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seq_printf(m, "\tWQ size %d, offset: 0x%x, tail %d\n",
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@ -37,16 +37,16 @@
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* descriptor and a workqueue (all of them inside a single gem object that
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* contains all required pages for these elements).
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*
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* GuC context descriptor:
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* GuC stage descriptor:
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* During initialization, the driver allocates a static pool of 1024 such
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* descriptors, and shares them with the GuC.
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* Currently, there exists a 1:1 mapping between a i915_guc_client and a
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* guc_context_desc (via the client's context_index), so effectively only
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* one guc_context_desc gets used. This context descriptor lets the GuC know
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* about the doorbell, workqueue and process descriptor. Theoretically, it also
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* lets the GuC know about our HW contexts (Context ID, etc...), but we actually
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* guc_stage_desc (via the client's stage_id), so effectively only one
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* gets used. This stage descriptor lets the GuC know about the doorbell,
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* workqueue and process descriptor. Theoretically, it also lets the GuC
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* know about our HW contexts (context ID, etc...), but we actually
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* employ a kind of submission where the GuC uses the LRCA sent via the work
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* item instead (the single guc_context_desc associated to execbuf client
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* item instead (the single guc_stage_desc associated to execbuf client
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* contains information about the default kernel context only, but this is
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* essentially unused). This is called a "proxy" submission.
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*
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@ -82,7 +82,7 @@
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static inline bool is_high_priority(struct i915_guc_client* client)
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{
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return client->priority <= GUC_CTX_PRIORITY_HIGH;
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return client->priority <= GUC_CLIENT_PRIORITY_HIGH;
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}
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static int __reserve_doorbell(struct i915_guc_client *client)
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@ -112,7 +112,7 @@ static int __reserve_doorbell(struct i915_guc_client *client)
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__set_bit(id, client->guc->doorbell_bitmap);
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client->doorbell_id = id;
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DRM_DEBUG_DRIVER("client %u (high prio=%s) reserved doorbell: %d\n",
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client->ctx_index, yesno(is_high_priority(client)),
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client->stage_id, yesno(is_high_priority(client)),
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id);
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return 0;
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}
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@ -129,31 +129,31 @@ static void __unreserve_doorbell(struct i915_guc_client *client)
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* Tell the GuC to allocate or deallocate a specific doorbell
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*/
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static int __guc_allocate_doorbell(struct intel_guc *guc, u32 ctx_index)
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static int __guc_allocate_doorbell(struct intel_guc *guc, u32 stage_id)
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{
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u32 action[] = {
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INTEL_GUC_ACTION_ALLOCATE_DOORBELL,
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ctx_index
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stage_id
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};
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return intel_guc_send(guc, action, ARRAY_SIZE(action));
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}
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static int __guc_deallocate_doorbell(struct intel_guc *guc, u32 ctx_index)
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static int __guc_deallocate_doorbell(struct intel_guc *guc, u32 stage_id)
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{
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u32 action[] = {
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INTEL_GUC_ACTION_DEALLOCATE_DOORBELL,
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ctx_index
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stage_id
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};
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return intel_guc_send(guc, action, ARRAY_SIZE(action));
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}
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static struct guc_context_desc *__get_context_desc(struct i915_guc_client *client)
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static struct guc_stage_desc *__get_stage_desc(struct i915_guc_client *client)
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{
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struct guc_context_desc *base = client->guc->ctx_pool_vaddr;
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struct guc_stage_desc *base = client->guc->stage_desc_pool_vaddr;
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return &base[client->ctx_index];
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return &base[client->stage_id];
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}
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/*
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@ -165,10 +165,10 @@ static struct guc_context_desc *__get_context_desc(struct i915_guc_client *clien
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static void __update_doorbell_desc(struct i915_guc_client *client, u16 new_id)
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{
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struct guc_context_desc *desc;
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struct guc_stage_desc *desc;
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/* Update the GuC's idea of the doorbell ID */
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desc = __get_context_desc(client);
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desc = __get_stage_desc(client);
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desc->db_id = new_id;
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}
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@ -194,7 +194,7 @@ static int __create_doorbell(struct i915_guc_client *client)
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doorbell->db_status = GUC_DOORBELL_ENABLED;
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doorbell->cookie = client->doorbell_cookie;
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err = __guc_allocate_doorbell(client->guc, client->ctx_index);
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err = __guc_allocate_doorbell(client->guc, client->stage_id);
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if (err) {
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doorbell->db_status = GUC_DOORBELL_DISABLED;
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doorbell->cookie = 0;
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@ -220,7 +220,7 @@ static int __destroy_doorbell(struct i915_guc_client *client)
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if (wait_for_us(!(I915_READ(GEN8_DRBREGL(db_id)) & GEN8_DRB_VALID), 10))
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WARN_ONCE(true, "Doorbell never became invalid after disable\n");
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return __guc_deallocate_doorbell(client->guc, client->ctx_index);
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return __guc_deallocate_doorbell(client->guc, client->stage_id);
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}
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static int create_doorbell(struct i915_guc_client *client)
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@ -301,34 +301,34 @@ static void guc_proc_desc_init(struct intel_guc *guc,
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desc->wq_base_addr = 0;
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desc->db_base_addr = 0;
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desc->context_id = client->ctx_index;
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desc->stage_id = client->stage_id;
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desc->wq_size_bytes = client->wq_size;
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desc->wq_status = WQ_STATUS_ACTIVE;
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desc->priority = client->priority;
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}
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/*
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* Initialise/clear the context descriptor shared with the GuC firmware.
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* Initialise/clear the stage descriptor shared with the GuC firmware.
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*
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* This descriptor tells the GuC where (in GGTT space) to find the important
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* data structures relating to this client (doorbell, process descriptor,
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* write queue, etc).
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*/
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static void guc_ctx_desc_init(struct intel_guc *guc,
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struct i915_guc_client *client)
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static void guc_stage_desc_init(struct intel_guc *guc,
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struct i915_guc_client *client)
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{
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struct drm_i915_private *dev_priv = guc_to_i915(guc);
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struct intel_engine_cs *engine;
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struct i915_gem_context *ctx = client->owner;
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struct guc_context_desc *desc;
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struct guc_stage_desc *desc;
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unsigned int tmp;
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u32 gfx_addr;
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desc = __get_context_desc(client);
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desc = __get_stage_desc(client);
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memset(desc, 0, sizeof(*desc));
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desc->attribute = GUC_CTX_DESC_ATTR_ACTIVE | GUC_CTX_DESC_ATTR_KERNEL;
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desc->context_id = client->ctx_index;
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desc->attribute = GUC_STAGE_DESC_ATTR_ACTIVE | GUC_STAGE_DESC_ATTR_KERNEL;
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desc->stage_id = client->stage_id;
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desc->priority = client->priority;
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desc->db_id = client->doorbell_id;
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@ -348,7 +348,7 @@ static void guc_ctx_desc_init(struct intel_guc *guc,
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break; /* XXX: continue? */
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/*
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* XXX: When this is a GUC_CTX_DESC_ATTR_KERNEL client (proxy
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* XXX: When this is a GUC_STAGE_DESC_ATTR_KERNEL client (proxy
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* submission or, in other words, not using a direct submission
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* model) the KMD's LRCA is not used for any work submission.
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* Instead, the GuC uses the LRCA of the user mode context (see
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@ -359,7 +359,10 @@ static void guc_ctx_desc_init(struct intel_guc *guc,
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/* The state page is after PPHWSP */
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lrc->ring_lrca =
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guc_ggtt_offset(ce->state) + LRC_STATE_PN * PAGE_SIZE;
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lrc->context_id = (client->ctx_index << GUC_ELC_CTXID_OFFSET) |
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/* XXX: In direct submission, the GuC wants the HW context id
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* here. In proxy submission, it wants the stage id */
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lrc->context_id = (client->stage_id << GUC_ELC_CTXID_OFFSET) |
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(guc_engine_id << GUC_ELC_ENGINE_OFFSET);
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lrc->ring_begin = guc_ggtt_offset(ce->ring->vma);
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@ -390,12 +393,12 @@ static void guc_ctx_desc_init(struct intel_guc *guc,
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desc->desc_private = (uintptr_t)client;
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}
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static void guc_ctx_desc_fini(struct intel_guc *guc,
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struct i915_guc_client *client)
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static void guc_stage_desc_fini(struct intel_guc *guc,
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struct i915_guc_client *client)
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{
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struct guc_context_desc *desc;
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struct guc_stage_desc *desc;
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desc = __get_context_desc(client);
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desc = __get_stage_desc(client);
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memset(desc, 0, sizeof(*desc));
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}
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@ -863,7 +866,7 @@ static int guc_init_doorbell_hw(struct intel_guc *guc)
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ret = __create_doorbell(client);
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if (ret) {
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DRM_ERROR("Couldn't recreate client %u doorbell: %d\n",
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client->ctx_index, ret);
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client->stage_id, ret);
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return ret;
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}
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}
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@ -913,12 +916,12 @@ guc_client_alloc(struct drm_i915_private *dev_priv,
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client->wq_size = GUC_WQ_SIZE;
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spin_lock_init(&client->wq_lock);
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ret = ida_simple_get(&guc->ctx_ids, 0, GUC_MAX_GPU_CONTEXTS,
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ret = ida_simple_get(&guc->stage_ids, 0, GUC_MAX_STAGE_DESCRIPTORS,
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GFP_KERNEL);
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if (ret < 0)
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goto err_client;
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client->ctx_index = ret;
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client->stage_id = ret;
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/* The first page is doorbell/proc_desc. Two followed pages are wq. */
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vma = intel_guc_allocate_vma(guc, GUC_DB_SIZE + GUC_WQ_SIZE);
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@ -950,14 +953,14 @@ guc_client_alloc(struct drm_i915_private *dev_priv,
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client->proc_desc_offset = (GUC_DB_SIZE / 2);
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guc_proc_desc_init(guc, client);
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guc_ctx_desc_init(guc, client);
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guc_stage_desc_init(guc, client);
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ret = create_doorbell(client);
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if (ret)
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goto err_vaddr;
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DRM_DEBUG_DRIVER("new priority %u client %p for engine(s) 0x%x: ctx_index %u\n",
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priority, client, client->engines, client->ctx_index);
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DRM_DEBUG_DRIVER("new priority %u client %p for engine(s) 0x%x: stage_id %u\n",
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priority, client, client->engines, client->stage_id);
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DRM_DEBUG_DRIVER("doorbell id %u, cacheline offset 0x%lx\n",
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client->doorbell_id, client->doorbell_offset);
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@ -968,7 +971,7 @@ err_vaddr:
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err_vma:
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i915_vma_unpin_and_release(&client->vma);
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err_id:
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ida_simple_remove(&guc->ctx_ids, client->ctx_index);
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ida_simple_remove(&guc->stage_ids, client->stage_id);
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err_client:
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kfree(client);
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return ERR_PTR(ret);
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@ -985,10 +988,10 @@ static void guc_client_free(struct i915_guc_client *client)
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* reset, so we cannot destroy the doorbell properly. Ignore the
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* error message for now */
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destroy_doorbell(client);
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guc_ctx_desc_fini(client->guc, client);
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guc_stage_desc_fini(client->guc, client);
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i915_gem_object_unpin_map(client->vma->obj);
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i915_vma_unpin_and_release(&client->vma);
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ida_simple_remove(&client->guc->ctx_ids, client->ctx_index);
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ida_simple_remove(&client->guc->stage_ids, client->stage_id);
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kfree(client);
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}
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@ -1000,7 +1003,7 @@ static void guc_policies_init(struct guc_policies *policies)
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policies->dpc_promote_time = 500000;
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policies->max_num_work_items = POLICY_MAX_NUM_WI;
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for (p = 0; p < GUC_CTX_PRIORITY_NUM; p++) {
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for (p = 0; p < GUC_CLIENT_PRIORITY_NUM; p++) {
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for (i = GUC_RENDER_ENGINE; i < GUC_MAX_ENGINES_NUM; i++) {
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policy = &policies->policy[p][i];
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@ -1088,30 +1091,29 @@ static void guc_ads_destroy(struct intel_guc *guc)
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*/
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int i915_guc_submission_init(struct drm_i915_private *dev_priv)
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{
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const size_t ctxsize = sizeof(struct guc_context_desc);
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const size_t poolsize = GUC_MAX_GPU_CONTEXTS * ctxsize;
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const size_t gemsize = round_up(poolsize, PAGE_SIZE);
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struct intel_guc *guc = &dev_priv->guc;
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struct i915_vma *vma;
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void *vaddr;
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int ret;
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if (guc->ctx_pool)
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if (guc->stage_desc_pool)
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return 0;
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vma = intel_guc_allocate_vma(guc, gemsize);
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vma = intel_guc_allocate_vma(guc,
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PAGE_ALIGN(sizeof(struct guc_stage_desc) *
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GUC_MAX_STAGE_DESCRIPTORS));
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if (IS_ERR(vma))
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return PTR_ERR(vma);
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guc->ctx_pool = vma;
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guc->stage_desc_pool = vma;
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vaddr = i915_gem_object_pin_map(guc->ctx_pool->obj, I915_MAP_WB);
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vaddr = i915_gem_object_pin_map(guc->stage_desc_pool->obj, I915_MAP_WB);
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if (IS_ERR(vaddr)) {
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ret = PTR_ERR(vaddr);
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goto err_vma;
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}
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guc->ctx_pool_vaddr = vaddr;
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guc->stage_desc_pool_vaddr = vaddr;
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ret = intel_guc_log_create(guc);
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if (ret < 0)
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@ -1121,16 +1123,16 @@ int i915_guc_submission_init(struct drm_i915_private *dev_priv)
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if (ret < 0)
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goto err_log;
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ida_init(&guc->ctx_ids);
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ida_init(&guc->stage_ids);
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return 0;
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err_log:
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intel_guc_log_destroy(guc);
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err_vaddr:
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i915_gem_object_unpin_map(guc->ctx_pool->obj);
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i915_gem_object_unpin_map(guc->stage_desc_pool->obj);
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err_vma:
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i915_vma_unpin_and_release(&guc->ctx_pool);
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i915_vma_unpin_and_release(&guc->stage_desc_pool);
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return ret;
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}
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@ -1138,11 +1140,11 @@ void i915_guc_submission_fini(struct drm_i915_private *dev_priv)
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{
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struct intel_guc *guc = &dev_priv->guc;
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ida_destroy(&guc->ctx_ids);
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ida_destroy(&guc->stage_ids);
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guc_ads_destroy(guc);
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intel_guc_log_destroy(guc);
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i915_gem_object_unpin_map(guc->ctx_pool->obj);
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i915_vma_unpin_and_release(&guc->ctx_pool);
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i915_gem_object_unpin_map(guc->stage_desc_pool->obj);
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i915_vma_unpin_and_release(&guc->stage_desc_pool);
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}
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static void guc_interrupts_capture(struct drm_i915_private *dev_priv)
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@ -1198,7 +1200,7 @@ int i915_guc_submission_enable(struct drm_i915_private *dev_priv)
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if (!client) {
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client = guc_client_alloc(dev_priv,
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INTEL_INFO(dev_priv)->ring_mask,
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GUC_CTX_PRIORITY_KMD_NORMAL,
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GUC_CLIENT_PRIORITY_KMD_NORMAL,
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dev_priv->kernel_context);
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if (IS_ERR(client)) {
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DRM_ERROR("Failed to create GuC client for execbuf!\n");
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@ -26,14 +26,14 @@
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#define GFXCORE_FAMILY_GEN9 12
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#define GFXCORE_FAMILY_UNKNOWN 0x7fffffff
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#define GUC_CTX_PRIORITY_KMD_HIGH 0
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#define GUC_CTX_PRIORITY_HIGH 1
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#define GUC_CTX_PRIORITY_KMD_NORMAL 2
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#define GUC_CTX_PRIORITY_NORMAL 3
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#define GUC_CTX_PRIORITY_NUM 4
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#define GUC_CLIENT_PRIORITY_KMD_HIGH 0
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#define GUC_CLIENT_PRIORITY_HIGH 1
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#define GUC_CLIENT_PRIORITY_KMD_NORMAL 2
|
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#define GUC_CLIENT_PRIORITY_NORMAL 3
|
||||
#define GUC_CLIENT_PRIORITY_NUM 4
|
||||
|
||||
#define GUC_MAX_GPU_CONTEXTS 1024
|
||||
#define GUC_INVALID_CTX_ID GUC_MAX_GPU_CONTEXTS
|
||||
#define GUC_MAX_STAGE_DESCRIPTORS 1024
|
||||
#define GUC_INVALID_STAGE_ID GUC_MAX_STAGE_DESCRIPTORS
|
||||
|
||||
#define GUC_RENDER_ENGINE 0
|
||||
#define GUC_VIDEO_ENGINE 1
|
||||
|
@ -68,14 +68,14 @@
|
|||
#define GUC_DOORBELL_ENABLED 1
|
||||
#define GUC_DOORBELL_DISABLED 0
|
||||
|
||||
#define GUC_CTX_DESC_ATTR_ACTIVE (1 << 0)
|
||||
#define GUC_CTX_DESC_ATTR_PENDING_DB (1 << 1)
|
||||
#define GUC_CTX_DESC_ATTR_KERNEL (1 << 2)
|
||||
#define GUC_CTX_DESC_ATTR_PREEMPT (1 << 3)
|
||||
#define GUC_CTX_DESC_ATTR_RESET (1 << 4)
|
||||
#define GUC_CTX_DESC_ATTR_WQLOCKED (1 << 5)
|
||||
#define GUC_CTX_DESC_ATTR_PCH (1 << 6)
|
||||
#define GUC_CTX_DESC_ATTR_TERMINATED (1 << 7)
|
||||
#define GUC_STAGE_DESC_ATTR_ACTIVE BIT(0)
|
||||
#define GUC_STAGE_DESC_ATTR_PENDING_DB BIT(1)
|
||||
#define GUC_STAGE_DESC_ATTR_KERNEL BIT(2)
|
||||
#define GUC_STAGE_DESC_ATTR_PREEMPT BIT(3)
|
||||
#define GUC_STAGE_DESC_ATTR_RESET BIT(4)
|
||||
#define GUC_STAGE_DESC_ATTR_WQLOCKED BIT(5)
|
||||
#define GUC_STAGE_DESC_ATTR_PCH BIT(6)
|
||||
#define GUC_STAGE_DESC_ATTR_TERMINATED BIT(7)
|
||||
|
||||
/* The guc control data is 10 DWORDs */
|
||||
#define GUC_CTL_CTXINFO 0
|
||||
|
@ -256,7 +256,7 @@ struct guc_wq_item {
|
|||
} __packed;
|
||||
|
||||
struct guc_process_desc {
|
||||
u32 context_id;
|
||||
u32 stage_id;
|
||||
u64 db_base_addr;
|
||||
u32 head;
|
||||
u32 tail;
|
||||
|
@ -289,10 +289,18 @@ struct guc_execlist_context {
|
|||
u16 engine_submit_queue_count;
|
||||
} __packed;
|
||||
|
||||
/*Context descriptor for communicating between uKernel and Driver*/
|
||||
struct guc_context_desc {
|
||||
/*
|
||||
* This structure describes a stage set arranged for a particular communication
|
||||
* between uKernel (GuC) and Driver (KMD). Technically, this is known as a
|
||||
* "GuC Context descriptor" in the specs, but we use the term "stage descriptor"
|
||||
* to avoid confusion with all the other things already named "context" in the
|
||||
* driver. A static pool of these descriptors are stored inside a GEM object
|
||||
* (stage_desc_pool) which is held for the entire lifetime of our interaction
|
||||
* with the GuC, being allocated before the GuC is loaded with its firmware.
|
||||
*/
|
||||
struct guc_stage_desc {
|
||||
u32 sched_common_area;
|
||||
u32 context_id;
|
||||
u32 stage_id;
|
||||
u32 pas_id;
|
||||
u8 engines_used;
|
||||
u64 db_trigger_cpu;
|
||||
|
@ -359,7 +367,7 @@ struct guc_policy {
|
|||
} __packed;
|
||||
|
||||
struct guc_policies {
|
||||
struct guc_policy policy[GUC_CTX_PRIORITY_NUM][GUC_MAX_ENGINES_NUM];
|
||||
struct guc_policy policy[GUC_CLIENT_PRIORITY_NUM][GUC_MAX_ENGINES_NUM];
|
||||
|
||||
/* In micro seconds. How much time to allow before DPC processing is
|
||||
* called back via interrupt (to prevent DPC queue drain starving).
|
||||
|
|
|
@ -151,8 +151,8 @@ static void guc_params_init(struct drm_i915_private *dev_priv)
|
|||
/* If GuC submission is enabled, set up additional parameters here */
|
||||
if (i915.enable_guc_submission) {
|
||||
u32 ads = guc_ggtt_offset(guc->ads_vma) >> PAGE_SHIFT;
|
||||
u32 pgs = guc_ggtt_offset(dev_priv->guc.ctx_pool);
|
||||
u32 ctx_in_16 = GUC_MAX_GPU_CONTEXTS / 16;
|
||||
u32 pgs = guc_ggtt_offset(dev_priv->guc.stage_desc_pool);
|
||||
u32 ctx_in_16 = GUC_MAX_STAGE_DESCRIPTORS / 16;
|
||||
|
||||
params[GUC_CTL_DEBUG] |= ads << GUC_ADS_ADDR_SHIFT;
|
||||
params[GUC_CTL_DEBUG] |= GUC_ADS_ENABLED;
|
||||
|
|
|
@ -74,7 +74,7 @@ struct i915_guc_client {
|
|||
|
||||
uint32_t engines; /* bitmap of (host) engine ids */
|
||||
uint32_t priority;
|
||||
u32 ctx_index;
|
||||
u32 stage_id;
|
||||
uint32_t proc_desc_offset;
|
||||
|
||||
u16 doorbell_id;
|
||||
|
@ -157,9 +157,9 @@ struct intel_guc {
|
|||
bool interrupts_enabled;
|
||||
|
||||
struct i915_vma *ads_vma;
|
||||
struct i915_vma *ctx_pool;
|
||||
void *ctx_pool_vaddr;
|
||||
struct ida ctx_ids;
|
||||
struct i915_vma *stage_desc_pool;
|
||||
void *stage_desc_pool_vaddr;
|
||||
struct ida stage_ids;
|
||||
|
||||
struct i915_guc_client *execbuf_client;
|
||||
|
||||
|
|
Loading…
Reference in a new issue