Merge branch 'devel-stable' into for-linus
Conflicts: arch/arm/Kconfig.debug arch/arm/plat-versatile/Kconfig Merge fixes: arch/arm/mach-integrator/Kconfig drivers/clocksource/Kconfig
This commit is contained in:
commit
b0df898680
|
@ -30,7 +30,6 @@ config ARM
|
|||
select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
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||||
select HAVE_C_RECORDMCOUNT
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||||
select HAVE_GENERIC_HARDIRQS
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||||
select HAVE_SPARSE_IRQ
|
||||
select GENERIC_IRQ_SHOW
|
||||
select CPU_PM if (SUSPEND || CPU_IDLE)
|
||||
select GENERIC_PCI_IOMAP
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||||
|
@ -55,9 +54,6 @@ config MIGHT_HAVE_PCI
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config SYS_SUPPORTS_APM_EMULATION
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||||
bool
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||||
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||||
config HAVE_SCHED_CLOCK
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||||
bool
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||||
|
||||
config GENERIC_GPIO
|
||||
bool
|
||||
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||||
|
@ -355,6 +351,7 @@ config ARCH_HIGHBANK
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|||
select GENERIC_CLOCKEVENTS
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||||
select HAVE_ARM_SCU
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||||
select HAVE_SMP
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select SPARSE_IRQ
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||||
select USE_OF
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||||
help
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||||
Support for the Calxeda Highbank SoC based boards.
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||||
|
@ -443,7 +440,6 @@ config ARCH_MXC
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|||
select CLKDEV_LOOKUP
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select CLKSRC_MMIO
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select GENERIC_IRQ_CHIP
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select HAVE_SCHED_CLOCK
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select MULTI_IRQ_HANDLER
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help
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||||
Support for Freescale MXC/iMX-based family of processors
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||||
|
@ -535,7 +531,6 @@ config ARCH_IXP4XX
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select CPU_XSCALE
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select GENERIC_GPIO
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select GENERIC_CLOCKEVENTS
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select HAVE_SCHED_CLOCK
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select MIGHT_HAVE_PCI
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select DMABOUNCE if PCI
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||||
help
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||||
|
@ -606,7 +601,6 @@ config ARCH_MMP
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select CLKDEV_LOOKUP
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select GENERIC_CLOCKEVENTS
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select GPIO_PXA
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select HAVE_SCHED_CLOCK
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select TICK_ONESHOT
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select PLAT_PXA
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select SPARSE_IRQ
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|
@ -647,7 +641,6 @@ config ARCH_TEGRA
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select GENERIC_CLOCKEVENTS
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select GENERIC_GPIO
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select HAVE_CLK
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select HAVE_SCHED_CLOCK
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select HAVE_SMP
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select MIGHT_HAVE_CACHE_L2X0
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select ARCH_HAS_CPUFREQ
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@ -664,7 +657,6 @@ config ARCH_PICOXCELL
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select DW_APB_TIMER
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select GENERIC_CLOCKEVENTS
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select GENERIC_GPIO
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select HAVE_SCHED_CLOCK
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select HAVE_TCM
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select NO_IOPORT
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select SPARSE_IRQ
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@ -692,7 +684,6 @@ config ARCH_PXA
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select ARCH_REQUIRE_GPIOLIB
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select GENERIC_CLOCKEVENTS
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select GPIO_PXA
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select HAVE_SCHED_CLOCK
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select TICK_ONESHOT
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select PLAT_PXA
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select SPARSE_IRQ
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@ -760,7 +751,6 @@ config ARCH_SA1100
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select CPU_FREQ
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select GENERIC_CLOCKEVENTS
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select CLKDEV_LOOKUP
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select HAVE_SCHED_CLOCK
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select TICK_ONESHOT
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select ARCH_REQUIRE_GPIOLIB
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||||
select HAVE_IDE
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@ -817,7 +807,6 @@ config ARCH_S5P64X0
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select CLKSRC_MMIO
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select HAVE_S3C2410_WATCHDOG if WATCHDOG
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select GENERIC_CLOCKEVENTS
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||||
select HAVE_SCHED_CLOCK
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select HAVE_S3C2410_I2C if I2C
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select HAVE_S3C_RTC if RTC_CLASS
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||||
help
|
||||
|
@ -850,7 +839,6 @@ config ARCH_S5PV210
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|||
select ARM_L1_CACHE_SHIFT_6
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||||
select ARCH_HAS_CPUFREQ
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||||
select GENERIC_CLOCKEVENTS
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||||
select HAVE_SCHED_CLOCK
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||||
select HAVE_S3C2410_I2C if I2C
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||||
select HAVE_S3C_RTC if RTC_CLASS
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||||
select HAVE_S3C2410_WATCHDOG if WATCHDOG
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||||
|
@ -893,7 +881,6 @@ config ARCH_U300
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|||
depends on MMU
|
||||
select CLKSRC_MMIO
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||||
select CPU_ARM926T
|
||||
select HAVE_SCHED_CLOCK
|
||||
select HAVE_TCM
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||||
select ARM_AMBA
|
||||
select ARM_PATCH_PHYS_VIRT
|
||||
|
@ -951,7 +938,6 @@ config ARCH_OMAP
|
|||
select ARCH_HAS_CPUFREQ
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||||
select CLKSRC_MMIO
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||||
select GENERIC_CLOCKEVENTS
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||||
select HAVE_SCHED_CLOCK
|
||||
select ARCH_HAS_HOLES_MEMORYMODEL
|
||||
help
|
||||
Support for TI's OMAP platform (OMAP1/2/3/4).
|
||||
|
@ -1117,13 +1103,11 @@ config ARCH_ACORN
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|||
config PLAT_IOP
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||||
bool
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||||
select GENERIC_CLOCKEVENTS
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||||
select HAVE_SCHED_CLOCK
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||||
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||||
config PLAT_ORION
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||||
bool
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||||
select CLKSRC_MMIO
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||||
select GENERIC_IRQ_CHIP
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||||
select HAVE_SCHED_CLOCK
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||||
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||||
config PLAT_PXA
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bool
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||||
|
|
|
@ -81,41 +81,6 @@ choice
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|||
prompt "Kernel low-level debugging port"
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||||
depends on DEBUG_LL
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||||
|
||||
config DEBUG_LL_UART_NONE
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||||
bool "No low-level debugging UART"
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||||
help
|
||||
Say Y here if your platform doesn't provide a UART option
|
||||
below. This relies on your platform choosing the right UART
|
||||
definition internally in order for low-level debugging to
|
||||
work.
|
||||
|
||||
config DEBUG_ICEDCC
|
||||
bool "Kernel low-level debugging via EmbeddedICE DCC channel"
|
||||
help
|
||||
Say Y here if you want the debug print routines to direct
|
||||
their output to the EmbeddedICE macrocell's DCC channel using
|
||||
co-processor 14. This is known to work on the ARM9 style ICE
|
||||
channel and on the XScale with the PEEDI.
|
||||
|
||||
Note that the system will appear to hang during boot if there
|
||||
is nothing connected to read from the DCC.
|
||||
|
||||
config DEBUG_SEMIHOSTING
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||||
bool "Kernel low-level debug output via semihosting I"
|
||||
help
|
||||
Semihosting enables code running on an ARM target to use
|
||||
the I/O facilities on a host debugger/emulator through a
|
||||
simple SVC calls. The host debugger or emulator must have
|
||||
semihosting enabled for the special svc call to be trapped
|
||||
otherwise the kernel will crash.
|
||||
|
||||
This is known to work with OpenOCD, as wellas
|
||||
ARM's Fast Models, or any other controlling environment
|
||||
that implements semihosting.
|
||||
|
||||
For more details about semihosting, please see
|
||||
chapter 8 of DUI0203I_rvct_developer_guide.pdf from ARM Ltd.
|
||||
|
||||
config AT91_DEBUG_LL_DBGU0
|
||||
bool "Kernel low-level debugging on rm9200, 9260/9g20, 9261/9g10 and 9rl"
|
||||
depends on HAVE_AT91_DBGU0
|
||||
|
@ -124,20 +89,6 @@ choice
|
|||
bool "Kernel low-level debugging on 9263, 9g45 and cap9"
|
||||
depends on HAVE_AT91_DBGU1
|
||||
|
||||
config DEBUG_FOOTBRIDGE_COM1
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||||
bool "Kernel low-level debugging messages via footbridge 8250 at PCI COM1"
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||||
depends on FOOTBRIDGE
|
||||
help
|
||||
Say Y here if you want the debug print routines to direct
|
||||
their output to the 8250 at PCI COM1.
|
||||
|
||||
config DEBUG_DC21285_PORT
|
||||
bool "Kernel low-level debugging messages via footbridge serial port"
|
||||
depends on FOOTBRIDGE
|
||||
help
|
||||
Say Y here if you want the debug print routines to direct
|
||||
their output to the serial port in the DC21285 (Footbridge).
|
||||
|
||||
config DEBUG_CLPS711X_UART1
|
||||
bool "Kernel low-level debugging messages via UART1"
|
||||
depends on ARCH_CLPS711X
|
||||
|
@ -152,6 +103,20 @@ choice
|
|||
Say Y here if you want the debug print routines to direct
|
||||
their output to the second serial port on these devices.
|
||||
|
||||
config DEBUG_DC21285_PORT
|
||||
bool "Kernel low-level debugging messages via footbridge serial port"
|
||||
depends on FOOTBRIDGE
|
||||
help
|
||||
Say Y here if you want the debug print routines to direct
|
||||
their output to the serial port in the DC21285 (Footbridge).
|
||||
|
||||
config DEBUG_FOOTBRIDGE_COM1
|
||||
bool "Kernel low-level debugging messages via footbridge 8250 at PCI COM1"
|
||||
depends on FOOTBRIDGE
|
||||
help
|
||||
Say Y here if you want the debug print routines to direct
|
||||
their output to the 8250 at PCI COM1.
|
||||
|
||||
config DEBUG_HIGHBANK_UART
|
||||
bool "Kernel low-level debugging messages via Highbank UART"
|
||||
depends on ARCH_HIGHBANK
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||||
|
@ -222,55 +187,6 @@ choice
|
|||
Say Y here if you want kernel low-level debugging support
|
||||
on i.MX6Q.
|
||||
|
||||
config DEBUG_S3C_UART0
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||||
depends on PLAT_SAMSUNG
|
||||
bool "Use S3C UART 0 for low-level debug"
|
||||
help
|
||||
Say Y here if you want the debug print routines to direct
|
||||
their output to UART 0. The port must have been initialised
|
||||
by the boot-loader before use.
|
||||
|
||||
The uncompressor code port configuration is now handled
|
||||
by CONFIG_S3C_LOWLEVEL_UART_PORT.
|
||||
|
||||
config DEBUG_S3C_UART1
|
||||
depends on PLAT_SAMSUNG
|
||||
bool "Use S3C UART 1 for low-level debug"
|
||||
help
|
||||
Say Y here if you want the debug print routines to direct
|
||||
their output to UART 1. The port must have been initialised
|
||||
by the boot-loader before use.
|
||||
|
||||
The uncompressor code port configuration is now handled
|
||||
by CONFIG_S3C_LOWLEVEL_UART_PORT.
|
||||
|
||||
config DEBUG_S3C_UART2
|
||||
depends on PLAT_SAMSUNG
|
||||
bool "Use S3C UART 2 for low-level debug"
|
||||
help
|
||||
Say Y here if you want the debug print routines to direct
|
||||
their output to UART 2. The port must have been initialised
|
||||
by the boot-loader before use.
|
||||
|
||||
The uncompressor code port configuration is now handled
|
||||
by CONFIG_S3C_LOWLEVEL_UART_PORT.
|
||||
|
||||
config DEBUG_REALVIEW_STD_PORT
|
||||
bool "RealView Default UART"
|
||||
depends on ARCH_REALVIEW
|
||||
help
|
||||
Say Y here if you want the debug print routines to direct
|
||||
their output to the serial port on RealView EB, PB11MP, PBA8
|
||||
and PBX platforms.
|
||||
|
||||
config DEBUG_REALVIEW_PB1176_PORT
|
||||
bool "RealView PB1176 UART"
|
||||
depends on MACH_REALVIEW_PB1176
|
||||
help
|
||||
Say Y here if you want the debug print routines to direct
|
||||
their output to the standard serial port on the RealView
|
||||
PB1176 platform.
|
||||
|
||||
config DEBUG_MSM_UART1
|
||||
bool "Kernel low-level debugging messages via MSM UART1"
|
||||
depends on ARCH_MSM7X00A || ARCH_MSM7X30 || ARCH_QSD8X50
|
||||
|
@ -308,6 +224,90 @@ choice
|
|||
Say Y here if you want the debug print routines to direct
|
||||
their output to the serial port on MSM 8960 devices.
|
||||
|
||||
config DEBUG_REALVIEW_STD_PORT
|
||||
bool "RealView Default UART"
|
||||
depends on ARCH_REALVIEW
|
||||
help
|
||||
Say Y here if you want the debug print routines to direct
|
||||
their output to the serial port on RealView EB, PB11MP, PBA8
|
||||
and PBX platforms.
|
||||
|
||||
config DEBUG_REALVIEW_PB1176_PORT
|
||||
bool "RealView PB1176 UART"
|
||||
depends on MACH_REALVIEW_PB1176
|
||||
help
|
||||
Say Y here if you want the debug print routines to direct
|
||||
their output to the standard serial port on the RealView
|
||||
PB1176 platform.
|
||||
|
||||
config DEBUG_S3C_UART0
|
||||
depends on PLAT_SAMSUNG
|
||||
bool "Use S3C UART 0 for low-level debug"
|
||||
help
|
||||
Say Y here if you want the debug print routines to direct
|
||||
their output to UART 0. The port must have been initialised
|
||||
by the boot-loader before use.
|
||||
|
||||
The uncompressor code port configuration is now handled
|
||||
by CONFIG_S3C_LOWLEVEL_UART_PORT.
|
||||
|
||||
config DEBUG_S3C_UART1
|
||||
depends on PLAT_SAMSUNG
|
||||
bool "Use S3C UART 1 for low-level debug"
|
||||
help
|
||||
Say Y here if you want the debug print routines to direct
|
||||
their output to UART 1. The port must have been initialised
|
||||
by the boot-loader before use.
|
||||
|
||||
The uncompressor code port configuration is now handled
|
||||
by CONFIG_S3C_LOWLEVEL_UART_PORT.
|
||||
|
||||
config DEBUG_S3C_UART2
|
||||
depends on PLAT_SAMSUNG
|
||||
bool "Use S3C UART 2 for low-level debug"
|
||||
help
|
||||
Say Y here if you want the debug print routines to direct
|
||||
their output to UART 2. The port must have been initialised
|
||||
by the boot-loader before use.
|
||||
|
||||
The uncompressor code port configuration is now handled
|
||||
by CONFIG_S3C_LOWLEVEL_UART_PORT.
|
||||
|
||||
config DEBUG_LL_UART_NONE
|
||||
bool "No low-level debugging UART"
|
||||
help
|
||||
Say Y here if your platform doesn't provide a UART option
|
||||
below. This relies on your platform choosing the right UART
|
||||
definition internally in order for low-level debugging to
|
||||
work.
|
||||
|
||||
config DEBUG_ICEDCC
|
||||
bool "Kernel low-level debugging via EmbeddedICE DCC channel"
|
||||
help
|
||||
Say Y here if you want the debug print routines to direct
|
||||
their output to the EmbeddedICE macrocell's DCC channel using
|
||||
co-processor 14. This is known to work on the ARM9 style ICE
|
||||
channel and on the XScale with the PEEDI.
|
||||
|
||||
Note that the system will appear to hang during boot if there
|
||||
is nothing connected to read from the DCC.
|
||||
|
||||
config DEBUG_SEMIHOSTING
|
||||
bool "Kernel low-level debug output via semihosting I"
|
||||
help
|
||||
Semihosting enables code running on an ARM target to use
|
||||
the I/O facilities on a host debugger/emulator through a
|
||||
simple SVC calls. The host debugger or emulator must have
|
||||
semihosting enabled for the special svc call to be trapped
|
||||
otherwise the kernel will crash.
|
||||
|
||||
This is known to work with OpenOCD, as wellas
|
||||
ARM's Fast Models, or any other controlling environment
|
||||
that implements semihosting.
|
||||
|
||||
For more details about semihosting, please see
|
||||
chapter 8 of DUI0203I_rvct_developer_guide.pdf from ARM Ltd.
|
||||
|
||||
endchoice
|
||||
|
||||
config EARLY_PRINTK
|
||||
|
|
|
@ -9,6 +9,9 @@
|
|||
|
||||
#ifndef __ASM_HARDWARE_IT8152_H
|
||||
#define __ASM_HARDWARE_IT8152_H
|
||||
|
||||
#include <mach/irqs.h>
|
||||
|
||||
extern void __iomem *it8152_base_address;
|
||||
|
||||
#define IT8152_IO_BASE (it8152_base_address + 0x03e00000)
|
||||
|
|
|
@ -1,14 +1,18 @@
|
|||
#ifndef __ASM_ARM_IRQ_H
|
||||
#define __ASM_ARM_IRQ_H
|
||||
|
||||
#define NR_IRQS_LEGACY 16
|
||||
|
||||
#ifndef CONFIG_SPARSE_IRQ
|
||||
#include <mach/irqs.h>
|
||||
#else
|
||||
#define NR_IRQS NR_IRQS_LEGACY
|
||||
#endif
|
||||
|
||||
#ifndef irq_canonicalize
|
||||
#define irq_canonicalize(i) (i)
|
||||
#endif
|
||||
|
||||
#define NR_IRQS_LEGACY 16
|
||||
|
||||
/*
|
||||
* Use this value to indicate lack of interrupt
|
||||
* capability
|
||||
|
|
|
@ -5,7 +5,9 @@
|
|||
#define _ASM_MC146818RTC_H
|
||||
|
||||
#include <linux/io.h>
|
||||
#include <mach/irqs.h>
|
||||
#include <linux/kernel.h>
|
||||
|
||||
#define RTC_IRQ BUILD_BUG_ON(1)
|
||||
|
||||
#ifndef RTC_PORT
|
||||
#define RTC_PORT(x) (0x70 + (x))
|
||||
|
|
|
@ -79,6 +79,7 @@ extern void cpu_init(void);
|
|||
|
||||
void soft_restart(unsigned long);
|
||||
extern void (*arm_pm_restart)(char str, const char *cmd);
|
||||
extern void (*arm_pm_idle)(void);
|
||||
|
||||
#define UDBG_UNDEFINED (1 << 0)
|
||||
#define UDBG_SYSCALL (1 << 1)
|
||||
|
|
|
@ -16,8 +16,8 @@ CFLAGS_REMOVE_return_address.o = -pg
|
|||
# Object file lists.
|
||||
|
||||
obj-y := elf.o entry-armv.o entry-common.o irq.o opcodes.o \
|
||||
process.o ptrace.o return_address.o setup.o signal.o \
|
||||
sys_arm.o stacktrace.o time.o traps.o
|
||||
process.o ptrace.o return_address.o sched_clock.o \
|
||||
setup.o signal.o stacktrace.o sys_arm.o time.o traps.o
|
||||
|
||||
obj-$(CONFIG_DEPRECATED_PARAM_STRUCT) += compat.o
|
||||
|
||||
|
@ -32,7 +32,6 @@ obj-$(CONFIG_ARTHUR) += arthur.o
|
|||
obj-$(CONFIG_ISA_DMA) += dma-isa.o
|
||||
obj-$(CONFIG_PCI) += bios32.o isa.o
|
||||
obj-$(CONFIG_ARM_CPU_SUSPEND) += sleep.o suspend.o
|
||||
obj-$(CONFIG_HAVE_SCHED_CLOCK) += sched_clock.o
|
||||
obj-$(CONFIG_SMP) += smp.o smp_tlb.o
|
||||
obj-$(CONFIG_HAVE_ARM_SCU) += smp_scu.o
|
||||
obj-$(CONFIG_HAVE_ARM_TWD) += smp_twd.o
|
||||
|
|
|
@ -61,8 +61,6 @@ extern void setup_mm_for_reboot(void);
|
|||
|
||||
static volatile int hlt_counter;
|
||||
|
||||
#include <mach/system.h>
|
||||
|
||||
void disable_hlt(void)
|
||||
{
|
||||
hlt_counter++;
|
||||
|
@ -181,13 +179,17 @@ void cpu_idle_wait(void)
|
|||
EXPORT_SYMBOL_GPL(cpu_idle_wait);
|
||||
|
||||
/*
|
||||
* This is our default idle handler. We need to disable
|
||||
* interrupts here to ensure we don't miss a wakeup call.
|
||||
* This is our default idle handler.
|
||||
*/
|
||||
|
||||
void (*arm_pm_idle)(void);
|
||||
|
||||
static void default_idle(void)
|
||||
{
|
||||
if (!need_resched())
|
||||
arch_idle();
|
||||
if (arm_pm_idle)
|
||||
arm_pm_idle();
|
||||
else
|
||||
cpu_do_idle();
|
||||
local_irq_enable();
|
||||
}
|
||||
|
||||
|
@ -215,6 +217,10 @@ void cpu_idle(void)
|
|||
cpu_die();
|
||||
#endif
|
||||
|
||||
/*
|
||||
* We need to disable interrupts here
|
||||
* to ensure we don't miss a wakeup call.
|
||||
*/
|
||||
local_irq_disable();
|
||||
#ifdef CONFIG_PL310_ERRATA_769419
|
||||
wmb();
|
||||
|
@ -222,19 +228,18 @@ void cpu_idle(void)
|
|||
if (hlt_counter) {
|
||||
local_irq_enable();
|
||||
cpu_relax();
|
||||
} else {
|
||||
} else if (!need_resched()) {
|
||||
stop_critical_timings();
|
||||
if (cpuidle_idle_call())
|
||||
pm_idle();
|
||||
start_critical_timings();
|
||||
/*
|
||||
* This will eventually be removed - pm_idle
|
||||
* functions should always return with IRQs
|
||||
* enabled.
|
||||
* pm_idle functions must always
|
||||
* return with IRQs enabled.
|
||||
*/
|
||||
WARN_ON(irqs_disabled());
|
||||
} else
|
||||
local_irq_enable();
|
||||
}
|
||||
}
|
||||
leds_event(led_idle_end);
|
||||
rcu_idle_exit();
|
||||
|
|
|
@ -25,8 +25,6 @@
|
|||
#include <linux/timer.h>
|
||||
#include <linux/irq.h>
|
||||
|
||||
#include <linux/mc146818rtc.h>
|
||||
|
||||
#include <asm/leds.h>
|
||||
#include <asm/thread_info.h>
|
||||
#include <asm/sched_clock.h>
|
||||
|
@ -149,8 +147,6 @@ void __init time_init(void)
|
|||
{
|
||||
system_timer = machine_desc->timer;
|
||||
system_timer->init();
|
||||
#ifdef CONFIG_HAVE_SCHED_CLOCK
|
||||
sched_clock_postinit();
|
||||
#endif
|
||||
}
|
||||
|
||||
|
|
|
@ -14,6 +14,7 @@
|
|||
|
||||
#include <linux/module.h>
|
||||
|
||||
#include <asm/proc-fns.h>
|
||||
#include <asm/irq.h>
|
||||
#include <asm/mach/arch.h>
|
||||
#include <asm/mach/map.h>
|
||||
|
@ -314,6 +315,12 @@ static struct at91_gpio_bank at91cap9_gpio[] __initdata = {
|
|||
}
|
||||
};
|
||||
|
||||
static void at91cap9_idle(void)
|
||||
{
|
||||
at91_sys_write(AT91_PMC_SCDR, AT91_PMC_PCK);
|
||||
cpu_do_idle();
|
||||
}
|
||||
|
||||
static void at91cap9_restart(char mode, const char *cmd)
|
||||
{
|
||||
at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_PROCRST | AT91_RSTC_PERRST);
|
||||
|
@ -337,6 +344,7 @@ static void __init at91cap9_ioremap_registers(void)
|
|||
|
||||
static void __init at91cap9_initialize(void)
|
||||
{
|
||||
arm_pm_idle = at91cap9_idle;
|
||||
arm_pm_restart = at91cap9_restart;
|
||||
at91_extern_irq = (1 << AT91CAP9_ID_IRQ0) | (1 << AT91CAP9_ID_IRQ1);
|
||||
|
||||
|
|
|
@ -289,6 +289,15 @@ static struct at91_gpio_bank at91rm9200_gpio[] __initdata = {
|
|||
}
|
||||
};
|
||||
|
||||
static void at91rm9200_idle(void)
|
||||
{
|
||||
/*
|
||||
* Disable the processor clock. The processor will be automatically
|
||||
* re-enabled by an interrupt or by a reset.
|
||||
*/
|
||||
at91_sys_write(AT91_PMC_SCDR, AT91_PMC_PCK);
|
||||
}
|
||||
|
||||
static void at91rm9200_restart(char mode, const char *cmd)
|
||||
{
|
||||
/*
|
||||
|
@ -314,6 +323,7 @@ static void __init at91rm9200_ioremap_registers(void)
|
|||
|
||||
static void __init at91rm9200_initialize(void)
|
||||
{
|
||||
arm_pm_idle = at91rm9200_idle;
|
||||
arm_pm_restart = at91rm9200_restart;
|
||||
at91_extern_irq = (1 << AT91RM9200_ID_IRQ0) | (1 << AT91RM9200_ID_IRQ1)
|
||||
| (1 << AT91RM9200_ID_IRQ2) | (1 << AT91RM9200_ID_IRQ3)
|
||||
|
|
|
@ -12,6 +12,7 @@
|
|||
|
||||
#include <linux/module.h>
|
||||
|
||||
#include <asm/proc-fns.h>
|
||||
#include <asm/irq.h>
|
||||
#include <asm/mach/arch.h>
|
||||
#include <asm/mach/map.h>
|
||||
|
@ -327,8 +328,15 @@ static void __init at91sam9260_ioremap_registers(void)
|
|||
at91sam9_ioremap_smc(0, AT91SAM9260_BASE_SMC);
|
||||
}
|
||||
|
||||
static void at91sam9260_idle(void)
|
||||
{
|
||||
at91_sys_write(AT91_PMC_SCDR, AT91_PMC_PCK);
|
||||
cpu_do_idle();
|
||||
}
|
||||
|
||||
static void __init at91sam9260_initialize(void)
|
||||
{
|
||||
arm_pm_idle = at91sam9260_idle;
|
||||
arm_pm_restart = at91sam9_alt_restart;
|
||||
at91_extern_irq = (1 << AT91SAM9260_ID_IRQ0) | (1 << AT91SAM9260_ID_IRQ1)
|
||||
| (1 << AT91SAM9260_ID_IRQ2);
|
||||
|
|
|
@ -12,6 +12,7 @@
|
|||
|
||||
#include <linux/module.h>
|
||||
|
||||
#include <asm/proc-fns.h>
|
||||
#include <asm/irq.h>
|
||||
#include <asm/mach/arch.h>
|
||||
#include <asm/mach/map.h>
|
||||
|
@ -285,8 +286,15 @@ static void __init at91sam9261_ioremap_registers(void)
|
|||
at91sam9_ioremap_smc(0, AT91SAM9261_BASE_SMC);
|
||||
}
|
||||
|
||||
static void at91sam9261_idle(void)
|
||||
{
|
||||
at91_sys_write(AT91_PMC_SCDR, AT91_PMC_PCK);
|
||||
cpu_do_idle();
|
||||
}
|
||||
|
||||
static void __init at91sam9261_initialize(void)
|
||||
{
|
||||
arm_pm_idle = at91sam9261_idle;
|
||||
arm_pm_restart = at91sam9_alt_restart;
|
||||
at91_extern_irq = (1 << AT91SAM9261_ID_IRQ0) | (1 << AT91SAM9261_ID_IRQ1)
|
||||
| (1 << AT91SAM9261_ID_IRQ2);
|
||||
|
|
|
@ -12,6 +12,7 @@
|
|||
|
||||
#include <linux/module.h>
|
||||
|
||||
#include <asm/proc-fns.h>
|
||||
#include <asm/irq.h>
|
||||
#include <asm/mach/arch.h>
|
||||
#include <asm/mach/map.h>
|
||||
|
@ -306,8 +307,15 @@ static void __init at91sam9263_ioremap_registers(void)
|
|||
at91sam9_ioremap_smc(1, AT91SAM9263_BASE_SMC1);
|
||||
}
|
||||
|
||||
static void at91sam9263_idle(void)
|
||||
{
|
||||
at91_sys_write(AT91_PMC_SCDR, AT91_PMC_PCK);
|
||||
cpu_do_idle();
|
||||
}
|
||||
|
||||
static void __init at91sam9263_initialize(void)
|
||||
{
|
||||
arm_pm_idle = at91sam9263_idle;
|
||||
arm_pm_restart = at91sam9_alt_restart;
|
||||
at91_extern_irq = (1 << AT91SAM9263_ID_IRQ0) | (1 << AT91SAM9263_ID_IRQ1);
|
||||
|
||||
|
|
|
@ -318,6 +318,12 @@ static struct at91_gpio_bank at91sam9g45_gpio[] __initdata = {
|
|||
}
|
||||
};
|
||||
|
||||
static void at91sam9g45_idle(void)
|
||||
{
|
||||
at91_sys_write(AT91_PMC_SCDR, AT91_PMC_PCK);
|
||||
cpu_do_idle();
|
||||
}
|
||||
|
||||
static void at91sam9g45_restart(char mode, const char *cmd)
|
||||
{
|
||||
at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_PROCRST | AT91_RSTC_PERRST);
|
||||
|
@ -342,6 +348,7 @@ static void __init at91sam9g45_ioremap_registers(void)
|
|||
|
||||
static void __init at91sam9g45_initialize(void)
|
||||
{
|
||||
arm_pm_idle = at91sam9g45_idle;
|
||||
arm_pm_restart = at91sam9g45_restart;
|
||||
at91_extern_irq = (1 << AT91SAM9G45_ID_IRQ0);
|
||||
|
||||
|
|
|
@ -11,6 +11,7 @@
|
|||
|
||||
#include <linux/module.h>
|
||||
|
||||
#include <asm/proc-fns.h>
|
||||
#include <asm/irq.h>
|
||||
#include <asm/mach/arch.h>
|
||||
#include <asm/mach/map.h>
|
||||
|
@ -290,8 +291,15 @@ static void __init at91sam9rl_ioremap_registers(void)
|
|||
at91sam9_ioremap_smc(0, AT91SAM9RL_BASE_SMC);
|
||||
}
|
||||
|
||||
static void at91sam9rl_idle(void)
|
||||
{
|
||||
at91_sys_write(AT91_PMC_SCDR, AT91_PMC_PCK);
|
||||
cpu_do_idle();
|
||||
}
|
||||
|
||||
static void __init at91sam9rl_initialize(void)
|
||||
{
|
||||
arm_pm_idle = at91sam9rl_idle;
|
||||
arm_pm_restart = at91sam9_alt_restart;
|
||||
at91_extern_irq = (1 << AT91SAM9RL_ID_IRQ0);
|
||||
|
||||
|
|
|
@ -13,6 +13,7 @@
|
|||
#include <linux/kernel.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/irq.h>
|
||||
#include <asm/proc-fns.h>
|
||||
#include <asm/mach/arch.h>
|
||||
#include <mach/at91x40.h>
|
||||
#include <mach/at91_st.h>
|
||||
|
@ -37,8 +38,19 @@ unsigned long clk_get_rate(struct clk *clk)
|
|||
return AT91X40_MASTER_CLOCK;
|
||||
}
|
||||
|
||||
static void at91x40_idle(void)
|
||||
{
|
||||
/*
|
||||
* Disable the processor clock. The processor will be automatically
|
||||
* re-enabled by an interrupt or by a reset.
|
||||
*/
|
||||
at91_sys_write(AT91_PS_CR, AT91_PS_CR_CPU);
|
||||
cpu_do_idle();
|
||||
}
|
||||
|
||||
void __init at91x40_initialize(unsigned long main_clock)
|
||||
{
|
||||
arm_pm_idle = at91x40_idle;
|
||||
at91_extern_irq = (1 << AT91X40_ID_IRQ0) | (1 << AT91X40_ID_IRQ1)
|
||||
| (1 << AT91X40_ID_IRQ2);
|
||||
}
|
||||
|
|
|
@ -1,50 +0,0 @@
|
|||
/*
|
||||
* arch/arm/mach-at91/include/mach/system.h
|
||||
*
|
||||
* Copyright (C) 2003 SAN People
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#ifndef __ASM_ARCH_SYSTEM_H
|
||||
#define __ASM_ARCH_SYSTEM_H
|
||||
|
||||
#include <mach/hardware.h>
|
||||
#include <mach/at91_st.h>
|
||||
#include <mach/at91_dbgu.h>
|
||||
#include <mach/at91_pmc.h>
|
||||
|
||||
static inline void arch_idle(void)
|
||||
{
|
||||
/*
|
||||
* Disable the processor clock. The processor will be automatically
|
||||
* re-enabled by an interrupt or by a reset.
|
||||
*/
|
||||
#ifdef AT91_PS
|
||||
at91_sys_write(AT91_PS_CR, AT91_PS_CR_CPU);
|
||||
#else
|
||||
at91_sys_write(AT91_PMC_SCDR, AT91_PMC_PCK);
|
||||
#endif
|
||||
#ifndef CONFIG_CPU_ARM920T
|
||||
/*
|
||||
* Set the processor (CP15) into 'Wait for Interrupt' mode.
|
||||
* Post-RM9200 processors need this in conjunction with the above
|
||||
* to save power when idle.
|
||||
*/
|
||||
cpu_do_idle();
|
||||
#endif
|
||||
}
|
||||
|
||||
#endif
|
|
@ -52,27 +52,8 @@
|
|||
#include <mach/csp/chipcHw_inline.h>
|
||||
#include <mach/csp/tmrHw_reg.h>
|
||||
|
||||
#define AMBA_DEVICE(name, initname, base, plat, size) \
|
||||
static struct amba_device name##_device = { \
|
||||
.dev = { \
|
||||
.coherent_dma_mask = ~0, \
|
||||
.init_name = initname, \
|
||||
.platform_data = plat \
|
||||
}, \
|
||||
.res = { \
|
||||
.start = MM_ADDR_IO_##base, \
|
||||
.end = MM_ADDR_IO_##base + (size) - 1, \
|
||||
.flags = IORESOURCE_MEM \
|
||||
}, \
|
||||
.dma_mask = ~0, \
|
||||
.irq = { \
|
||||
IRQ_##base \
|
||||
} \
|
||||
}
|
||||
|
||||
|
||||
AMBA_DEVICE(uartA, "uarta", UARTA, NULL, SZ_4K);
|
||||
AMBA_DEVICE(uartB, "uartb", UARTB, NULL, SZ_4K);
|
||||
static AMBA_APB_DEVICE(uartA, "uarta", MM_ADDR_IO_UARTA, { IRQ_UARTA }, NULL);
|
||||
static AMBA_APB_DEVICE(uartB, "uartb", MM_ADDR_IO_UARTB, { IRQ_UARTB }, NULL);
|
||||
|
||||
static struct clk pll1_clk = {
|
||||
.name = "PLL1",
|
||||
|
|
|
@ -1,28 +0,0 @@
|
|||
/*
|
||||
*
|
||||
* Copyright (C) 1999 ARM Limited
|
||||
* Copyright (C) 2000 Deep Blue Solutions Ltd
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
#ifndef __ASM_ARCH_SYSTEM_H
|
||||
#define __ASM_ARCH_SYSTEM_H
|
||||
|
||||
static inline void arch_idle(void)
|
||||
{
|
||||
cpu_do_idle();
|
||||
}
|
||||
|
||||
#endif
|
|
@ -225,3 +225,19 @@ void clps711x_restart(char mode, const char *cmd)
|
|||
{
|
||||
soft_restart(0);
|
||||
}
|
||||
|
||||
static void clps711x_idle(void)
|
||||
{
|
||||
clps_writel(1, HALT);
|
||||
__asm__ __volatile__(
|
||||
"mov r0, r0\n\
|
||||
mov r0, r0");
|
||||
}
|
||||
|
||||
static int __init clps711x_idle_init(void)
|
||||
{
|
||||
arm_pm_idle = clps711x_idle;
|
||||
return 0;
|
||||
}
|
||||
|
||||
arch_initcall(clps711x_idle_init);
|
||||
|
|
|
@ -1,35 +0,0 @@
|
|||
/*
|
||||
* arch/arm/mach-clps711x/include/mach/system.h
|
||||
*
|
||||
* Copyright (C) 2000 Deep Blue Solutions Ltd
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
#ifndef __ASM_ARCH_SYSTEM_H
|
||||
#define __ASM_ARCH_SYSTEM_H
|
||||
|
||||
#include <linux/io.h>
|
||||
#include <mach/hardware.h>
|
||||
#include <asm/hardware/clps7111.h>
|
||||
|
||||
static inline void arch_idle(void)
|
||||
{
|
||||
clps_writel(1, HALT);
|
||||
__asm__ __volatile__(
|
||||
"mov r0, r0\n\
|
||||
mov r0, r0");
|
||||
}
|
||||
|
||||
#endif
|
|
@ -1,25 +0,0 @@
|
|||
/*
|
||||
* Copyright 2000 Deep Blue Solutions Ltd
|
||||
* Copyright 2003 ARM Limited
|
||||
* Copyright 2008 Cavium Networks
|
||||
*
|
||||
* This file is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License, Version 2, as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef __MACH_SYSTEM_H
|
||||
#define __MACH_SYSTEM_H
|
||||
|
||||
#include <asm/proc-fns.h>
|
||||
|
||||
static inline void arch_idle(void)
|
||||
{
|
||||
/*
|
||||
* This should do all the clock switching
|
||||
* and wait for interrupt tricks
|
||||
*/
|
||||
cpu_do_idle();
|
||||
}
|
||||
|
||||
#endif
|
|
@ -1,21 +0,0 @@
|
|||
/*
|
||||
* DaVinci system defines
|
||||
*
|
||||
* Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com>
|
||||
*
|
||||
* 2007 (c) MontaVista Software, Inc. This file is licensed under
|
||||
* the terms of the GNU General Public License version 2. This program
|
||||
* is licensed "as is" without any warranty of any kind, whether express
|
||||
* or implied.
|
||||
*/
|
||||
#ifndef __ASM_ARCH_SYSTEM_H
|
||||
#define __ASM_ARCH_SYSTEM_H
|
||||
|
||||
#include <mach/common.h>
|
||||
|
||||
static inline void arch_idle(void)
|
||||
{
|
||||
cpu_do_idle();
|
||||
}
|
||||
|
||||
#endif /* __ASM_ARCH_SYSTEM_H */
|
|
@ -19,11 +19,14 @@
|
|||
#include <linux/err.h>
|
||||
#include <linux/platform_device.h>
|
||||
|
||||
#include <mach/hardware.h>
|
||||
#include <asm/sched_clock.h>
|
||||
#include <asm/mach/irq.h>
|
||||
#include <asm/mach/time.h>
|
||||
|
||||
#include <mach/cputype.h>
|
||||
#include <mach/hardware.h>
|
||||
#include <mach/time.h>
|
||||
|
||||
#include "clock.h"
|
||||
|
||||
static struct clock_event_device clockevent_davinci;
|
||||
|
@ -272,19 +275,9 @@ static cycle_t read_cycles(struct clocksource *cs)
|
|||
return (cycles_t)timer32_read(t);
|
||||
}
|
||||
|
||||
/*
|
||||
* Kernel assumes that sched_clock can be called early but may not have
|
||||
* things ready yet.
|
||||
*/
|
||||
static cycle_t read_dummy(struct clocksource *cs)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
static struct clocksource clocksource_davinci = {
|
||||
.rating = 300,
|
||||
.read = read_dummy,
|
||||
.read = read_cycles,
|
||||
.mask = CLOCKSOURCE_MASK(32),
|
||||
.flags = CLOCK_SOURCE_IS_CONTINUOUS,
|
||||
};
|
||||
|
@ -292,12 +285,9 @@ static struct clocksource clocksource_davinci = {
|
|||
/*
|
||||
* Overwrite weak default sched_clock with something more precise
|
||||
*/
|
||||
unsigned long long notrace sched_clock(void)
|
||||
static u32 notrace davinci_read_sched_clock(void)
|
||||
{
|
||||
const cycle_t cyc = clocksource_davinci.read(&clocksource_davinci);
|
||||
|
||||
return clocksource_cyc2ns(cyc, clocksource_davinci.mult,
|
||||
clocksource_davinci.shift);
|
||||
return timer32_read(&timers[TID_CLOCKSOURCE]);
|
||||
}
|
||||
|
||||
/*
|
||||
|
@ -397,12 +387,14 @@ static void __init davinci_timer_init(void)
|
|||
davinci_clock_tick_rate = clk_get_rate(timer_clk);
|
||||
|
||||
/* setup clocksource */
|
||||
clocksource_davinci.read = read_cycles;
|
||||
clocksource_davinci.name = id_to_name[clocksource_id];
|
||||
if (clocksource_register_hz(&clocksource_davinci,
|
||||
davinci_clock_tick_rate))
|
||||
printk(err, clocksource_davinci.name);
|
||||
|
||||
setup_sched_clock(davinci_read_sched_clock, 32,
|
||||
davinci_clock_tick_rate);
|
||||
|
||||
/* setup clockevent */
|
||||
clockevent_davinci.name = id_to_name[timers[TID_CLOCKEVENT].id];
|
||||
clockevent_davinci.mult = div_sc(davinci_clock_tick_rate, NSEC_PER_SEC,
|
||||
|
|
|
@ -1,17 +0,0 @@
|
|||
/*
|
||||
* arch/arm/mach-dove/include/mach/system.h
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without any
|
||||
* warranty of any kind, whether express or implied.
|
||||
*/
|
||||
|
||||
#ifndef __ASM_ARCH_SYSTEM_H
|
||||
#define __ASM_ARCH_SYSTEM_H
|
||||
|
||||
static inline void arch_idle(void)
|
||||
{
|
||||
cpu_do_idle();
|
||||
}
|
||||
|
||||
#endif
|
|
@ -271,8 +271,33 @@ static struct platform_device *ebsa110_devices[] = {
|
|||
&am79c961_device,
|
||||
};
|
||||
|
||||
/*
|
||||
* EBSA110 idling methodology:
|
||||
*
|
||||
* We can not execute the "wait for interrupt" instruction since that
|
||||
* will stop our MCLK signal (which provides the clock for the glue
|
||||
* logic, and therefore the timer interrupt).
|
||||
*
|
||||
* Instead, we spin, polling the IRQ_STAT register for the occurrence
|
||||
* of any interrupt with core clock down to the memory clock.
|
||||
*/
|
||||
static void ebsa110_idle(void)
|
||||
{
|
||||
const char *irq_stat = (char *)0xff000000;
|
||||
|
||||
/* disable clock switching */
|
||||
asm volatile ("mcr p15, 0, ip, c15, c2, 2" : : : "cc");
|
||||
|
||||
/* wait for an interrupt to occur */
|
||||
while (!*irq_stat);
|
||||
|
||||
/* enable clock switching */
|
||||
asm volatile ("mcr p15, 0, ip, c15, c1, 2" : : : "cc");
|
||||
}
|
||||
|
||||
static int __init ebsa110_init(void)
|
||||
{
|
||||
arm_pm_idle = ebsa110_idle;
|
||||
return platform_add_devices(ebsa110_devices, ARRAY_SIZE(ebsa110_devices));
|
||||
}
|
||||
|
||||
|
|
|
@ -1,37 +0,0 @@
|
|||
/*
|
||||
* arch/arm/mach-ebsa110/include/mach/system.h
|
||||
*
|
||||
* Copyright (C) 1996-2000 Russell King.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
#ifndef __ASM_ARCH_SYSTEM_H
|
||||
#define __ASM_ARCH_SYSTEM_H
|
||||
|
||||
/*
|
||||
* EBSA110 idling methodology:
|
||||
*
|
||||
* We can not execute the "wait for interrupt" instruction since that
|
||||
* will stop our MCLK signal (which provides the clock for the glue
|
||||
* logic, and therefore the timer interrupt).
|
||||
*
|
||||
* Instead, we spin, polling the IRQ_STAT register for the occurrence
|
||||
* of any interrupt with core clock down to the memory clock.
|
||||
*/
|
||||
static inline void arch_idle(void)
|
||||
{
|
||||
const char *irq_stat = (char *)0xff000000;
|
||||
|
||||
/* disable clock switching */
|
||||
asm volatile ("mcr p15, 0, ip, c15, c2, 2" : : : "cc");
|
||||
|
||||
/* wait for an interrupt to occur */
|
||||
while (!*irq_stat);
|
||||
|
||||
/* enable clock switching */
|
||||
asm volatile ("mcr p15, 0, ip, c15, c1, 2" : : : "cc");
|
||||
}
|
||||
|
||||
#endif
|
|
@ -279,48 +279,14 @@ static struct amba_pl010_data ep93xx_uart_data = {
|
|||
.set_mctrl = ep93xx_uart_set_mctrl,
|
||||
};
|
||||
|
||||
static struct amba_device uart1_device = {
|
||||
.dev = {
|
||||
.init_name = "apb:uart1",
|
||||
.platform_data = &ep93xx_uart_data,
|
||||
},
|
||||
.res = {
|
||||
.start = EP93XX_UART1_PHYS_BASE,
|
||||
.end = EP93XX_UART1_PHYS_BASE + 0x0fff,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
.irq = { IRQ_EP93XX_UART1, NO_IRQ },
|
||||
.periphid = 0x00041010,
|
||||
};
|
||||
static AMBA_APB_DEVICE(uart1, "apb:uart1", 0x00041010, EP93XX_UART1_PHYS_BASE,
|
||||
{ IRQ_EP93XX_UART1 }, &ep93xx_uart_data);
|
||||
|
||||
static struct amba_device uart2_device = {
|
||||
.dev = {
|
||||
.init_name = "apb:uart2",
|
||||
.platform_data = &ep93xx_uart_data,
|
||||
},
|
||||
.res = {
|
||||
.start = EP93XX_UART2_PHYS_BASE,
|
||||
.end = EP93XX_UART2_PHYS_BASE + 0x0fff,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
.irq = { IRQ_EP93XX_UART2, NO_IRQ },
|
||||
.periphid = 0x00041010,
|
||||
};
|
||||
|
||||
static struct amba_device uart3_device = {
|
||||
.dev = {
|
||||
.init_name = "apb:uart3",
|
||||
.platform_data = &ep93xx_uart_data,
|
||||
},
|
||||
.res = {
|
||||
.start = EP93XX_UART3_PHYS_BASE,
|
||||
.end = EP93XX_UART3_PHYS_BASE + 0x0fff,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
.irq = { IRQ_EP93XX_UART3, NO_IRQ },
|
||||
.periphid = 0x00041010,
|
||||
};
|
||||
static AMBA_APB_DEVICE(uart2, "apb:uart2", 0x00041010, EP93XX_UART2_PHYS_BASE,
|
||||
{ IRQ_EP93XX_UART2 }, &ep93xx_uart_data);
|
||||
|
||||
static AMBA_APB_DEVICE(uart3, "apb:uart3", 0x00041010, EP93XX_UART3_PHYS_BASE,
|
||||
{ IRQ_EP93XX_UART3 }, &ep93xx_uart_data);
|
||||
|
||||
static struct resource ep93xx_rtc_resource[] = {
|
||||
{
|
||||
|
|
|
@ -1,7 +0,0 @@
|
|||
/*
|
||||
* arch/arm/mach-ep93xx/include/mach/system.h
|
||||
*/
|
||||
static inline void arch_idle(void)
|
||||
{
|
||||
cpu_do_idle();
|
||||
}
|
|
@ -201,14 +201,6 @@ static struct map_desc exynos4_iodesc1[] __initdata = {
|
|||
},
|
||||
};
|
||||
|
||||
static void exynos_idle(void)
|
||||
{
|
||||
if (!need_resched())
|
||||
cpu_do_idle();
|
||||
|
||||
local_irq_enable();
|
||||
}
|
||||
|
||||
void exynos4_restart(char mode, const char *cmd)
|
||||
{
|
||||
__raw_writel(0x1, S5P_SWRESET);
|
||||
|
@ -467,10 +459,6 @@ early_initcall(exynos4_l2x0_cache_init);
|
|||
int __init exynos_init(void)
|
||||
{
|
||||
printk(KERN_INFO "EXYNOS: Initializing architecture\n");
|
||||
|
||||
/* set idle function */
|
||||
pm_idle = exynos_idle;
|
||||
|
||||
return device_register(&exynos4_dev);
|
||||
}
|
||||
|
||||
|
|
|
@ -74,21 +74,8 @@ struct dma_pl330_platdata exynos4_pdma0_pdata = {
|
|||
.peri_id = pdma0_peri,
|
||||
};
|
||||
|
||||
struct amba_device exynos4_device_pdma0 = {
|
||||
.dev = {
|
||||
.init_name = "dma-pl330.0",
|
||||
.dma_mask = &dma_dmamask,
|
||||
.coherent_dma_mask = DMA_BIT_MASK(32),
|
||||
.platform_data = &exynos4_pdma0_pdata,
|
||||
},
|
||||
.res = {
|
||||
.start = EXYNOS4_PA_PDMA0,
|
||||
.end = EXYNOS4_PA_PDMA0 + SZ_4K,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
.irq = {IRQ_PDMA0, NO_IRQ},
|
||||
.periphid = 0x00041330,
|
||||
};
|
||||
AMBA_AHB_DEVICE(exynos4_pdma0, "dma-pl330.0", 0x00041330, EXYNOS4_PA_PDMA0,
|
||||
{IRQ_PDMA0}, &exynos4_pdma0_pdata);
|
||||
|
||||
u8 pdma1_peri[] = {
|
||||
DMACH_PCM0_RX,
|
||||
|
@ -123,21 +110,8 @@ struct dma_pl330_platdata exynos4_pdma1_pdata = {
|
|||
.peri_id = pdma1_peri,
|
||||
};
|
||||
|
||||
struct amba_device exynos4_device_pdma1 = {
|
||||
.dev = {
|
||||
.init_name = "dma-pl330.1",
|
||||
.dma_mask = &dma_dmamask,
|
||||
.coherent_dma_mask = DMA_BIT_MASK(32),
|
||||
.platform_data = &exynos4_pdma1_pdata,
|
||||
},
|
||||
.res = {
|
||||
.start = EXYNOS4_PA_PDMA1,
|
||||
.end = EXYNOS4_PA_PDMA1 + SZ_4K,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
.irq = {IRQ_PDMA1, NO_IRQ},
|
||||
.periphid = 0x00041330,
|
||||
};
|
||||
AMBA_AHB_DEVICE(exynos4_pdma1, "dma-pl330.1", 0x00041330, EXYNOS4_PA_PDMA1,
|
||||
{IRQ_PDMA1}, &exynos4_pdma1_pdata);
|
||||
|
||||
static int __init exynos4_dma_init(void)
|
||||
{
|
||||
|
@ -146,11 +120,11 @@ static int __init exynos4_dma_init(void)
|
|||
|
||||
dma_cap_set(DMA_SLAVE, exynos4_pdma0_pdata.cap_mask);
|
||||
dma_cap_set(DMA_CYCLIC, exynos4_pdma0_pdata.cap_mask);
|
||||
amba_device_register(&exynos4_device_pdma0, &iomem_resource);
|
||||
amba_device_register(&exynos4_pdma0_device, &iomem_resource);
|
||||
|
||||
dma_cap_set(DMA_SLAVE, exynos4_pdma1_pdata.cap_mask);
|
||||
dma_cap_set(DMA_CYCLIC, exynos4_pdma1_pdata.cap_mask);
|
||||
amba_device_register(&exynos4_device_pdma1, &iomem_resource);
|
||||
amba_device_register(&exynos4_pdma1_device, &iomem_resource);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
|
@ -1,20 +0,0 @@
|
|||
/* linux/arch/arm/mach-exynos4/include/mach/system.h
|
||||
*
|
||||
* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com
|
||||
*
|
||||
* EXYNOS4 - system support header
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef __ASM_ARCH_SYSTEM_H
|
||||
#define __ASM_ARCH_SYSTEM_H __FILE__
|
||||
|
||||
static void arch_idle(void)
|
||||
{
|
||||
/* nothing here yet */
|
||||
}
|
||||
#endif /* __ASM_ARCH_SYSTEM_H */
|
|
@ -1,13 +0,0 @@
|
|||
/*
|
||||
* arch/arm/mach-footbridge/include/mach/system.h
|
||||
*
|
||||
* Copyright (C) 1996-1999 Russell King.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
static inline void arch_idle(void)
|
||||
{
|
||||
cpu_do_idle();
|
||||
}
|
|
@ -4,7 +4,7 @@
|
|||
|
||||
# Object file lists.
|
||||
|
||||
obj-y := irq.o mm.o time.o devices.o gpio.o
|
||||
obj-y := irq.o mm.o time.o devices.o gpio.o idle.o
|
||||
|
||||
# Board-specific support
|
||||
obj-$(CONFIG_MACH_NAS4220B) += board-nas4220b.o
|
||||
|
|
29
arch/arm/mach-gemini/idle.c
Normal file
29
arch/arm/mach-gemini/idle.c
Normal file
|
@ -0,0 +1,29 @@
|
|||
/*
|
||||
* arch/arm/mach-gemini/idle.c
|
||||
*/
|
||||
|
||||
#include <linux/init.h>
|
||||
#include <asm/system.h>
|
||||
#include <asm/proc-fns.h>
|
||||
|
||||
static void gemini_idle(void)
|
||||
{
|
||||
/*
|
||||
* Because of broken hardware we have to enable interrupts or the CPU
|
||||
* will never wakeup... Acctualy it is not very good to enable
|
||||
* interrupts first since scheduler can miss a tick, but there is
|
||||
* no other way around this. Platforms that needs it for power saving
|
||||
* should call enable_hlt() in init code, since by default it is
|
||||
* disabled.
|
||||
*/
|
||||
local_irq_enable();
|
||||
cpu_do_idle();
|
||||
}
|
||||
|
||||
static int __init gemini_idle_init(void)
|
||||
{
|
||||
arm_pm_idle = gemini_idle;
|
||||
return 0;
|
||||
}
|
||||
|
||||
arch_initcall(gemini_idle_init);
|
|
@ -14,20 +14,6 @@
|
|||
#include <mach/hardware.h>
|
||||
#include <mach/global_reg.h>
|
||||
|
||||
static inline void arch_idle(void)
|
||||
{
|
||||
/*
|
||||
* Because of broken hardware we have to enable interrupts or the CPU
|
||||
* will never wakeup... Acctualy it is not very good to enable
|
||||
* interrupts here since scheduler can miss a tick, but there is
|
||||
* no other way around this. Platforms that needs it for power saving
|
||||
* should call enable_hlt() in init code, since by default it is
|
||||
* disabled.
|
||||
*/
|
||||
local_irq_enable();
|
||||
cpu_do_idle();
|
||||
}
|
||||
|
||||
static inline void arch_reset(char mode, const char *cmd)
|
||||
{
|
||||
__raw_writel(RESET_GLOBAL | RESET_CPU1,
|
||||
|
|
|
@ -73,8 +73,8 @@ void __init gemini_init_irq(void)
|
|||
unsigned int i, mode = 0, level = 0;
|
||||
|
||||
/*
|
||||
* Disable arch_idle() by default since it is buggy
|
||||
* For more info see arch/arm/mach-gemini/include/mach/system.h
|
||||
* Disable the idle handler by default since it is buggy
|
||||
* For more info see arch/arm/mach-gemini/idle.c
|
||||
*/
|
||||
disable_hlt();
|
||||
|
||||
|
|
|
@ -247,3 +247,21 @@ void h720x_restart(char mode, const char *cmd)
|
|||
{
|
||||
CPU_REG (PMU_BASE, PMU_STAT) |= PMU_WARMRESET;
|
||||
}
|
||||
|
||||
static void h720x__idle(void)
|
||||
{
|
||||
CPU_REG (PMU_BASE, PMU_MODE) = PMU_MODE_IDLE;
|
||||
nop();
|
||||
nop();
|
||||
CPU_REG (PMU_BASE, PMU_MODE) = PMU_MODE_RUN;
|
||||
nop();
|
||||
nop();
|
||||
}
|
||||
|
||||
static int __init h720x_idle_init(void)
|
||||
{
|
||||
arm_pm_idle = h720x__idle;
|
||||
return 0;
|
||||
}
|
||||
|
||||
arch_initcall(h720x_idle_init);
|
||||
|
|
|
@ -1,27 +0,0 @@
|
|||
/*
|
||||
* arch/arm/mach-h720x/include/mach/system.h
|
||||
*
|
||||
* Copyright (C) 2001-2002 Jungjun Kim, Hynix Semiconductor Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
* arch/arm/mach-h720x/include/mach/system.h
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __ASM_ARCH_SYSTEM_H
|
||||
#define __ASM_ARCH_SYSTEM_H
|
||||
#include <mach/hardware.h>
|
||||
|
||||
static void arch_idle(void)
|
||||
{
|
||||
CPU_REG (PMU_BASE, PMU_MODE) = PMU_MODE_IDLE;
|
||||
nop();
|
||||
nop();
|
||||
CPU_REG (PMU_BASE, PMU_MODE) = PMU_MODE_RUN;
|
||||
nop();
|
||||
nop();
|
||||
}
|
||||
|
||||
#endif
|
|
@ -33,7 +33,6 @@
|
|||
#include <asm/mach/arch.h>
|
||||
#include <asm/mach/map.h>
|
||||
#include <asm/mach/time.h>
|
||||
#include <mach/irqs.h>
|
||||
|
||||
#include "core.h"
|
||||
#include "sysregs.h"
|
||||
|
|
|
@ -1,6 +0,0 @@
|
|||
#ifndef __MACH_IRQS_H
|
||||
#define __MACH_IRQS_H
|
||||
|
||||
#define NR_IRQS 192
|
||||
|
||||
#endif
|
|
@ -1,24 +0,0 @@
|
|||
/*
|
||||
* Copyright 2010-2011 Calxeda, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
#ifndef __MACH_SYSTEM_H
|
||||
#define __MACH_SYSTEM_H
|
||||
|
||||
static inline void arch_idle(void)
|
||||
{
|
||||
cpu_do_idle();
|
||||
}
|
||||
|
||||
#endif
|
|
@ -34,31 +34,29 @@ static void imx3_idle(void)
|
|||
{
|
||||
unsigned long reg = 0;
|
||||
|
||||
if (!need_resched())
|
||||
__asm__ __volatile__(
|
||||
/* disable I and D cache */
|
||||
"mrc p15, 0, %0, c1, c0, 0\n"
|
||||
"bic %0, %0, #0x00001000\n"
|
||||
"bic %0, %0, #0x00000004\n"
|
||||
"mcr p15, 0, %0, c1, c0, 0\n"
|
||||
/* invalidate I cache */
|
||||
"mov %0, #0\n"
|
||||
"mcr p15, 0, %0, c7, c5, 0\n"
|
||||
/* clear and invalidate D cache */
|
||||
"mov %0, #0\n"
|
||||
"mcr p15, 0, %0, c7, c14, 0\n"
|
||||
/* WFI */
|
||||
"mov %0, #0\n"
|
||||
"mcr p15, 0, %0, c7, c0, 4\n"
|
||||
"nop\n" "nop\n" "nop\n" "nop\n"
|
||||
"nop\n" "nop\n" "nop\n"
|
||||
/* enable I and D cache */
|
||||
"mrc p15, 0, %0, c1, c0, 0\n"
|
||||
"orr %0, %0, #0x00001000\n"
|
||||
"orr %0, %0, #0x00000004\n"
|
||||
"mcr p15, 0, %0, c1, c0, 0\n"
|
||||
: "=r" (reg));
|
||||
local_irq_enable();
|
||||
__asm__ __volatile__(
|
||||
/* disable I and D cache */
|
||||
"mrc p15, 0, %0, c1, c0, 0\n"
|
||||
"bic %0, %0, #0x00001000\n"
|
||||
"bic %0, %0, #0x00000004\n"
|
||||
"mcr p15, 0, %0, c1, c0, 0\n"
|
||||
/* invalidate I cache */
|
||||
"mov %0, #0\n"
|
||||
"mcr p15, 0, %0, c7, c5, 0\n"
|
||||
/* clear and invalidate D cache */
|
||||
"mov %0, #0\n"
|
||||
"mcr p15, 0, %0, c7, c14, 0\n"
|
||||
/* WFI */
|
||||
"mov %0, #0\n"
|
||||
"mcr p15, 0, %0, c7, c0, 4\n"
|
||||
"nop\n" "nop\n" "nop\n" "nop\n"
|
||||
"nop\n" "nop\n" "nop\n"
|
||||
/* enable I and D cache */
|
||||
"mrc p15, 0, %0, c1, c0, 0\n"
|
||||
"orr %0, %0, #0x00001000\n"
|
||||
"orr %0, %0, #0x00000004\n"
|
||||
"mcr p15, 0, %0, c1, c0, 0\n"
|
||||
: "=r" (reg));
|
||||
}
|
||||
|
||||
static void __iomem *imx3_ioremap(unsigned long phys_addr, size_t size,
|
||||
|
@ -134,8 +132,8 @@ void __init imx31_init_early(void)
|
|||
{
|
||||
mxc_set_cpu_type(MXC_CPU_MX31);
|
||||
mxc_arch_reset_init(MX31_IO_ADDRESS(MX31_WDOG_BASE_ADDR));
|
||||
pm_idle = imx3_idle;
|
||||
imx_ioremap = imx3_ioremap;
|
||||
arm_pm_idle = imx3_idle;
|
||||
}
|
||||
|
||||
void __init mx31_init_irq(void)
|
||||
|
@ -197,7 +195,7 @@ void __init imx35_init_early(void)
|
|||
mxc_set_cpu_type(MXC_CPU_MX35);
|
||||
mxc_iomux_v3_init(MX35_IO_ADDRESS(MX35_IOMUXC_BASE_ADDR));
|
||||
mxc_arch_reset_init(MX35_IO_ADDRESS(MX35_WDOG_BASE_ADDR));
|
||||
pm_idle = imx3_idle;
|
||||
arm_pm_idle = imx3_idle;
|
||||
imx_ioremap = imx3_ioremap;
|
||||
}
|
||||
|
||||
|
|
|
@ -10,7 +10,6 @@
|
|||
#include <linux/kernel.h>
|
||||
#include <linux/suspend.h>
|
||||
#include <linux/io.h>
|
||||
#include <mach/system.h>
|
||||
#include <mach/hardware.h>
|
||||
|
||||
static int mx27_suspend_enter(suspend_state_t state)
|
||||
|
@ -23,7 +22,7 @@ static int mx27_suspend_enter(suspend_state_t state)
|
|||
cscr &= 0xFFFFFFFC;
|
||||
__raw_writel(cscr, MX27_IO_ADDRESS(MX27_CCM_BASE_ADDR));
|
||||
/* Executes WFI */
|
||||
arch_idle();
|
||||
cpu_do_idle();
|
||||
break;
|
||||
|
||||
default:
|
||||
|
|
|
@ -5,7 +5,6 @@ menu "Integrator Options"
|
|||
config ARCH_INTEGRATOR_AP
|
||||
bool "Support Integrator/AP and Integrator/PP2 platforms"
|
||||
select CLKSRC_MMIO
|
||||
select HAVE_SCHED_CLOCK
|
||||
select MIGHT_HAVE_PCI
|
||||
select SERIAL_AMBA_PL010
|
||||
select SERIAL_AMBA_PL010_CONSOLE
|
||||
|
|
|
@ -36,67 +36,23 @@
|
|||
|
||||
static struct amba_pl010_data integrator_uart_data;
|
||||
|
||||
static struct amba_device rtc_device = {
|
||||
.dev = {
|
||||
.init_name = "mb:15",
|
||||
},
|
||||
.res = {
|
||||
.start = INTEGRATOR_RTC_BASE,
|
||||
.end = INTEGRATOR_RTC_BASE + SZ_4K - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
.irq = { IRQ_RTCINT, NO_IRQ },
|
||||
};
|
||||
#define INTEGRATOR_RTC_IRQ { IRQ_RTCINT }
|
||||
#define INTEGRATOR_UART0_IRQ { IRQ_UARTINT0 }
|
||||
#define INTEGRATOR_UART1_IRQ { IRQ_UARTINT1 }
|
||||
#define KMI0_IRQ { IRQ_KMIINT0 }
|
||||
#define KMI1_IRQ { IRQ_KMIINT1 }
|
||||
|
||||
static struct amba_device uart0_device = {
|
||||
.dev = {
|
||||
.init_name = "mb:16",
|
||||
.platform_data = &integrator_uart_data,
|
||||
},
|
||||
.res = {
|
||||
.start = INTEGRATOR_UART0_BASE,
|
||||
.end = INTEGRATOR_UART0_BASE + SZ_4K - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
.irq = { IRQ_UARTINT0, NO_IRQ },
|
||||
};
|
||||
static AMBA_APB_DEVICE(rtc, "mb:15", 0,
|
||||
INTEGRATOR_RTC_BASE, INTEGRATOR_RTC_IRQ, NULL);
|
||||
|
||||
static struct amba_device uart1_device = {
|
||||
.dev = {
|
||||
.init_name = "mb:17",
|
||||
.platform_data = &integrator_uart_data,
|
||||
},
|
||||
.res = {
|
||||
.start = INTEGRATOR_UART1_BASE,
|
||||
.end = INTEGRATOR_UART1_BASE + SZ_4K - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
.irq = { IRQ_UARTINT1, NO_IRQ },
|
||||
};
|
||||
static AMBA_APB_DEVICE(uart0, "mb:16", 0,
|
||||
INTEGRATOR_UART0_BASE, INTEGRATOR_UART0_IRQ, &integrator_uart_data);
|
||||
|
||||
static struct amba_device kmi0_device = {
|
||||
.dev = {
|
||||
.init_name = "mb:18",
|
||||
},
|
||||
.res = {
|
||||
.start = KMI0_BASE,
|
||||
.end = KMI0_BASE + SZ_4K - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
.irq = { IRQ_KMIINT0, NO_IRQ },
|
||||
};
|
||||
static AMBA_APB_DEVICE(uart1, "mb:17", 0,
|
||||
INTEGRATOR_UART1_BASE, INTEGRATOR_UART1_IRQ, &integrator_uart_data);
|
||||
|
||||
static struct amba_device kmi1_device = {
|
||||
.dev = {
|
||||
.init_name = "mb:19",
|
||||
},
|
||||
.res = {
|
||||
.start = KMI1_BASE,
|
||||
.end = KMI1_BASE + SZ_4K - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
.irq = { IRQ_KMIINT1, NO_IRQ },
|
||||
};
|
||||
static AMBA_APB_DEVICE(kmi0, "mb:18", 0, KMI0_BASE, KMI0_IRQ, NULL);
|
||||
static AMBA_APB_DEVICE(kmi1, "mb:19", 0, KMI1_BASE, KMI1_IRQ, NULL);
|
||||
|
||||
static struct amba_device *amba_devs[] __initdata = {
|
||||
&rtc_device,
|
||||
|
|
|
@ -401,24 +401,21 @@ static int impd1_probe(struct lm_device *dev)
|
|||
|
||||
pc_base = dev->resource.start + idev->offset;
|
||||
|
||||
d = kzalloc(sizeof(struct amba_device), GFP_KERNEL);
|
||||
d = amba_device_alloc(NULL, pc_base, SZ_4K);
|
||||
if (!d)
|
||||
continue;
|
||||
|
||||
dev_set_name(&d->dev, "lm%x:%5.5lx", dev->id, idev->offset >> 12);
|
||||
d->dev.parent = &dev->dev;
|
||||
d->res.start = dev->resource.start + idev->offset;
|
||||
d->res.end = d->res.start + SZ_4K - 1;
|
||||
d->res.flags = IORESOURCE_MEM;
|
||||
d->irq[0] = dev->irq;
|
||||
d->irq[1] = dev->irq;
|
||||
d->periphid = idev->id;
|
||||
d->dev.platform_data = idev->platform_data;
|
||||
|
||||
ret = amba_device_register(d, &dev->resource);
|
||||
ret = amba_device_add(d, &dev->resource);
|
||||
if (ret) {
|
||||
dev_err(&d->dev, "unable to register device: %d\n", ret);
|
||||
kfree(d);
|
||||
amba_device_put(d);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
@ -1,33 +0,0 @@
|
|||
/*
|
||||
* arch/arm/mach-integrator/include/mach/system.h
|
||||
*
|
||||
* Copyright (C) 1999 ARM Limited
|
||||
* Copyright (C) 2000 Deep Blue Solutions Ltd
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
#ifndef __ASM_ARCH_SYSTEM_H
|
||||
#define __ASM_ARCH_SYSTEM_H
|
||||
|
||||
static inline void arch_idle(void)
|
||||
{
|
||||
/*
|
||||
* This should do all the clock switching
|
||||
* and wait for interrupt tricks
|
||||
*/
|
||||
cpu_do_idle();
|
||||
}
|
||||
|
||||
#endif
|
|
@ -347,32 +347,14 @@ static struct mmci_platform_data mmc_data = {
|
|||
.gpio_cd = -1,
|
||||
};
|
||||
|
||||
static struct amba_device mmc_device = {
|
||||
.dev = {
|
||||
.init_name = "mb:1c",
|
||||
.platform_data = &mmc_data,
|
||||
},
|
||||
.res = {
|
||||
.start = INTEGRATOR_CP_MMC_BASE,
|
||||
.end = INTEGRATOR_CP_MMC_BASE + SZ_4K - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
.irq = { IRQ_CP_MMCIINT0, IRQ_CP_MMCIINT1 },
|
||||
.periphid = 0,
|
||||
};
|
||||
#define INTEGRATOR_CP_MMC_IRQS { IRQ_CP_MMCIINT0, IRQ_CP_MMCIINT1 }
|
||||
#define INTEGRATOR_CP_AACI_IRQS { IRQ_CP_AACIINT }
|
||||
|
||||
static struct amba_device aaci_device = {
|
||||
.dev = {
|
||||
.init_name = "mb:1d",
|
||||
},
|
||||
.res = {
|
||||
.start = INTEGRATOR_CP_AACI_BASE,
|
||||
.end = INTEGRATOR_CP_AACI_BASE + SZ_4K - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
.irq = { IRQ_CP_AACIINT, NO_IRQ },
|
||||
.periphid = 0,
|
||||
};
|
||||
static AMBA_APB_DEVICE(mmc, "mb:1c", 0, INTEGRATOR_CP_MMC_BASE,
|
||||
INTEGRATOR_CP_MMC_IRQS, &mmc_data);
|
||||
|
||||
static AMBA_APB_DEVICE(aaci, "mb:1d", 0, INTEGRATOR_CP_AACI_BASE,
|
||||
INTEGRATOR_CP_AACI_IRQS, NULL);
|
||||
|
||||
|
||||
/*
|
||||
|
@ -425,21 +407,8 @@ static struct clcd_board clcd_data = {
|
|||
.remove = versatile_clcd_remove_dma,
|
||||
};
|
||||
|
||||
static struct amba_device clcd_device = {
|
||||
.dev = {
|
||||
.init_name = "mb:c0",
|
||||
.coherent_dma_mask = ~0,
|
||||
.platform_data = &clcd_data,
|
||||
},
|
||||
.res = {
|
||||
.start = INTCP_PA_CLCD_BASE,
|
||||
.end = INTCP_PA_CLCD_BASE + SZ_4K - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
.dma_mask = ~0,
|
||||
.irq = { IRQ_CP_CLCDCINT, NO_IRQ },
|
||||
.periphid = 0,
|
||||
};
|
||||
static AMBA_AHB_DEVICE(clcd, "mb:c0", 0, INTCP_PA_CLCD_BASE,
|
||||
{ IRQ_CP_CLCDCINT }, &clcd_data);
|
||||
|
||||
static struct amba_device *amba_devs[] __initdata = {
|
||||
&mmc_device,
|
||||
|
|
|
@ -1,13 +0,0 @@
|
|||
/*
|
||||
* arch/arm/mach-iop13xx/include/mach/system.h
|
||||
*
|
||||
* Copyright (C) 2004 Intel Corp.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
static inline void arch_idle(void)
|
||||
{
|
||||
cpu_do_idle();
|
||||
}
|
|
@ -1,13 +0,0 @@
|
|||
/*
|
||||
* arch/arm/mach-iop32x/include/mach/system.h
|
||||
*
|
||||
* Copyright (C) 2001 MontaVista Software, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
static inline void arch_idle(void)
|
||||
{
|
||||
cpu_do_idle();
|
||||
}
|
|
@ -1,13 +0,0 @@
|
|||
/*
|
||||
* arch/arm/mach-iop33x/include/mach/system.h
|
||||
*
|
||||
* Copyright (C) 2001 MontaVista Software, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
static inline void arch_idle(void)
|
||||
{
|
||||
cpu_do_idle();
|
||||
}
|
|
@ -1,14 +0,0 @@
|
|||
/*
|
||||
* arch/arm/mach-ixp2000/include/mach/system.h
|
||||
*
|
||||
* Copyright (C) 2002 Intel Corp.
|
||||
* Copyricht (C) 2003-2005 MontaVista Software, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
static inline void arch_idle(void)
|
||||
{
|
||||
cpu_do_idle();
|
||||
}
|
|
@ -441,6 +441,9 @@ static struct platform_device *ixp23xx_devices[] __initdata = {
|
|||
|
||||
void __init ixp23xx_sys_init(void)
|
||||
{
|
||||
/* by default, the idle code is disabled */
|
||||
disable_hlt();
|
||||
|
||||
*IXP23XX_EXP_UNIT_FUSE |= 0xf;
|
||||
platform_add_devices(ixp23xx_devices, ARRAY_SIZE(ixp23xx_devices));
|
||||
}
|
||||
|
|
|
@ -1,16 +0,0 @@
|
|||
/*
|
||||
* arch/arm/mach-ixp23xx/include/mach/system.h
|
||||
*
|
||||
* Copyright (C) 2003 Intel Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
static inline void arch_idle(void)
|
||||
{
|
||||
#if 0
|
||||
if (!hlt_counter)
|
||||
cpu_do_idle();
|
||||
#endif
|
||||
}
|
|
@ -236,6 +236,12 @@ void __init ixp4xx_init_irq(void)
|
|||
{
|
||||
int i = 0;
|
||||
|
||||
/*
|
||||
* ixp4xx does not implement the XScale PWRMODE register
|
||||
* so it must not call cpu_do_idle().
|
||||
*/
|
||||
disable_hlt();
|
||||
|
||||
/* Route all sources to IRQ instead of FIQ */
|
||||
*IXP4XX_ICLR = 0x0;
|
||||
|
||||
|
|
|
@ -1,19 +0,0 @@
|
|||
/*
|
||||
* arch/arm/mach-ixp4xx/include/mach/system.h
|
||||
*
|
||||
* Copyright (C) 2002 Intel Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
*/
|
||||
static inline void arch_idle(void)
|
||||
{
|
||||
/* ixp4xx does not implement the XScale PWRMODE register,
|
||||
* so it must not call cpu_do_idle() here.
|
||||
*/
|
||||
#if 0
|
||||
cpu_do_idle();
|
||||
#endif
|
||||
}
|
|
@ -1,17 +0,0 @@
|
|||
/*
|
||||
* arch/arm/mach-kirkwood/include/mach/system.h
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without any
|
||||
* warranty of any kind, whether express or implied.
|
||||
*/
|
||||
|
||||
#ifndef __ASM_ARCH_SYSTEM_H
|
||||
#define __ASM_ARCH_SYSTEM_H
|
||||
|
||||
static inline void arch_idle(void)
|
||||
{
|
||||
cpu_do_idle();
|
||||
}
|
||||
|
||||
#endif
|
|
@ -1,27 +0,0 @@
|
|||
/*
|
||||
* arch/arm/mach-s3c2410/include/mach/system.h
|
||||
*
|
||||
* Copyright (C) 2006 Simtec Electronics
|
||||
* Ben Dooks <ben@simtec.co.uk>
|
||||
*
|
||||
* KS8695 - System function defines and includes
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef __ASM_ARCH_SYSTEM_H
|
||||
#define __ASM_ARCH_SYSTEM_H
|
||||
|
||||
static void arch_idle(void)
|
||||
{
|
||||
/*
|
||||
* This should do all the clock switching
|
||||
* and wait for interrupt tricks,
|
||||
*/
|
||||
cpu_do_idle();
|
||||
|
||||
}
|
||||
|
||||
#endif
|
|
@ -1,27 +0,0 @@
|
|||
/*
|
||||
* arch/arm/mach-lpc32xx/include/mach/system.h
|
||||
*
|
||||
* Author: Kevin Wells <kevin.wells@nxp.com>
|
||||
*
|
||||
* Copyright (C) 2010 NXP Semiconductors
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef __ASM_ARCH_SYSTEM_H
|
||||
#define __ASM_ARCH_SYSTEM_H
|
||||
|
||||
static void arch_idle(void)
|
||||
{
|
||||
cpu_do_idle();
|
||||
}
|
||||
|
||||
#endif
|
|
@ -149,20 +149,8 @@ static struct clcd_board lpc32xx_clcd_data = {
|
|||
.remove = lpc32xx_clcd_remove,
|
||||
};
|
||||
|
||||
static struct amba_device lpc32xx_clcd_device = {
|
||||
.dev = {
|
||||
.coherent_dma_mask = ~0,
|
||||
.init_name = "dev:clcd",
|
||||
.platform_data = &lpc32xx_clcd_data,
|
||||
},
|
||||
.res = {
|
||||
.start = LPC32XX_LCD_BASE,
|
||||
.end = (LPC32XX_LCD_BASE + SZ_4K - 1),
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
.dma_mask = ~0,
|
||||
.irq = {IRQ_LPC32XX_LCD, NO_IRQ},
|
||||
};
|
||||
static AMBA_AHB_DEVICE(lpc32xx_clcd, "dev:clcd", 0,
|
||||
LPC32XX_LCD_BASE, { IRQ_LPC32XX_LCD }, &lpc32xx_clcd_data);
|
||||
|
||||
/*
|
||||
* AMBA SSP (SPI)
|
||||
|
@ -191,20 +179,8 @@ static struct pl022_ssp_controller lpc32xx_ssp0_data = {
|
|||
.enable_dma = 0,
|
||||
};
|
||||
|
||||
static struct amba_device lpc32xx_ssp0_device = {
|
||||
.dev = {
|
||||
.coherent_dma_mask = ~0,
|
||||
.init_name = "dev:ssp0",
|
||||
.platform_data = &lpc32xx_ssp0_data,
|
||||
},
|
||||
.res = {
|
||||
.start = LPC32XX_SSP0_BASE,
|
||||
.end = (LPC32XX_SSP0_BASE + SZ_4K - 1),
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
.dma_mask = ~0,
|
||||
.irq = {IRQ_LPC32XX_SSP0, NO_IRQ},
|
||||
};
|
||||
static AMBA_APB_DEVICE(lpc32xx_ssp0, "dev:ssp0", 0,
|
||||
LPC32XX_SSP0_BASE, { IRQ_LPC32XX_SSP0 }, &lpc32xx_ssp0_data);
|
||||
|
||||
/* AT25 driver registration */
|
||||
static int __init phy3250_spi_board_register(void)
|
||||
|
|
|
@ -24,6 +24,7 @@
|
|||
#include <mach/addr-map.h>
|
||||
#include <mach/mfp-pxa168.h>
|
||||
#include <mach/pxa168.h>
|
||||
#include <mach/irqs.h>
|
||||
#include <video/pxa168fb.h>
|
||||
#include <linux/input.h>
|
||||
#include <plat/pxa27x_keypad.h>
|
||||
|
@ -240,7 +241,7 @@ static void __init common_init(void)
|
|||
|
||||
MACHINE_START(ASPENITE, "PXA168-based Aspenite Development Platform")
|
||||
.map_io = mmp_map_io,
|
||||
.nr_irqs = IRQ_BOARD_START,
|
||||
.nr_irqs = MMP_NR_IRQS,
|
||||
.init_irq = pxa168_init_irq,
|
||||
.timer = &pxa168_timer,
|
||||
.init_machine = common_init,
|
||||
|
@ -249,7 +250,7 @@ MACHINE_END
|
|||
|
||||
MACHINE_START(ZYLONITE2, "PXA168-based Zylonite2 Development Platform")
|
||||
.map_io = mmp_map_io,
|
||||
.nr_irqs = IRQ_BOARD_START,
|
||||
.nr_irqs = MMP_NR_IRQS,
|
||||
.init_irq = pxa168_init_irq,
|
||||
.timer = &pxa168_timer,
|
||||
.init_machine = common_init,
|
||||
|
|
|
@ -43,6 +43,7 @@ static void __init avengers_lite_init(void)
|
|||
|
||||
MACHINE_START(AVENGERS_LITE, "PXA168 Avengers lite Development Platform")
|
||||
.map_io = mmp_map_io,
|
||||
.nr_irqs = MMP_NR_IRQS,
|
||||
.init_irq = pxa168_init_irq,
|
||||
.timer = &pxa168_timer,
|
||||
.init_machine = avengers_lite_init,
|
||||
|
|
|
@ -28,7 +28,7 @@
|
|||
|
||||
#include "common.h"
|
||||
|
||||
#define BROWNSTONE_NR_IRQS (IRQ_BOARD_START + 40)
|
||||
#define BROWNSTONE_NR_IRQS (MMP_NR_IRQS + 40)
|
||||
|
||||
#define GPIO_5V_ENABLE (89)
|
||||
|
||||
|
@ -158,7 +158,7 @@ static struct platform_device brownstone_v_5vp_device = {
|
|||
};
|
||||
|
||||
static struct max8925_platform_data brownstone_max8925_info = {
|
||||
.irq_base = IRQ_BOARD_START,
|
||||
.irq_base = MMP_NR_IRQS,
|
||||
};
|
||||
|
||||
static struct i2c_board_info brownstone_twsi1_info[] = {
|
||||
|
|
|
@ -23,10 +23,11 @@
|
|||
#include <mach/addr-map.h>
|
||||
#include <mach/mfp-mmp2.h>
|
||||
#include <mach/mmp2.h>
|
||||
#include <mach/irqs.h>
|
||||
|
||||
#include "common.h"
|
||||
|
||||
#define FLINT_NR_IRQS (IRQ_BOARD_START + 48)
|
||||
#define FLINT_NR_IRQS (MMP_NR_IRQS + 48)
|
||||
|
||||
static unsigned long flint_pin_config[] __initdata = {
|
||||
/* UART1 */
|
||||
|
|
|
@ -191,7 +191,7 @@ static void __init gplugd_init(void)
|
|||
|
||||
MACHINE_START(GPLUGD, "PXA168-based GuruPlug Display (gplugD) Platform")
|
||||
.map_io = mmp_map_io,
|
||||
.nr_irqs = IRQ_BOARD_START,
|
||||
.nr_irqs = MMP_NR_IRQS,
|
||||
.init_irq = pxa168_init_irq,
|
||||
.timer = &pxa168_timer,
|
||||
.init_machine = gplugd_init,
|
||||
|
|
|
@ -223,7 +223,6 @@
|
|||
#define MMP_GPIO_TO_IRQ(gpio) (IRQ_GPIO_START + (gpio))
|
||||
|
||||
#define IRQ_BOARD_START (IRQ_GPIO_START + MMP_NR_BUILTIN_GPIO)
|
||||
|
||||
#define NR_IRQS (IRQ_BOARD_START)
|
||||
#define MMP_NR_IRQS IRQ_BOARD_START
|
||||
|
||||
#endif /* __ASM_MACH_IRQS_H */
|
||||
|
|
|
@ -1,16 +0,0 @@
|
|||
/*
|
||||
* linux/arch/arm/mach-mmp/include/mach/system.h
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef __ASM_MACH_SYSTEM_H
|
||||
#define __ASM_MACH_SYSTEM_H
|
||||
|
||||
static inline void arch_idle(void)
|
||||
{
|
||||
cpu_do_idle();
|
||||
}
|
||||
#endif /* __ASM_MACH_SYSTEM_H */
|
|
@ -15,6 +15,7 @@
|
|||
#include <linux/irq.h>
|
||||
#include <linux/io.h>
|
||||
|
||||
#include <mach/irqs.h>
|
||||
#include <mach/regs-icu.h>
|
||||
#include <mach/mmp2.h>
|
||||
|
||||
|
|
|
@ -19,6 +19,7 @@
|
|||
#include <linux/mfd/max8925.h>
|
||||
#include <linux/interrupt.h>
|
||||
|
||||
#include <mach/irqs.h>
|
||||
#include <asm/mach-types.h>
|
||||
#include <asm/mach/arch.h>
|
||||
#include <mach/addr-map.h>
|
||||
|
@ -27,7 +28,7 @@
|
|||
|
||||
#include "common.h"
|
||||
|
||||
#define JASPER_NR_IRQS (IRQ_BOARD_START + 48)
|
||||
#define JASPER_NR_IRQS (MMP_NR_IRQS + 48)
|
||||
|
||||
static unsigned long jasper_pin_config[] __initdata = {
|
||||
/* UART1 */
|
||||
|
@ -135,7 +136,7 @@ static struct max8925_power_pdata jasper_power_data = {
|
|||
static struct max8925_platform_data jasper_max8925_info = {
|
||||
.backlight = &jasper_backlight_data,
|
||||
.power = &jasper_power_data,
|
||||
.irq_base = IRQ_BOARD_START,
|
||||
.irq_base = MMP_NR_IRQS,
|
||||
};
|
||||
|
||||
static struct i2c_board_info jasper_twsi1_info[] = {
|
||||
|
|
|
@ -102,6 +102,7 @@ static void __init tavorevb_init(void)
|
|||
|
||||
MACHINE_START(TAVOREVB, "PXA910 Evaluation Board (aka TavorEVB)")
|
||||
.map_io = mmp_map_io,
|
||||
.nr_irqs = MMP_NR_IRQS,
|
||||
.init_irq = pxa910_init_irq,
|
||||
.timer = &pxa910_timer,
|
||||
.init_machine = tavorevb_init,
|
||||
|
|
|
@ -26,6 +26,7 @@
|
|||
#include <mach/mfp-pxa168.h>
|
||||
#include <mach/pxa168.h>
|
||||
#include <mach/teton_bga.h>
|
||||
#include <mach/irqs.h>
|
||||
|
||||
#include "common.h"
|
||||
|
||||
|
@ -83,7 +84,7 @@ static void __init teton_bga_init(void)
|
|||
|
||||
MACHINE_START(TETON_BGA, "PXA168-based Teton BGA Development Platform")
|
||||
.map_io = mmp_map_io,
|
||||
.nr_irqs = IRQ_BOARD_START,
|
||||
.nr_irqs = MMP_NR_IRQS,
|
||||
.init_irq = pxa168_init_irq,
|
||||
.timer = &pxa168_timer,
|
||||
.init_machine = teton_bga_init,
|
||||
|
|
|
@ -38,7 +38,7 @@
|
|||
* 16 board interrupts -- PCA9575 GPIO expander
|
||||
* 24 board interrupts -- 88PM860x PMIC
|
||||
*/
|
||||
#define TTCDKB_NR_IRQS (IRQ_BOARD_START + 16 + 16 + 24)
|
||||
#define TTCDKB_NR_IRQS (MMP_NR_IRQS + 16 + 16 + 24)
|
||||
|
||||
static unsigned long ttc_dkb_pin_config[] __initdata = {
|
||||
/* UART2 */
|
||||
|
@ -130,7 +130,7 @@ static struct platform_device *ttc_dkb_devices[] = {
|
|||
static struct pca953x_platform_data max7312_data[] = {
|
||||
{
|
||||
.gpio_base = TTCDKB_GPIO_EXT0(0),
|
||||
.irq_base = IRQ_BOARD_START,
|
||||
.irq_base = MMP_NR_IRQS,
|
||||
},
|
||||
};
|
||||
|
||||
|
|
|
@ -1,36 +0,0 @@
|
|||
/* arch/arm/mach-msm/include/mach/idle.S
|
||||
*
|
||||
* Idle processing for MSM7K - work around bugs with SWFI.
|
||||
*
|
||||
* Copyright (c) 2007 QUALCOMM Incorporated.
|
||||
* Copyright (C) 2007 Google, Inc.
|
||||
*
|
||||
* This software is licensed under the terms of the GNU General Public
|
||||
* License version 2, as published by the Free Software Foundation, and
|
||||
* may be copied, distributed, and modified under those terms.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
*/
|
||||
|
||||
#include <linux/linkage.h>
|
||||
#include <asm/assembler.h>
|
||||
|
||||
ENTRY(arch_idle)
|
||||
#ifdef CONFIG_MSM7X00A_IDLE
|
||||
mrc p15, 0, r1, c1, c0, 0 /* read current CR */
|
||||
bic r0, r1, #(1 << 2) /* clear dcache bit */
|
||||
bic r0, r0, #(1 << 12) /* clear icache bit */
|
||||
mcr p15, 0, r0, c1, c0, 0 /* disable d/i cache */
|
||||
|
||||
mov r0, #0 /* prepare wfi value */
|
||||
mcr p15, 0, r0, c7, c10, 0 /* flush the cache */
|
||||
mcr p15, 0, r0, c7, c10, 4 /* memory barrier */
|
||||
mcr p15, 0, r0, c7, c0, 4 /* wait for interrupt */
|
||||
|
||||
mcr p15, 0, r1, c1, c0, 0 /* restore d/i cache */
|
||||
#endif
|
||||
mov pc, lr
|
49
arch/arm/mach-msm/idle.c
Normal file
49
arch/arm/mach-msm/idle.c
Normal file
|
@ -0,0 +1,49 @@
|
|||
/* arch/arm/mach-msm/idle.c
|
||||
*
|
||||
* Idle processing for MSM7K - work around bugs with SWFI.
|
||||
*
|
||||
* Copyright (c) 2007 QUALCOMM Incorporated.
|
||||
* Copyright (C) 2007 Google, Inc.
|
||||
*
|
||||
* This software is licensed under the terms of the GNU General Public
|
||||
* License version 2, as published by the Free Software Foundation, and
|
||||
* may be copied, distributed, and modified under those terms.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
*/
|
||||
|
||||
#include <linux/init.h>
|
||||
#include <asm/system.h>
|
||||
|
||||
static void msm_idle(void)
|
||||
{
|
||||
#ifdef CONFIG_MSM7X00A_IDLE
|
||||
asm volatile (
|
||||
|
||||
"mrc p15, 0, r1, c1, c0, 0 /* read current CR */ \n\t"
|
||||
"bic r0, r1, #(1 << 2) /* clear dcache bit */ \n\t"
|
||||
"bic r0, r0, #(1 << 12) /* clear icache bit */ \n\t"
|
||||
"mcr p15, 0, r0, c1, c0, 0 /* disable d/i cache */ \n\t"
|
||||
|
||||
"mov r0, #0 /* prepare wfi value */ \n\t"
|
||||
"mcr p15, 0, r0, c7, c10, 0 /* flush the cache */ \n\t"
|
||||
"mcr p15, 0, r0, c7, c10, 4 /* memory barrier */ \n\t"
|
||||
"mcr p15, 0, r0, c7, c0, 4 /* wait for interrupt */ \n\t"
|
||||
|
||||
"mcr p15, 0, r1, c1, c0, 0 /* restore d/i cache */ \n\t"
|
||||
|
||||
: : : "r0","r1" );
|
||||
#endif
|
||||
}
|
||||
|
||||
static int __init msm_idle_init(void)
|
||||
{
|
||||
arm_pm_idle = msm_idle;
|
||||
return 0;
|
||||
}
|
||||
|
||||
arch_initcall(msm_idle_init);
|
|
@ -12,7 +12,6 @@
|
|||
* GNU General Public License for more details.
|
||||
*
|
||||
*/
|
||||
void arch_idle(void);
|
||||
|
||||
/* low level hardware reset hook -- for example, hitting the
|
||||
* PSHOLD line on the PMIC to hard reset the system
|
||||
|
|
|
@ -24,6 +24,7 @@
|
|||
#include <asm/mach/time.h>
|
||||
#include <asm/hardware/gic.h>
|
||||
#include <asm/localtimer.h>
|
||||
#include <asm/sched_clock.h>
|
||||
|
||||
#include <mach/msm_iomap.h>
|
||||
#include <mach/cpu.h>
|
||||
|
@ -105,12 +106,12 @@ static union {
|
|||
|
||||
static void __iomem *source_base;
|
||||
|
||||
static cycle_t msm_read_timer_count(struct clocksource *cs)
|
||||
static notrace cycle_t msm_read_timer_count(struct clocksource *cs)
|
||||
{
|
||||
return readl_relaxed(source_base + TIMER_COUNT_VAL);
|
||||
}
|
||||
|
||||
static cycle_t msm_read_timer_count_shift(struct clocksource *cs)
|
||||
static notrace cycle_t msm_read_timer_count_shift(struct clocksource *cs)
|
||||
{
|
||||
/*
|
||||
* Shift timer count down by a constant due to unreliable lower bits
|
||||
|
@ -127,6 +128,11 @@ static struct clocksource msm_clocksource = {
|
|||
.flags = CLOCK_SOURCE_IS_CONTINUOUS,
|
||||
};
|
||||
|
||||
static notrace u32 msm_sched_clock_read(void)
|
||||
{
|
||||
return msm_clocksource.read(&msm_clocksource);
|
||||
}
|
||||
|
||||
static void __init msm_timer_init(void)
|
||||
{
|
||||
struct clock_event_device *ce = &msm_clockevent;
|
||||
|
@ -189,6 +195,8 @@ err:
|
|||
res = clocksource_register_hz(cs, dgt_hz);
|
||||
if (res)
|
||||
pr_err("clocksource_register failed\n");
|
||||
setup_sched_clock(msm_sched_clock_read,
|
||||
cpu_is_msm7x01() ? 32 - MSM_DGT_SHIFT : 32, dgt_hz);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_LOCAL_TIMERS
|
||||
|
|
|
@ -1,17 +0,0 @@
|
|||
/*
|
||||
* arch/arm/mach-mv78xx0/include/mach/system.h
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without any
|
||||
* warranty of any kind, whether express or implied.
|
||||
*/
|
||||
|
||||
#ifndef __ASM_ARCH_SYSTEM_H
|
||||
#define __ASM_ARCH_SYSTEM_H
|
||||
|
||||
static inline void arch_idle(void)
|
||||
{
|
||||
cpu_do_idle();
|
||||
}
|
||||
|
||||
#endif
|
|
@ -26,23 +26,17 @@ static struct clk *gpc_dvfs_clk;
|
|||
|
||||
static void imx5_idle(void)
|
||||
{
|
||||
if (!need_resched()) {
|
||||
/* gpc clock is needed for SRPG */
|
||||
if (gpc_dvfs_clk == NULL) {
|
||||
gpc_dvfs_clk = clk_get(NULL, "gpc_dvfs");
|
||||
if (IS_ERR(gpc_dvfs_clk))
|
||||
goto err0;
|
||||
}
|
||||
clk_enable(gpc_dvfs_clk);
|
||||
mx5_cpu_lp_set(WAIT_UNCLOCKED_POWER_OFF);
|
||||
if (tzic_enable_wake())
|
||||
goto err1;
|
||||
cpu_do_idle();
|
||||
err1:
|
||||
clk_disable(gpc_dvfs_clk);
|
||||
/* gpc clock is needed for SRPG */
|
||||
if (gpc_dvfs_clk == NULL) {
|
||||
gpc_dvfs_clk = clk_get(NULL, "gpc_dvfs");
|
||||
if (IS_ERR(gpc_dvfs_clk))
|
||||
return;
|
||||
}
|
||||
err0:
|
||||
local_irq_enable();
|
||||
clk_enable(gpc_dvfs_clk);
|
||||
mx5_cpu_lp_set(WAIT_UNCLOCKED_POWER_OFF);
|
||||
if (tzic_enable_wake() != 0)
|
||||
cpu_do_idle();
|
||||
clk_disable(gpc_dvfs_clk);
|
||||
}
|
||||
|
||||
/*
|
||||
|
@ -108,7 +102,7 @@ void __init imx51_init_early(void)
|
|||
mxc_set_cpu_type(MXC_CPU_MX51);
|
||||
mxc_iomux_v3_init(MX51_IO_ADDRESS(MX51_IOMUXC_BASE_ADDR));
|
||||
mxc_arch_reset_init(MX51_IO_ADDRESS(MX51_WDOG1_BASE_ADDR));
|
||||
pm_idle = imx5_idle;
|
||||
arm_pm_idle = imx5_idle;
|
||||
}
|
||||
|
||||
void __init imx53_init_early(void)
|
||||
|
|
|
@ -77,16 +77,18 @@ err:
|
|||
|
||||
int __init mxs_add_amba_device(const struct amba_device *dev)
|
||||
{
|
||||
struct amba_device *adev = kmalloc(sizeof(*adev), GFP_KERNEL);
|
||||
struct amba_device *adev = amba_device_alloc(dev->dev.init_name,
|
||||
dev->res.start, resource_size(&dev->res));
|
||||
|
||||
if (!adev) {
|
||||
pr_err("%s: failed to allocate memory", __func__);
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
*adev = *dev;
|
||||
adev->irq[0] = dev->irq[0];
|
||||
adev->irq[1] = dev->irq[1];
|
||||
|
||||
return amba_device_register(adev, &iomem_resource);
|
||||
return amba_device_add(adev, &iomem_resource);
|
||||
}
|
||||
|
||||
struct device mxs_apbh_bus = {
|
||||
|
|
|
@ -23,7 +23,7 @@ const struct amba_device name##_device __initconst = { \
|
|||
.end = (soc ## _DUART_BASE_ADDR) + SZ_8K - 1, \
|
||||
.flags = IORESOURCE_MEM, \
|
||||
}, \
|
||||
.irq = {soc ## _INT_DUART, NO_IRQ}, \
|
||||
.irq = {soc ## _INT_DUART}, \
|
||||
}
|
||||
|
||||
#ifdef CONFIG_SOC_IMX23
|
||||
|
|
|
@ -1,25 +0,0 @@
|
|||
/*
|
||||
* Copyright (C) 1999 ARM Limited
|
||||
* Copyright (C) 2000 Deep Blue Solutions Ltd
|
||||
* Copyright 2004-2008 Freescale Semiconductor, Inc. All Rights Reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef __MACH_MXS_SYSTEM_H__
|
||||
#define __MACH_MXS_SYSTEM_H__
|
||||
|
||||
static inline void arch_idle(void)
|
||||
{
|
||||
cpu_do_idle();
|
||||
}
|
||||
|
||||
#endif /* __MACH_MXS_SYSTEM_H__ */
|
|
@ -15,13 +15,12 @@
|
|||
#include <linux/kernel.h>
|
||||
#include <linux/suspend.h>
|
||||
#include <linux/io.h>
|
||||
#include <mach/system.h>
|
||||
|
||||
static int mxs_suspend_enter(suspend_state_t state)
|
||||
{
|
||||
switch (state) {
|
||||
case PM_SUSPEND_MEM:
|
||||
arch_idle();
|
||||
cpu_do_idle();
|
||||
break;
|
||||
|
||||
default:
|
||||
|
|
|
@ -92,18 +92,7 @@ void clk_put(struct clk *clk)
|
|||
{
|
||||
}
|
||||
|
||||
static struct amba_device fb_device = {
|
||||
.dev = {
|
||||
.init_name = "fb",
|
||||
.coherent_dma_mask = ~0,
|
||||
},
|
||||
.res = {
|
||||
.start = 0x00104000,
|
||||
.end = 0x00104fff,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
.irq = { NETX_IRQ_LCD, NO_IRQ },
|
||||
};
|
||||
static AMBA_AHB_DEVICE(fb, "fb", 0, 0x00104000, { NETX_IRQ_LCD }, NULL);
|
||||
|
||||
int netx_fb_init(struct clcd_board *board, struct clcd_panel *panel)
|
||||
{
|
||||
|
|
|
@ -1,28 +0,0 @@
|
|||
/*
|
||||
* arch/arm/mach-netx/include/mach/system.h
|
||||
*
|
||||
* Copyright (C) 2005 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2
|
||||
* as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
#ifndef __ASM_ARCH_SYSTEM_H
|
||||
#define __ASM_ARCH_SYSTEM_H
|
||||
|
||||
static inline void arch_idle(void)
|
||||
{
|
||||
cpu_do_idle();
|
||||
}
|
||||
|
||||
#endif
|
||||
|
|
@ -185,20 +185,11 @@ static void __init nhk8815_onenand_init(void)
|
|||
#endif
|
||||
}
|
||||
|
||||
#define __MEM_4K_RESOURCE(x) \
|
||||
.res = {.start = (x), .end = (x) + SZ_4K - 1, .flags = IORESOURCE_MEM}
|
||||
static AMBA_APB_DEVICE(uart0, "uart0", 0, NOMADIK_UART0_BASE,
|
||||
{ IRQ_UART0 }, NULL);
|
||||
|
||||
static struct amba_device uart0_device = {
|
||||
.dev = { .init_name = "uart0" },
|
||||
__MEM_4K_RESOURCE(NOMADIK_UART0_BASE),
|
||||
.irq = {IRQ_UART0, NO_IRQ},
|
||||
};
|
||||
|
||||
static struct amba_device uart1_device = {
|
||||
.dev = { .init_name = "uart1" },
|
||||
__MEM_4K_RESOURCE(NOMADIK_UART1_BASE),
|
||||
.irq = {IRQ_UART1, NO_IRQ},
|
||||
};
|
||||
static AMBA_APB_DEVICE(uart1, "uart1", 0, NOMADIK_UART1_BASE,
|
||||
{ IRQ_UART1 }, NULL);
|
||||
|
||||
static struct amba_device *amba_devs[] __initdata = {
|
||||
&uart0_device,
|
||||
|
|
|
@ -97,12 +97,7 @@ static struct platform_device cpu8815_platform_gpio[] = {
|
|||
GPIO_DEVICE(3),
|
||||
};
|
||||
|
||||
static struct amba_device cpu8815_amba_rng = {
|
||||
.dev = {
|
||||
.init_name = "rng",
|
||||
},
|
||||
__MEM_4K_RESOURCE(NOMADIK_RNG_BASE),
|
||||
};
|
||||
static AMBA_APB_DEVICE(cpu8815_amba_rng, "rng", 0, NOMADIK_RNG_BASE, { }, NULL);
|
||||
|
||||
static struct platform_device *platform_devs[] __initdata = {
|
||||
cpu8815_platform_gpio + 0,
|
||||
|
@ -112,7 +107,7 @@ static struct platform_device *platform_devs[] __initdata = {
|
|||
};
|
||||
|
||||
static struct amba_device *amba_devs[] __initdata = {
|
||||
&cpu8815_amba_rng
|
||||
&cpu8815_amba_rng_device
|
||||
};
|
||||
|
||||
static int __init cpu8815_init(void)
|
||||
|
|
|
@ -1,32 +0,0 @@
|
|||
/*
|
||||
* mach-nomadik/include/mach/system.h
|
||||
*
|
||||
* Copyright (C) 2008 STMicroelectronics
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
#ifndef __ASM_ARCH_SYSTEM_H
|
||||
#define __ASM_ARCH_SYSTEM_H
|
||||
|
||||
static inline void arch_idle(void)
|
||||
{
|
||||
/*
|
||||
* This should do all the clock switching
|
||||
* and wait for interrupt tricks
|
||||
*/
|
||||
cpu_do_idle();
|
||||
}
|
||||
|
||||
#endif
|
|
@ -1,5 +0,0 @@
|
|||
/*
|
||||
* arch/arm/mach-omap1/include/mach/system.h
|
||||
*/
|
||||
|
||||
#include <plat/system.h>
|
|
@ -42,9 +42,9 @@
|
|||
#include <linux/sysfs.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/atomic.h>
|
||||
|
||||
#include <asm/irq.h>
|
||||
#include <linux/atomic.h>
|
||||
#include <asm/mach/time.h>
|
||||
#include <asm/mach/irq.h>
|
||||
|
||||
|
@ -108,13 +108,7 @@ void omap1_pm_idle(void)
|
|||
__u32 use_idlect1 = arm_idlect1_mask;
|
||||
int do_sleep = 0;
|
||||
|
||||
local_irq_disable();
|
||||
local_fiq_disable();
|
||||
if (need_resched()) {
|
||||
local_fiq_enable();
|
||||
local_irq_enable();
|
||||
return;
|
||||
}
|
||||
|
||||
#if defined(CONFIG_OMAP_MPU_TIMER) && !defined(CONFIG_OMAP_DM_TIMER)
|
||||
#warning Enable 32kHz OS timer in order to allow sleep states in idle
|
||||
|
@ -157,14 +151,12 @@ void omap1_pm_idle(void)
|
|||
omap_writel(saved_idlect1, ARM_IDLECT1);
|
||||
|
||||
local_fiq_enable();
|
||||
local_irq_enable();
|
||||
return;
|
||||
}
|
||||
omap_sram_suspend(omap_readl(ARM_IDLECT1),
|
||||
omap_readl(ARM_IDLECT2));
|
||||
|
||||
local_fiq_enable();
|
||||
local_irq_enable();
|
||||
}
|
||||
|
||||
/*
|
||||
|
@ -583,8 +575,6 @@ static void omap_pm_init_proc(void)
|
|||
|
||||
#endif /* DEBUG && CONFIG_PROC_FS */
|
||||
|
||||
static void (*saved_idle)(void) = NULL;
|
||||
|
||||
/*
|
||||
* omap_pm_prepare - Do preliminary suspend work.
|
||||
*
|
||||
|
@ -592,8 +582,7 @@ static void (*saved_idle)(void) = NULL;
|
|||
static int omap_pm_prepare(void)
|
||||
{
|
||||
/* We cannot sleep in idle until we have resumed */
|
||||
saved_idle = pm_idle;
|
||||
pm_idle = NULL;
|
||||
disable_hlt();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
@ -630,7 +619,7 @@ static int omap_pm_enter(suspend_state_t state)
|
|||
|
||||
static void omap_pm_finish(void)
|
||||
{
|
||||
pm_idle = saved_idle;
|
||||
enable_hlt();
|
||||
}
|
||||
|
||||
|
||||
|
@ -687,7 +676,7 @@ static int __init omap_pm_init(void)
|
|||
return -ENODEV;
|
||||
}
|
||||
|
||||
pm_idle = omap1_pm_idle;
|
||||
arm_pm_idle = omap1_pm_idle;
|
||||
|
||||
if (cpu_is_omap7xx())
|
||||
setup_irq(INT_7XX_WAKE_UP_REQ, &omap_wakeup_irq);
|
||||
|
|
|
@ -30,29 +30,8 @@ MODULE_AUTHOR("Alexander Shishkin");
|
|||
#define ETB_BASE (L4_EMU_34XX_PHYS + 0x1b000)
|
||||
#define DAPCTL (L4_EMU_34XX_PHYS + 0x1d000)
|
||||
|
||||
static struct amba_device omap3_etb_device = {
|
||||
.dev = {
|
||||
.init_name = "etb",
|
||||
},
|
||||
.res = {
|
||||
.start = ETB_BASE,
|
||||
.end = ETB_BASE + SZ_4K - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
.periphid = 0x000bb907,
|
||||
};
|
||||
|
||||
static struct amba_device omap3_etm_device = {
|
||||
.dev = {
|
||||
.init_name = "etm",
|
||||
},
|
||||
.res = {
|
||||
.start = ETM_BASE,
|
||||
.end = ETM_BASE + SZ_4K - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
.periphid = 0x102bb921,
|
||||
};
|
||||
static AMBA_APB_DEVICE(omap3_etb, "etb", 0x000bb907, ETB_BASE, { }, NULL);
|
||||
static AMBA_APB_DEVICE(omap3_etm, "etm", 0x102bb921, ETM_BASE, { }, NULL);
|
||||
|
||||
static int __init emu_init(void)
|
||||
{
|
||||
|
@ -66,4 +45,3 @@ static int __init emu_init(void)
|
|||
}
|
||||
|
||||
subsys_initcall(emu_init);
|
||||
|
||||
|
|
|
@ -1,5 +0,0 @@
|
|||
/*
|
||||
* arch/arm/mach-omap2/include/mach/system.h
|
||||
*/
|
||||
|
||||
#include <plat/system.h>
|
|
@ -232,7 +232,6 @@ static int omap2_can_sleep(void)
|
|||
|
||||
static void omap2_pm_idle(void)
|
||||
{
|
||||
local_irq_disable();
|
||||
local_fiq_disable();
|
||||
|
||||
if (!omap2_can_sleep()) {
|
||||
|
@ -249,7 +248,6 @@ static void omap2_pm_idle(void)
|
|||
|
||||
out:
|
||||
local_fiq_enable();
|
||||
local_irq_enable();
|
||||
}
|
||||
|
||||
#ifdef CONFIG_SUSPEND
|
||||
|
@ -468,7 +466,7 @@ static int __init omap2_pm_init(void)
|
|||
}
|
||||
|
||||
suspend_set_ops(&omap_pm_ops);
|
||||
pm_idle = omap2_pm_idle;
|
||||
arm_pm_idle = omap2_pm_idle;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
|
@ -418,10 +418,9 @@ void omap_sram_idle(void)
|
|||
|
||||
static void omap3_pm_idle(void)
|
||||
{
|
||||
local_irq_disable();
|
||||
local_fiq_disable();
|
||||
|
||||
if (omap_irq_pending() || need_resched())
|
||||
if (omap_irq_pending())
|
||||
goto out;
|
||||
|
||||
trace_power_start(POWER_CSTATE, 1, smp_processor_id());
|
||||
|
@ -434,7 +433,6 @@ static void omap3_pm_idle(void)
|
|||
|
||||
out:
|
||||
local_fiq_enable();
|
||||
local_irq_enable();
|
||||
}
|
||||
|
||||
#ifdef CONFIG_SUSPEND
|
||||
|
@ -848,7 +846,7 @@ static int __init omap3_pm_init(void)
|
|||
suspend_set_ops(&omap_pm_ops);
|
||||
#endif /* CONFIG_SUSPEND */
|
||||
|
||||
pm_idle = omap3_pm_idle;
|
||||
arm_pm_idle = omap3_pm_idle;
|
||||
omap3_idle_init();
|
||||
|
||||
/*
|
||||
|
|
|
@ -173,18 +173,16 @@ static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused)
|
|||
* omap_default_idle - OMAP4 default ilde routine.'
|
||||
*
|
||||
* Implements OMAP4 memory, IO ordering requirements which can't be addressed
|
||||
* with default arch_idle() hook. Used by all CPUs with !CONFIG_CPUIDLE and
|
||||
* with default cpu_do_idle() hook. Used by all CPUs with !CONFIG_CPUIDLE and
|
||||
* by secondary CPU with CONFIG_CPUIDLE.
|
||||
*/
|
||||
static void omap_default_idle(void)
|
||||
{
|
||||
local_irq_disable();
|
||||
local_fiq_disable();
|
||||
|
||||
omap_do_wfi();
|
||||
|
||||
local_fiq_enable();
|
||||
local_irq_enable();
|
||||
}
|
||||
|
||||
/**
|
||||
|
@ -255,8 +253,8 @@ static int __init omap4_pm_init(void)
|
|||
suspend_set_ops(&omap_pm_ops);
|
||||
#endif /* CONFIG_SUSPEND */
|
||||
|
||||
/* Overwrite the default arch_idle() */
|
||||
pm_idle = omap_default_idle;
|
||||
/* Overwrite the default cpu_do_idle() */
|
||||
arm_pm_idle = omap_default_idle;
|
||||
|
||||
omap4_idle_init();
|
||||
|
||||
|
|
|
@ -24,7 +24,6 @@
|
|||
#include <linux/interrupt.h>
|
||||
#include <linux/slab.h>
|
||||
|
||||
#include <mach/system.h>
|
||||
#include <plat/common.h>
|
||||
#include <plat/prcm.h>
|
||||
#include <plat/irqs.h>
|
||||
|
|
|
@ -1,19 +0,0 @@
|
|||
/*
|
||||
* arch/arm/mach-orion5x/include/mach/system.h
|
||||
*
|
||||
* Tzachi Perelstein <tzachi@marvell.com>
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without any
|
||||
* warranty of any kind, whether express or implied.
|
||||
*/
|
||||
|
||||
#ifndef __ASM_ARCH_SYSTEM_H
|
||||
#define __ASM_ARCH_SYSTEM_H
|
||||
|
||||
static inline void arch_idle(void)
|
||||
{
|
||||
cpu_do_idle();
|
||||
}
|
||||
|
||||
#endif
|
|
@ -1,20 +0,0 @@
|
|||
/*
|
||||
* Copyright (c) 2011 Picochip Ltd., Jamie Iles
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
#ifndef __MACH_IRQS_H
|
||||
#define __MACH_IRQS_H
|
||||
|
||||
/* We dynamically allocate our irq_desc's. */
|
||||
#define NR_IRQS 0
|
||||
|
||||
#endif /* __MACH_IRQS_H */
|
|
@ -1,26 +0,0 @@
|
|||
/*
|
||||
* Copyright (c) 2011 Picochip Ltd., Jamie Iles
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
#ifndef __ASM_ARCH_SYSTEM_H
|
||||
#define __ASM_ARCH_SYSTEM_H
|
||||
|
||||
static inline void arch_idle(void)
|
||||
{
|
||||
/*
|
||||
* This should do all the clock switching and wait for interrupt
|
||||
* tricks.
|
||||
*/
|
||||
cpu_do_idle();
|
||||
}
|
||||
|
||||
#endif /* __ASM_ARCH_SYSTEM_H */
|
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