clk: divider: read-only divider can propagate rate change
When a divider clock has CLK_DIVIDER_READ_ONLY set, it means that the
register shall be left un-touched, but it does not mean the clock
should stop rate propagation if CLK_SET_RATE_PARENT is set
This is properly handled in qcom clk-regmap-divider but it was not in
the generic divider
To fix this situation, introduce a new helper function
divider_ro_round_rate, on the same model as divider_round_rate.
Fixes: e6d5e7d90b
("clk-divider: Fix READ_ONLY when divider > 1")
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Tested-By: David Lechner <david@lechnology.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
This commit is contained in:
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@ -342,19 +342,43 @@ long divider_round_rate_parent(struct clk_hw *hw, struct clk_hw *parent,
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}
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EXPORT_SYMBOL_GPL(divider_round_rate_parent);
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long divider_ro_round_rate_parent(struct clk_hw *hw, struct clk_hw *parent,
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unsigned long rate, unsigned long *prate,
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const struct clk_div_table *table, u8 width,
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unsigned long flags, unsigned int val)
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{
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int div;
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div = _get_div(table, val, flags, width);
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/* Even a read-only clock can propagate a rate change */
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if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) {
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if (!parent)
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return -EINVAL;
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*prate = clk_hw_round_rate(parent, rate * div);
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}
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return DIV_ROUND_UP_ULL((u64)*prate, div);
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}
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EXPORT_SYMBOL_GPL(divider_ro_round_rate_parent);
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static long clk_divider_round_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *prate)
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{
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struct clk_divider *divider = to_clk_divider(hw);
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int bestdiv;
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/* if read only, just return current value */
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if (divider->flags & CLK_DIVIDER_READ_ONLY) {
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bestdiv = clk_readl(divider->reg) >> divider->shift;
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bestdiv &= clk_div_mask(divider->width);
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bestdiv = _get_div(divider->table, bestdiv, divider->flags,
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divider->width);
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return DIV_ROUND_UP_ULL((u64)*prate, bestdiv);
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u32 val;
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val = clk_readl(divider->reg) >> divider->shift;
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val &= clk_div_mask(divider->width);
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return divider_ro_round_rate(hw, rate, prate, divider->table,
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divider->width, divider->flags,
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val);
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}
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return divider_round_rate(hw, rate, prate, divider->table,
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@ -420,6 +420,10 @@ long divider_round_rate_parent(struct clk_hw *hw, struct clk_hw *parent,
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unsigned long rate, unsigned long *prate,
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const struct clk_div_table *table,
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u8 width, unsigned long flags);
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long divider_ro_round_rate_parent(struct clk_hw *hw, struct clk_hw *parent,
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unsigned long rate, unsigned long *prate,
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const struct clk_div_table *table, u8 width,
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unsigned long flags, unsigned int val);
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int divider_get_val(unsigned long rate, unsigned long parent_rate,
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const struct clk_div_table *table, u8 width,
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unsigned long flags);
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@ -780,6 +784,17 @@ static inline long divider_round_rate(struct clk_hw *hw, unsigned long rate,
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rate, prate, table, width, flags);
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}
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static inline long divider_ro_round_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *prate,
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const struct clk_div_table *table,
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u8 width, unsigned long flags,
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unsigned int val)
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{
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return divider_ro_round_rate_parent(hw, clk_hw_get_parent(hw),
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rate, prate, table, width, flags,
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val);
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}
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/*
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* FIXME clock api without lock protection
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*/
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