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MLK-14438-06 net: fec: add property to define exclusive MII bus 

In defalut, most of i.MX boards share one MII bus in boards design to reduce
pins utilize, but others each MAC use their exclusive MII bus. To solve the
problem, user can select to define the mii-exclusive property in board dts file.

The patch also update binding doc.

Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
pull/10/head
Andy Duan 2017-03-14 15:50:41 +08:00 committed by Jason Liu
parent 43670f3e78
commit b16ae037b5
2 changed files with 16 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
Documentation/devicetree/bindings/net/fsl-fec.txt
View File

@ -5,6 +5,13 @@ Required properties:
- reg : Address and length of the register set for the device
- interrupts : Should contain fec interrupt
- phy-mode : See ethernet.txt file in the same directory
- clock-name: Should be the names of the clocks
- "ipg" for MAC ipg_clk_s, ipg_clk_mac_s that are for register accessing
- "ahb" for MAC ipg_clk, ipg_clk_mac that are bus clock
- "ptp" for IEEE1588 timer clock
- "enet_clk_ref" for MAC transmit/receiver reference clock
- "enet_out" output clock for external device
- clocks: Phandles to input clocks.
Optional properties:
- phy-reset-gpios : Should specify the gpio for phy reset
@ -37,6 +44,9 @@ Optional properties:
- fsl,wakeup_irq : The property define the wakeup irq index in enet irq source.
- stop-mode : If present, indicates soc need to set gpr bit to request stop
mode.
- fsl,ar8031-phy-fixup : If present, indicates board need to do phy fixup setting.
- mii-exclusive: If present, each MAC has their exclusive MDIO bus in current board
design, otherwise mutiple MACs share one MDIO bus to reduce Pins utilize.
Optional subnodes:
- mdio : specifies the mdio bus in the FEC, used as a container for phy nodes

8
drivers/net/ethernet/freescale/fec_main.c
View File

@ -2044,7 +2044,7 @@ static int fec_enet_mii_init(struct platform_device *pdev)
* mdio interface in board design, and need to be configured by
* fec0 mii_bus.
*/
if ((fep->quirks & FEC_QUIRK_ENET_MAC) && fep->dev_id > 0) {
if ((fep->quirks & FEC_QUIRK_SINGLE_MDIO) && fep->dev_id > 0) {
/* fec1 uses fec0 mii_bus */
if (mii_cnt && fec0_mii_bus) {
fep->mii_bus = fec0_mii_bus;
@ -2124,7 +2124,7 @@ static int fec_enet_mii_init(struct platform_device *pdev)
mii_cnt++;
/* save fec0 mii_bus */
if (fep->quirks & FEC_QUIRK_ENET_MAC) {
if (fep->quirks & FEC_QUIRK_SINGLE_MDIO) {
fec0_mii_bus = fep->mii_bus;
fec_mii_bus_share = &fep->mii_bus_share;
}
@ -3672,6 +3672,10 @@ fec_probe(struct platform_device *pdev)
fep->wake_irq = fep->irq[0];
init_completion(&fep->mdio_done);
/* board only enable one mii bus in default */
if (!of_get_property(np, "fsl,mii-exclusive", NULL))
fep->quirks |= FEC_QUIRK_SINGLE_MDIO;
ret = fec_enet_mii_init(pdev);
if (ret) {
dev_id = 0;