Merge remote-tracking branch 'asoc/topic/doc' into asoc-next
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b27aafedfd
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@ -48,10 +48,25 @@ struct snd_compr_stream;
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#define SND_SOC_DAIFMT_GATED (0 << 4) /* clock is gated */
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#define SND_SOC_DAIFMT_GATED (0 << 4) /* clock is gated */
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/*
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/*
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* DAI hardware signal inversions.
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* DAI hardware signal polarity.
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*
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*
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* Specifies whether the DAI can also support inverted clocks for the specified
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* Specifies whether the DAI can also support inverted clocks for the specified
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* format.
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* format.
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*
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* BCLK:
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* - "normal" polarity means signal is available at rising edge of BCLK
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* - "inverted" polarity means signal is available at falling edge of BCLK
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*
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* FSYNC "normal" polarity depends on the frame format:
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* - I2S: frame consists of left then right channel data. Left channel starts
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* with falling FSYNC edge, right channel starts with rising FSYNC edge.
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* - Left/Right Justified: frame consists of left then right channel data.
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* Left channel starts with rising FSYNC edge, right channel starts with
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* falling FSYNC edge.
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* - DSP A/B: Frame starts with rising FSYNC edge.
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* - AC97: Frame starts with rising FSYNC edge.
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*
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* "Negative" FSYNC polarity is the one opposite of "normal" polarity.
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*/
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*/
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#define SND_SOC_DAIFMT_NB_NF (0 << 8) /* normal bit clock + frame */
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#define SND_SOC_DAIFMT_NB_NF (0 << 8) /* normal bit clock + frame */
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#define SND_SOC_DAIFMT_NB_IF (2 << 8) /* normal BCLK + inv FRM */
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#define SND_SOC_DAIFMT_NB_IF (2 << 8) /* normal BCLK + inv FRM */
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