Merge branch 'clockevents/4.19' of git://git.linaro.org/people/daniel.lezcano/linux into timers/core
Pull clockevent/source changes from Daniel Lezcano: - Add a less accurate but always-on clocksource for the sprd platform (Baoling Wang) - Add the system timer for the new mediatek platforms (Stanley Chu) - Change the cpumask to cpu_possible_mask (Sudeep Holla)zero-colors
Thomas Gleixner
commit
b2ab472dc1
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@ -1,19 +1,25 @@
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Mediatek MT6577, MT6572 and MT6589 Timers
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---------------------------------------
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Mediatek Timers
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---------------
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Mediatek SoCs have two different timers on different platforms,
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- GPT (General Purpose Timer)
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- SYST (System Timer)
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The proper timer will be selected automatically by driver.
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Required properties:
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- compatible should contain:
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* "mediatek,mt2701-timer" for MT2701 compatible timers
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* "mediatek,mt6580-timer" for MT6580 compatible timers
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* "mediatek,mt6589-timer" for MT6589 compatible timers
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* "mediatek,mt7623-timer" for MT7623 compatible timers
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* "mediatek,mt8127-timer" for MT8127 compatible timers
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* "mediatek,mt8135-timer" for MT8135 compatible timers
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* "mediatek,mt8173-timer" for MT8173 compatible timers
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* "mediatek,mt6577-timer" for MT6577 and all above compatible timers
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- reg: Should contain location and length for timers register.
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- clocks: Clocks driving the timer hardware. This list should include two
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clocks. The order is system clock and as second clock the RTC clock.
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* "mediatek,mt2701-timer" for MT2701 compatible timers (GPT)
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* "mediatek,mt6580-timer" for MT6580 compatible timers (GPT)
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* "mediatek,mt6589-timer" for MT6589 compatible timers (GPT)
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* "mediatek,mt7623-timer" for MT7623 compatible timers (GPT)
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* "mediatek,mt8127-timer" for MT8127 compatible timers (GPT)
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* "mediatek,mt8135-timer" for MT8135 compatible timers (GPT)
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* "mediatek,mt8173-timer" for MT8173 compatible timers (GPT)
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* "mediatek,mt6577-timer" for MT6577 and all above compatible timers (GPT)
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* "mediatek,mt6765-timer" for MT6765 compatible timers (SYST)
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- reg: Should contain location and length for timer register.
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- clocks: Should contain system clock.
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Examples:
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@ -21,5 +27,5 @@ Examples:
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compatible = "mediatek,mt6577-timer";
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reg = <0x10008000 0x80>;
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interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&system_clk>, <&rtc_clk>;
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clocks = <&system_clk>;
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};
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@ -49,7 +49,7 @@ obj-$(CONFIG_CLKSRC_SAMSUNG_PWM) += samsung_pwm_timer.o
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obj-$(CONFIG_FSL_FTM_TIMER) += fsl_ftm_timer.o
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obj-$(CONFIG_VF_PIT_TIMER) += vf_pit_timer.o
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obj-$(CONFIG_CLKSRC_QCOM) += qcom-timer.o
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obj-$(CONFIG_MTK_TIMER) += mtk_timer.o
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obj-$(CONFIG_MTK_TIMER) += timer-mediatek.o
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obj-$(CONFIG_CLKSRC_PISTACHIO) += time-pistachio.o
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obj-$(CONFIG_CLKSRC_TI_32K) += timer-ti-32k.o
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obj-$(CONFIG_CLKSRC_NPS) += timer-nps.o
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@ -1,268 +0,0 @@
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/*
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* Mediatek SoCs General-Purpose Timer handling.
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*
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* Copyright (C) 2014 Matthias Brugger
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*
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* Matthias Brugger <matthias.bgg@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
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#include <linux/clk.h>
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#include <linux/clockchips.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/irqreturn.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/sched_clock.h>
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#include <linux/slab.h>
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#define GPT_IRQ_EN_REG 0x00
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#define GPT_IRQ_ENABLE(val) BIT((val) - 1)
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#define GPT_IRQ_ACK_REG 0x08
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#define GPT_IRQ_ACK(val) BIT((val) - 1)
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#define TIMER_CTRL_REG(val) (0x10 * (val))
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#define TIMER_CTRL_OP(val) (((val) & 0x3) << 4)
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#define TIMER_CTRL_OP_ONESHOT (0)
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#define TIMER_CTRL_OP_REPEAT (1)
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#define TIMER_CTRL_OP_FREERUN (3)
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#define TIMER_CTRL_CLEAR (2)
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#define TIMER_CTRL_ENABLE (1)
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#define TIMER_CTRL_DISABLE (0)
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#define TIMER_CLK_REG(val) (0x04 + (0x10 * (val)))
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#define TIMER_CLK_SRC(val) (((val) & 0x1) << 4)
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#define TIMER_CLK_SRC_SYS13M (0)
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#define TIMER_CLK_SRC_RTC32K (1)
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#define TIMER_CLK_DIV1 (0x0)
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#define TIMER_CLK_DIV2 (0x1)
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#define TIMER_CNT_REG(val) (0x08 + (0x10 * (val)))
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#define TIMER_CMP_REG(val) (0x0C + (0x10 * (val)))
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#define GPT_CLK_EVT 1
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#define GPT_CLK_SRC 2
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struct mtk_clock_event_device {
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void __iomem *gpt_base;
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u32 ticks_per_jiffy;
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struct clock_event_device dev;
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};
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static void __iomem *gpt_sched_reg __read_mostly;
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static u64 notrace mtk_read_sched_clock(void)
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{
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return readl_relaxed(gpt_sched_reg);
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}
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static inline struct mtk_clock_event_device *to_mtk_clk(
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struct clock_event_device *c)
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{
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return container_of(c, struct mtk_clock_event_device, dev);
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}
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static void mtk_clkevt_time_stop(struct mtk_clock_event_device *evt, u8 timer)
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{
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u32 val;
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val = readl(evt->gpt_base + TIMER_CTRL_REG(timer));
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writel(val & ~TIMER_CTRL_ENABLE, evt->gpt_base +
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TIMER_CTRL_REG(timer));
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}
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static void mtk_clkevt_time_setup(struct mtk_clock_event_device *evt,
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unsigned long delay, u8 timer)
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{
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writel(delay, evt->gpt_base + TIMER_CMP_REG(timer));
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}
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static void mtk_clkevt_time_start(struct mtk_clock_event_device *evt,
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bool periodic, u8 timer)
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{
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u32 val;
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/* Acknowledge interrupt */
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writel(GPT_IRQ_ACK(timer), evt->gpt_base + GPT_IRQ_ACK_REG);
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val = readl(evt->gpt_base + TIMER_CTRL_REG(timer));
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/* Clear 2 bit timer operation mode field */
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val &= ~TIMER_CTRL_OP(0x3);
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if (periodic)
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val |= TIMER_CTRL_OP(TIMER_CTRL_OP_REPEAT);
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else
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val |= TIMER_CTRL_OP(TIMER_CTRL_OP_ONESHOT);
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writel(val | TIMER_CTRL_ENABLE | TIMER_CTRL_CLEAR,
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evt->gpt_base + TIMER_CTRL_REG(timer));
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}
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static int mtk_clkevt_shutdown(struct clock_event_device *clk)
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{
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mtk_clkevt_time_stop(to_mtk_clk(clk), GPT_CLK_EVT);
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return 0;
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}
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static int mtk_clkevt_set_periodic(struct clock_event_device *clk)
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{
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struct mtk_clock_event_device *evt = to_mtk_clk(clk);
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mtk_clkevt_time_stop(evt, GPT_CLK_EVT);
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mtk_clkevt_time_setup(evt, evt->ticks_per_jiffy, GPT_CLK_EVT);
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mtk_clkevt_time_start(evt, true, GPT_CLK_EVT);
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return 0;
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}
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static int mtk_clkevt_next_event(unsigned long event,
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struct clock_event_device *clk)
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{
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struct mtk_clock_event_device *evt = to_mtk_clk(clk);
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mtk_clkevt_time_stop(evt, GPT_CLK_EVT);
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mtk_clkevt_time_setup(evt, event, GPT_CLK_EVT);
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mtk_clkevt_time_start(evt, false, GPT_CLK_EVT);
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return 0;
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}
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static irqreturn_t mtk_timer_interrupt(int irq, void *dev_id)
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{
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struct mtk_clock_event_device *evt = dev_id;
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/* Acknowledge timer0 irq */
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writel(GPT_IRQ_ACK(GPT_CLK_EVT), evt->gpt_base + GPT_IRQ_ACK_REG);
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evt->dev.event_handler(&evt->dev);
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return IRQ_HANDLED;
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}
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static void
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__init mtk_timer_setup(struct mtk_clock_event_device *evt, u8 timer, u8 option)
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{
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writel(TIMER_CTRL_CLEAR | TIMER_CTRL_DISABLE,
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evt->gpt_base + TIMER_CTRL_REG(timer));
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writel(TIMER_CLK_SRC(TIMER_CLK_SRC_SYS13M) | TIMER_CLK_DIV1,
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evt->gpt_base + TIMER_CLK_REG(timer));
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writel(0x0, evt->gpt_base + TIMER_CMP_REG(timer));
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writel(TIMER_CTRL_OP(option) | TIMER_CTRL_ENABLE,
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evt->gpt_base + TIMER_CTRL_REG(timer));
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}
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static void mtk_timer_enable_irq(struct mtk_clock_event_device *evt, u8 timer)
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{
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u32 val;
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/* Disable all interrupts */
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writel(0x0, evt->gpt_base + GPT_IRQ_EN_REG);
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/* Acknowledge all spurious pending interrupts */
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writel(0x3f, evt->gpt_base + GPT_IRQ_ACK_REG);
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val = readl(evt->gpt_base + GPT_IRQ_EN_REG);
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writel(val | GPT_IRQ_ENABLE(timer),
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evt->gpt_base + GPT_IRQ_EN_REG);
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}
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static int __init mtk_timer_init(struct device_node *node)
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{
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struct mtk_clock_event_device *evt;
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struct resource res;
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unsigned long rate = 0;
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struct clk *clk;
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evt = kzalloc(sizeof(*evt), GFP_KERNEL);
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if (!evt)
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return -ENOMEM;
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evt->dev.name = "mtk_tick";
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evt->dev.rating = 300;
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evt->dev.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
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evt->dev.set_state_shutdown = mtk_clkevt_shutdown;
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evt->dev.set_state_periodic = mtk_clkevt_set_periodic;
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evt->dev.set_state_oneshot = mtk_clkevt_shutdown;
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evt->dev.tick_resume = mtk_clkevt_shutdown;
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evt->dev.set_next_event = mtk_clkevt_next_event;
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evt->dev.cpumask = cpu_possible_mask;
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evt->gpt_base = of_io_request_and_map(node, 0, "mtk-timer");
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if (IS_ERR(evt->gpt_base)) {
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pr_err("Can't get resource\n");
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goto err_kzalloc;
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}
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evt->dev.irq = irq_of_parse_and_map(node, 0);
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if (evt->dev.irq <= 0) {
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pr_err("Can't parse IRQ\n");
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goto err_mem;
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}
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clk = of_clk_get(node, 0);
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if (IS_ERR(clk)) {
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pr_err("Can't get timer clock\n");
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goto err_irq;
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}
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if (clk_prepare_enable(clk)) {
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pr_err("Can't prepare clock\n");
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goto err_clk_put;
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}
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rate = clk_get_rate(clk);
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if (request_irq(evt->dev.irq, mtk_timer_interrupt,
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IRQF_TIMER | IRQF_IRQPOLL, "mtk_timer", evt)) {
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pr_err("failed to setup irq %d\n", evt->dev.irq);
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goto err_clk_disable;
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}
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evt->ticks_per_jiffy = DIV_ROUND_UP(rate, HZ);
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/* Configure clock source */
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mtk_timer_setup(evt, GPT_CLK_SRC, TIMER_CTRL_OP_FREERUN);
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clocksource_mmio_init(evt->gpt_base + TIMER_CNT_REG(GPT_CLK_SRC),
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node->name, rate, 300, 32, clocksource_mmio_readl_up);
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gpt_sched_reg = evt->gpt_base + TIMER_CNT_REG(GPT_CLK_SRC);
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sched_clock_register(mtk_read_sched_clock, 32, rate);
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||||
/* Configure clock event */
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mtk_timer_setup(evt, GPT_CLK_EVT, TIMER_CTRL_OP_REPEAT);
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clockevents_config_and_register(&evt->dev, rate, 0x3,
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0xffffffff);
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mtk_timer_enable_irq(evt, GPT_CLK_EVT);
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||||
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||||
return 0;
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||||
|
||||
err_clk_disable:
|
||||
clk_disable_unprepare(clk);
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||||
err_clk_put:
|
||||
clk_put(clk);
|
||||
err_irq:
|
||||
irq_dispose_mapping(evt->dev.irq);
|
||||
err_mem:
|
||||
iounmap(evt->gpt_base);
|
||||
of_address_to_resource(node, 0, &res);
|
||||
release_mem_region(res.start, resource_size(&res));
|
||||
err_kzalloc:
|
||||
kfree(evt);
|
||||
|
||||
return -EINVAL;
|
||||
}
|
||||
TIMER_OF_DECLARE(mtk_mt6577, "mediatek,mt6577-timer", mtk_timer_init);
|
||||
|
|
@ -230,7 +230,7 @@ static int __init tegra20_init_timer(struct device_node *np)
|
|||
return ret;
|
||||
}
|
||||
|
||||
tegra_clockevent.cpumask = cpu_all_mask;
|
||||
tegra_clockevent.cpumask = cpu_possible_mask;
|
||||
tegra_clockevent.irq = tegra_timer_irq.irq;
|
||||
clockevents_config_and_register(&tegra_clockevent, 1000000,
|
||||
0x1, 0x1fffffff);
|
||||
|
|
|
|||
|
|
@ -185,7 +185,7 @@ static struct timer_of to = {
|
|||
.set_state_oneshot = atcpit100_clkevt_set_oneshot,
|
||||
.tick_resume = atcpit100_clkevt_shutdown,
|
||||
.set_next_event = atcpit100_clkevt_next_event,
|
||||
.cpumask = cpu_all_mask,
|
||||
.cpumask = cpu_possible_mask,
|
||||
},
|
||||
|
||||
.of_irq = {
|
||||
|
|
|
|||
|
|
@ -211,7 +211,7 @@ static int __init keystone_timer_init(struct device_node *np)
|
|||
event_dev->set_state_shutdown = keystone_shutdown;
|
||||
event_dev->set_state_periodic = keystone_set_periodic;
|
||||
event_dev->set_state_oneshot = keystone_shutdown;
|
||||
event_dev->cpumask = cpu_all_mask;
|
||||
event_dev->cpumask = cpu_possible_mask;
|
||||
event_dev->owner = THIS_MODULE;
|
||||
event_dev->name = TIMER_NAME;
|
||||
event_dev->irq = irq;
|
||||
|
|
|
|||
|
|
@ -0,0 +1,328 @@
|
|||
/*
|
||||
* Mediatek SoCs General-Purpose Timer handling.
|
||||
*
|
||||
* Copyright (C) 2014 Matthias Brugger
|
||||
*
|
||||
* Matthias Brugger <matthias.bgg@gmail.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
|
||||
|
||||
#include <linux/clockchips.h>
|
||||
#include <linux/clocksource.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/irqreturn.h>
|
||||
#include <linux/sched_clock.h>
|
||||
#include <linux/slab.h>
|
||||
#include "timer-of.h"
|
||||
|
||||
#define TIMER_CLK_EVT (1)
|
||||
#define TIMER_CLK_SRC (2)
|
||||
|
||||
#define TIMER_SYNC_TICKS (3)
|
||||
|
||||
/* gpt */
|
||||
#define GPT_IRQ_EN_REG 0x00
|
||||
#define GPT_IRQ_ENABLE(val) BIT((val) - 1)
|
||||
#define GPT_IRQ_ACK_REG 0x08
|
||||
#define GPT_IRQ_ACK(val) BIT((val) - 1)
|
||||
|
||||
#define GPT_CTRL_REG(val) (0x10 * (val))
|
||||
#define GPT_CTRL_OP(val) (((val) & 0x3) << 4)
|
||||
#define GPT_CTRL_OP_ONESHOT (0)
|
||||
#define GPT_CTRL_OP_REPEAT (1)
|
||||
#define GPT_CTRL_OP_FREERUN (3)
|
||||
#define GPT_CTRL_CLEAR (2)
|
||||
#define GPT_CTRL_ENABLE (1)
|
||||
#define GPT_CTRL_DISABLE (0)
|
||||
|
||||
#define GPT_CLK_REG(val) (0x04 + (0x10 * (val)))
|
||||
#define GPT_CLK_SRC(val) (((val) & 0x1) << 4)
|
||||
#define GPT_CLK_SRC_SYS13M (0)
|
||||
#define GPT_CLK_SRC_RTC32K (1)
|
||||
#define GPT_CLK_DIV1 (0x0)
|
||||
#define GPT_CLK_DIV2 (0x1)
|
||||
|
||||
#define GPT_CNT_REG(val) (0x08 + (0x10 * (val)))
|
||||
#define GPT_CMP_REG(val) (0x0C + (0x10 * (val)))
|
||||
|
||||
/* system timer */
|
||||
#define SYST_BASE (0x40)
|
||||
|
||||
#define SYST_CON (SYST_BASE + 0x0)
|
||||
#define SYST_VAL (SYST_BASE + 0x4)
|
||||
|
||||
#define SYST_CON_REG(to) (timer_of_base(to) + SYST_CON)
|
||||
#define SYST_VAL_REG(to) (timer_of_base(to) + SYST_VAL)
|
||||
|
||||
/*
|
||||
* SYST_CON_EN: Clock enable. Shall be set to
|
||||
* - Start timer countdown.
|
||||
* - Allow timeout ticks being updated.
|
||||
* - Allow changing interrupt functions.
|
||||
*
|
||||
* SYST_CON_IRQ_EN: Set to allow interrupt.
|
||||
*
|
||||
* SYST_CON_IRQ_CLR: Set to clear interrupt.
|
||||
*/
|
||||
#define SYST_CON_EN BIT(0)
|
||||
#define SYST_CON_IRQ_EN BIT(1)
|
||||
#define SYST_CON_IRQ_CLR BIT(4)
|
||||
|
||||
static void __iomem *gpt_sched_reg __read_mostly;
|
||||
|
||||
static void mtk_syst_ack_irq(struct timer_of *to)
|
||||
{
|
||||
/* Clear and disable interrupt */
|
||||
writel(SYST_CON_IRQ_CLR | SYST_CON_EN, SYST_CON_REG(to));
|
||||
}
|
||||
|
||||
static irqreturn_t mtk_syst_handler(int irq, void *dev_id)
|
||||
{
|
||||
struct clock_event_device *clkevt = dev_id;
|
||||
struct timer_of *to = to_timer_of(clkevt);
|
||||
|
||||
mtk_syst_ack_irq(to);
|
||||
clkevt->event_handler(clkevt);
|
||||
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
static int mtk_syst_clkevt_next_event(unsigned long ticks,
|
||||
struct clock_event_device *clkevt)
|
||||
{
|
||||
struct timer_of *to = to_timer_of(clkevt);
|
||||
|
||||
/* Enable clock to allow timeout tick update later */
|
||||
writel(SYST_CON_EN, SYST_CON_REG(to));
|
||||
|
||||
/*
|
||||
* Write new timeout ticks. Timer shall start countdown
|
||||
* after timeout ticks are updated.
|
||||
*/
|
||||
writel(ticks, SYST_VAL_REG(to));
|
||||
|
||||
/* Enable interrupt */
|
||||
writel(SYST_CON_EN | SYST_CON_IRQ_EN, SYST_CON_REG(to));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int mtk_syst_clkevt_shutdown(struct clock_event_device *clkevt)
|
||||
{
|
||||
/* Disable timer */
|
||||
writel(0, SYST_CON_REG(to_timer_of(clkevt)));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int mtk_syst_clkevt_resume(struct clock_event_device *clkevt)
|
||||
{
|
||||
return mtk_syst_clkevt_shutdown(clkevt);
|
||||
}
|
||||
|
||||
static int mtk_syst_clkevt_oneshot(struct clock_event_device *clkevt)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static u64 notrace mtk_gpt_read_sched_clock(void)
|
||||
{
|
||||
return readl_relaxed(gpt_sched_reg);
|
||||
}
|
||||
|
||||
static void mtk_gpt_clkevt_time_stop(struct timer_of *to, u8 timer)
|
||||
{
|
||||
u32 val;
|
||||
|
||||
val = readl(timer_of_base(to) + GPT_CTRL_REG(timer));
|
||||
writel(val & ~GPT_CTRL_ENABLE, timer_of_base(to) +
|
||||
GPT_CTRL_REG(timer));
|
||||
}
|
||||
|
||||
static void mtk_gpt_clkevt_time_setup(struct timer_of *to,
|
||||
unsigned long delay, u8 timer)
|
||||
{
|
||||
writel(delay, timer_of_base(to) + GPT_CMP_REG(timer));
|
||||
}
|
||||
|
||||
static void mtk_gpt_clkevt_time_start(struct timer_of *to,
|
||||
bool periodic, u8 timer)
|
||||
{
|
||||
u32 val;
|
||||
|
||||
/* Acknowledge interrupt */
|
||||
writel(GPT_IRQ_ACK(timer), timer_of_base(to) + GPT_IRQ_ACK_REG);
|
||||
|
||||
val = readl(timer_of_base(to) + GPT_CTRL_REG(timer));
|
||||
|
||||
/* Clear 2 bit timer operation mode field */
|
||||
val &= ~GPT_CTRL_OP(0x3);
|
||||
|
||||
if (periodic)
|
||||
val |= GPT_CTRL_OP(GPT_CTRL_OP_REPEAT);
|
||||
else
|
||||
val |= GPT_CTRL_OP(GPT_CTRL_OP_ONESHOT);
|
||||
|
||||
writel(val | GPT_CTRL_ENABLE | GPT_CTRL_CLEAR,
|
||||
timer_of_base(to) + GPT_CTRL_REG(timer));
|
||||
}
|
||||
|
||||
static int mtk_gpt_clkevt_shutdown(struct clock_event_device *clk)
|
||||
{
|
||||
mtk_gpt_clkevt_time_stop(to_timer_of(clk), TIMER_CLK_EVT);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int mtk_gpt_clkevt_set_periodic(struct clock_event_device *clk)
|
||||
{
|
||||
struct timer_of *to = to_timer_of(clk);
|
||||
|
||||
mtk_gpt_clkevt_time_stop(to, TIMER_CLK_EVT);
|
||||
mtk_gpt_clkevt_time_setup(to, to->of_clk.period, TIMER_CLK_EVT);
|
||||
mtk_gpt_clkevt_time_start(to, true, TIMER_CLK_EVT);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int mtk_gpt_clkevt_next_event(unsigned long event,
|
||||
struct clock_event_device *clk)
|
||||
{
|
||||
struct timer_of *to = to_timer_of(clk);
|
||||
|
||||
mtk_gpt_clkevt_time_stop(to, TIMER_CLK_EVT);
|
||||
mtk_gpt_clkevt_time_setup(to, event, TIMER_CLK_EVT);
|
||||
mtk_gpt_clkevt_time_start(to, false, TIMER_CLK_EVT);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static irqreturn_t mtk_gpt_interrupt(int irq, void *dev_id)
|
||||
{
|
||||
struct clock_event_device *clkevt = (struct clock_event_device *)dev_id;
|
||||
struct timer_of *to = to_timer_of(clkevt);
|
||||
|
||||
/* Acknowledge timer0 irq */
|
||||
writel(GPT_IRQ_ACK(TIMER_CLK_EVT), timer_of_base(to) + GPT_IRQ_ACK_REG);
|
||||
clkevt->event_handler(clkevt);
|
||||
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
static void
|
||||
__init mtk_gpt_setup(struct timer_of *to, u8 timer, u8 option)
|
||||
{
|
||||
writel(GPT_CTRL_CLEAR | GPT_CTRL_DISABLE,
|
||||
timer_of_base(to) + GPT_CTRL_REG(timer));
|
||||
|
||||
writel(GPT_CLK_SRC(GPT_CLK_SRC_SYS13M) | GPT_CLK_DIV1,
|
||||
timer_of_base(to) + GPT_CLK_REG(timer));
|
||||
|
||||
writel(0x0, timer_of_base(to) + GPT_CMP_REG(timer));
|
||||
|
||||
writel(GPT_CTRL_OP(option) | GPT_CTRL_ENABLE,
|
||||
timer_of_base(to) + GPT_CTRL_REG(timer));
|
||||
}
|
||||
|
||||
static void mtk_gpt_enable_irq(struct timer_of *to, u8 timer)
|
||||
{
|
||||
u32 val;
|
||||
|
||||
/* Disable all interrupts */
|
||||
writel(0x0, timer_of_base(to) + GPT_IRQ_EN_REG);
|
||||
|
||||
/* Acknowledge all spurious pending interrupts */
|
||||
writel(0x3f, timer_of_base(to) + GPT_IRQ_ACK_REG);
|
||||
|
||||
val = readl(timer_of_base(to) + GPT_IRQ_EN_REG);
|
||||
writel(val | GPT_IRQ_ENABLE(timer),
|
||||
timer_of_base(to) + GPT_IRQ_EN_REG);
|
||||
}
|
||||
|
||||
static struct timer_of to = {
|
||||
.flags = TIMER_OF_IRQ | TIMER_OF_BASE | TIMER_OF_CLOCK,
|
||||
|
||||
.clkevt = {
|
||||
.name = "mtk-clkevt",
|
||||
.rating = 300,
|
||||
.cpumask = cpu_possible_mask,
|
||||
},
|
||||
|
||||
.of_irq = {
|
||||
.flags = IRQF_TIMER | IRQF_IRQPOLL,
|
||||
},
|
||||
};
|
||||
|
||||
static int __init mtk_syst_init(struct device_node *node)
|
||||
{
|
||||
int ret;
|
||||
|
||||
to.clkevt.features = CLOCK_EVT_FEAT_DYNIRQ | CLOCK_EVT_FEAT_ONESHOT;
|
||||
to.clkevt.set_state_shutdown = mtk_syst_clkevt_shutdown;
|
||||
to.clkevt.set_state_oneshot = mtk_syst_clkevt_oneshot;
|
||||
to.clkevt.tick_resume = mtk_syst_clkevt_resume;
|
||||
to.clkevt.set_next_event = mtk_syst_clkevt_next_event;
|
||||
to.of_irq.handler = mtk_syst_handler;
|
||||
|
||||
ret = timer_of_init(node, &to);
|
||||
if (ret)
|
||||
goto err;
|
||||
|
||||
clockevents_config_and_register(&to.clkevt, timer_of_rate(&to),
|
||||
TIMER_SYNC_TICKS, 0xffffffff);
|
||||
|
||||
return 0;
|
||||
err:
|
||||
timer_of_cleanup(&to);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int __init mtk_gpt_init(struct device_node *node)
|
||||
{
|
||||
int ret;
|
||||
|
||||
to.clkevt.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
|
||||
to.clkevt.set_state_shutdown = mtk_gpt_clkevt_shutdown;
|
||||
to.clkevt.set_state_periodic = mtk_gpt_clkevt_set_periodic;
|
||||
to.clkevt.set_state_oneshot = mtk_gpt_clkevt_shutdown;
|
||||
to.clkevt.tick_resume = mtk_gpt_clkevt_shutdown;
|
||||
to.clkevt.set_next_event = mtk_gpt_clkevt_next_event;
|
||||
to.of_irq.handler = mtk_gpt_interrupt;
|
||||
|
||||
ret = timer_of_init(node, &to);
|
||||
if (ret)
|
||||
goto err;
|
||||
|
||||
/* Configure clock source */
|
||||
mtk_gpt_setup(&to, TIMER_CLK_SRC, GPT_CTRL_OP_FREERUN);
|
||||
clocksource_mmio_init(timer_of_base(&to) + GPT_CNT_REG(TIMER_CLK_SRC),
|
||||
node->name, timer_of_rate(&to), 300, 32,
|
||||
clocksource_mmio_readl_up);
|
||||
gpt_sched_reg = timer_of_base(&to) + GPT_CNT_REG(TIMER_CLK_SRC);
|
||||
sched_clock_register(mtk_gpt_read_sched_clock, 32, timer_of_rate(&to));
|
||||
|
||||
/* Configure clock event */
|
||||
mtk_gpt_setup(&to, TIMER_CLK_EVT, GPT_CTRL_OP_REPEAT);
|
||||
clockevents_config_and_register(&to.clkevt, timer_of_rate(&to),
|
||||
TIMER_SYNC_TICKS, 0xffffffff);
|
||||
|
||||
mtk_gpt_enable_irq(&to, TIMER_CLK_EVT);
|
||||
|
||||
return 0;
|
||||
err:
|
||||
timer_of_cleanup(&to);
|
||||
return ret;
|
||||
}
|
||||
TIMER_OF_DECLARE(mtk_mt6577, "mediatek,mt6577-timer", mtk_gpt_init);
|
||||
TIMER_OF_DECLARE(mtk_mt6765, "mediatek,mt6765-timer", mtk_syst_init);
|
||||
|
|
@ -156,4 +156,54 @@ static int __init sprd_timer_init(struct device_node *np)
|
|||
return 0;
|
||||
}
|
||||
|
||||
static struct timer_of suspend_to = {
|
||||
.flags = TIMER_OF_BASE | TIMER_OF_CLOCK,
|
||||
};
|
||||
|
||||
static u64 sprd_suspend_timer_read(struct clocksource *cs)
|
||||
{
|
||||
return ~(u64)readl_relaxed(timer_of_base(&suspend_to) +
|
||||
TIMER_VALUE_SHDW_LO) & cs->mask;
|
||||
}
|
||||
|
||||
static int sprd_suspend_timer_enable(struct clocksource *cs)
|
||||
{
|
||||
sprd_timer_update_counter(timer_of_base(&suspend_to),
|
||||
TIMER_VALUE_LO_MASK);
|
||||
sprd_timer_enable(timer_of_base(&suspend_to), TIMER_CTL_PERIOD_MODE);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void sprd_suspend_timer_disable(struct clocksource *cs)
|
||||
{
|
||||
sprd_timer_disable(timer_of_base(&suspend_to));
|
||||
}
|
||||
|
||||
static struct clocksource suspend_clocksource = {
|
||||
.name = "sprd_suspend_timer",
|
||||
.rating = 200,
|
||||
.read = sprd_suspend_timer_read,
|
||||
.enable = sprd_suspend_timer_enable,
|
||||
.disable = sprd_suspend_timer_disable,
|
||||
.mask = CLOCKSOURCE_MASK(32),
|
||||
.flags = CLOCK_SOURCE_IS_CONTINUOUS | CLOCK_SOURCE_SUSPEND_NONSTOP,
|
||||
};
|
||||
|
||||
static int __init sprd_suspend_timer_init(struct device_node *np)
|
||||
{
|
||||
int ret;
|
||||
|
||||
ret = timer_of_init(np, &suspend_to);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
clocksource_register_hz(&suspend_clocksource,
|
||||
timer_of_rate(&suspend_to));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
TIMER_OF_DECLARE(sc9860_timer, "sprd,sc9860-timer", sprd_timer_init);
|
||||
TIMER_OF_DECLARE(sc9860_persistent_timer, "sprd,sc9860-suspend-timer",
|
||||
sprd_suspend_timer_init);
|
||||
|
|
|
|||
|
|
@ -162,7 +162,7 @@ static int __init zevio_timer_add(struct device_node *node)
|
|||
timer->clkevt.set_state_oneshot = zevio_timer_set_oneshot;
|
||||
timer->clkevt.tick_resume = zevio_timer_set_oneshot;
|
||||
timer->clkevt.rating = 200;
|
||||
timer->clkevt.cpumask = cpu_all_mask;
|
||||
timer->clkevt.cpumask = cpu_possible_mask;
|
||||
timer->clkevt.features = CLOCK_EVT_FEAT_ONESHOT;
|
||||
timer->clkevt.irq = irqnr;
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue