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ARM: davinci: irqs: Correct McASP1 TX interrupt definition for DM646x

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McASP1 TX interrupt is 30, not 32 on DM646x DMSoC.

While at it remove the bogus AEMIF interrupt entry from
dm646x_default_priorities[]. AEMIF interrupt on DM6467 is
60 not 30 and the entry for the correct interrupt number
is already present in the same table.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
[nsekhar@ti.com: remove bogus entry from dm646x_default_priorities[]]
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
This commit is contained in:
Peter Ujfalusi 2015-03-12 10:06:30 +02:00 committed by Sekhar Nori
parent 256b20a54a
commit b38434145b
2 changed files with 1 additions and 2 deletions
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1
arch/arm/mach-davinci/dm646x.c
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@ -493,7 +493,6 @@ static u8 dm646x_default_priorities[DAVINCI_N_AINTC_IRQ] = {
[IRQ_DM646X_EMACMISCINT] = 7,
[IRQ_DM646X_MCASP0TXINT] = 7,
[IRQ_DM646X_MCASP0RXINT] = 7,
[IRQ_AEMIFINT] = 7,
[IRQ_DM646X_RESERVED_3] = 7,
[IRQ_DM646X_MCASP1TXINT] = 7, /* clockevent */
[IRQ_TINT0_TINT34] = 7, /* clocksource */

2
arch/arm/mach-davinci/include/mach/irqs.h
View file

@ -129,8 +129,8 @@
#define IRQ_DM646X_EMACMISCINT 27
#define IRQ_DM646X_MCASP0TXINT 28
#define IRQ_DM646X_MCASP0RXINT 29
#define IRQ_DM646X_MCASP1TXINT 30
#define IRQ_DM646X_RESERVED_3 31
#define IRQ_DM646X_MCASP1TXINT 32
#define IRQ_DM646X_VLQINT 38
#define IRQ_DM646X_UARTINT2 42
#define IRQ_DM646X_SPINT0 43