ARM: davinci: irqs: Correct McASP1 TX interrupt definition for DM646x
McASP1 TX interrupt is 30, not 32 on DM646x DMSoC. While at it remove the bogus AEMIF interrupt entry from dm646x_default_priorities[]. AEMIF interrupt on DM6467 is 60 not 30 and the entry for the correct interrupt number is already present in the same table. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> [nsekhar@ti.com: remove bogus entry from dm646x_default_priorities[]] Signed-off-by: Sekhar Nori <nsekhar@ti.com>
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@ -493,7 +493,6 @@ static u8 dm646x_default_priorities[DAVINCI_N_AINTC_IRQ] = {
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[IRQ_DM646X_EMACMISCINT] = 7,
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[IRQ_DM646X_MCASP0TXINT] = 7,
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[IRQ_DM646X_MCASP0RXINT] = 7,
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[IRQ_AEMIFINT] = 7,
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[IRQ_DM646X_RESERVED_3] = 7,
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[IRQ_DM646X_MCASP1TXINT] = 7, /* clockevent */
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[IRQ_TINT0_TINT34] = 7, /* clocksource */
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@ -129,8 +129,8 @@
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#define IRQ_DM646X_EMACMISCINT 27
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#define IRQ_DM646X_MCASP0TXINT 28
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#define IRQ_DM646X_MCASP0RXINT 29
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#define IRQ_DM646X_MCASP1TXINT 30
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#define IRQ_DM646X_RESERVED_3 31
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#define IRQ_DM646X_MCASP1TXINT 32
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#define IRQ_DM646X_VLQINT 38
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#define IRQ_DM646X_UARTINT2 42
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#define IRQ_DM646X_SPINT0 43
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