MN10300: Allow some cacheflushes to be avoided if cache snooping is available
The AM34 core is able to do cache snooping, and so can skip some of the cache flushing. Signed-off-by: David Howells <dhowells@redhat.com>
This commit is contained in:
parent
9731d23710
commit
b478491f26
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@ -18,6 +18,7 @@ config AM33_3
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config AM34_2
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def_bool n
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select MN10300_HAS_ATOMIC_OPS_UNIT
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select MN10300_HAS_CACHE_SNOOP
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config MMU
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def_bool y
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@ -131,18 +131,22 @@ extern void mn10300_dcache_flush_inv_range2(unsigned long start, unsigned long s
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/*
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* Physically-indexed cache management
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*/
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#ifdef CONFIG_MN10300_CACHE_ENABLED
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#if defined(CONFIG_MN10300_CACHE_FLUSH_ICACHE)
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extern void flush_icache_page(struct vm_area_struct *vma, struct page *page);
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extern void flush_icache_range(unsigned long start, unsigned long end);
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#elif defined(CONFIG_MN10300_CACHE_INV_ICACHE)
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static inline void flush_icache_page(struct vm_area_struct *vma,
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struct page *page)
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{
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mn10300_icache_inv_page(page_to_phys(page));
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}
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extern void flush_icache_range(unsigned long start, unsigned long end);
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extern void flush_icache_page(struct vm_area_struct *vma, struct page *pg);
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#else
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#define flush_icache_range(start, end) do {} while (0)
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#define flush_icache_page(vma, pg) do {} while (0)
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#endif
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#define flush_icache_user_range(vma, pg, adr, len) \
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flush_icache_range(adr, adr + len)
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@ -377,8 +377,10 @@ void __kprobes arch_arm_kprobe(struct kprobe *p)
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void __kprobes arch_disarm_kprobe(struct kprobe *p)
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{
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#ifndef CONFIG_MN10300_CACHE_SNOOP
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mn10300_dcache_flush();
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mn10300_icache_inv();
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#endif
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}
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void arch_remove_kprobe(struct kprobe *p)
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@ -390,8 +392,10 @@ void __kprobes disarm_kprobe(struct kprobe *p, struct pt_regs *regs)
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{
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*p->addr = p->opcode;
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regs->pc = (unsigned long) p->addr;
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#ifndef CONFIG_MN10300_CACHE_SNOOP
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mn10300_dcache_flush();
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mn10300_icache_inv();
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#endif
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}
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static inline
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@ -533,8 +533,10 @@ void __init set_intr_stub(enum exception_code code, void *handler)
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vector[6] = 0xcb;
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vector[7] = 0xcb;
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#ifndef CONFIG_MN10300_CACHE_SNOOP
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mn10300_dcache_flush_inv();
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mn10300_icache_inv();
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#endif
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}
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/*
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@ -22,12 +22,26 @@ choice
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config MN10300_CACHE_WBACK
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bool "Write-Back"
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help
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The dcache operates in delayed write-back mode. It must be manually
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flushed if writes are made that subsequently need to be executed or
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to be DMA'd by a device.
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config MN10300_CACHE_WTHRU
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bool "Write-Through"
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help
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The dcache operates in immediate write-through mode. Writes are
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committed to RAM immediately in addition to being stored in the
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cache. This means that the written data is immediately available for
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execution or DMA.
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This is not available for use with an SMP kernel if cache flushing
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and invalidation by automatic purge register is not selected.
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config MN10300_CACHE_DISABLED
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bool "Disabled"
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help
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The icache and dcache are disabled.
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endchoice
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@ -64,3 +78,23 @@ config MN10300_CACHE_FLUSH_BY_TAG
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config MN10300_CACHE_FLUSH_BY_REG
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def_bool y if MN10300_CACHE_MANAGE_BY_REG && MN10300_CACHE_WBACK
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config MN10300_HAS_CACHE_SNOOP
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def_bool n
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config MN10300_CACHE_SNOOP
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bool "Use CPU Cache Snooping"
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depends on MN10300_CACHE_ENABLED && MN10300_HAS_CACHE_SNOOP
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default y
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config MN10300_CACHE_FLUSH_ICACHE
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def_bool y if MN10300_CACHE_WBACK && !MN10300_CACHE_SNOOP
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help
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Set if we need the dcache flushing before the icache is invalidated.
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config MN10300_CACHE_INV_ICACHE
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def_bool y if MN10300_CACHE_WTHRU && !MN10300_CACHE_SNOOP
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help
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Set if we need the icache to be invalidated, even if the dcache is in
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write-through mode and doesn't need flushing.
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@ -3,6 +3,8 @@
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#
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cacheflush-y := cache.o
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cacheflush-$(CONFIG_MN10300_CACHE_INV_ICACHE) += cache-inv-icache.o
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cacheflush-$(CONFIG_MN10300_CACHE_FLUSH_ICACHE) += cache-flush-icache.o
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cacheflush-$(CONFIG_MN10300_CACHE_INV_BY_TAG) += cache-inv-by-tag.o
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cacheflush-$(CONFIG_MN10300_CACHE_INV_BY_REG) += cache-inv-by-reg.o
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cacheflush-$(CONFIG_MN10300_CACHE_FLUSH_BY_TAG) += cache-flush-by-tag.o
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137
arch/mn10300/mm/cache-flush-icache.c
Normal file
137
arch/mn10300/mm/cache-flush-icache.c
Normal file
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@ -0,0 +1,137 @@
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/* Flush dcache and invalidate icache when the dcache is in writeback mode
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*
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* Copyright (C) 2010 Red Hat, Inc. All Rights Reserved.
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* Written by David Howells (dhowells@redhat.com)
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public Licence
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* as published by the Free Software Foundation; either version
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* 2 of the Licence, or (at your option) any later version.
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*/
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#include <linux/module.h>
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#include <linux/mm.h>
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#include <asm/cacheflush.h>
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/**
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* flush_icache_page - Flush a page from the dcache and invalidate the icache
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* @vma: The VMA the page is part of.
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* @page: The page to be flushed.
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*
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* Write a page back from the dcache and invalidate the icache so that we can
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* run code from it that we've just written into it
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*/
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void flush_icache_page(struct vm_area_struct *vma, struct page *page)
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{
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unsigned long start = page_to_phys(page);
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mn10300_dcache_flush_page(start);
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mn10300_icache_inv_page(start);
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}
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EXPORT_SYMBOL(flush_icache_page);
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/**
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* flush_icache_page_range - Flush dcache and invalidate icache for part of a
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* single page
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* @start: The starting virtual address of the page part.
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* @end: The ending virtual address of the page part.
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*
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* Flush the dcache and invalidate the icache for part of a single page, as
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* determined by the virtual addresses given. The page must be in the paged
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* area.
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*/
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static void flush_icache_page_range(unsigned long start, unsigned long end)
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{
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unsigned long addr, size, off;
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struct page *page;
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pgd_t *pgd;
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pud_t *pud;
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pmd_t *pmd;
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pte_t *ppte, pte;
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/* work out how much of the page to flush */
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off = start & ~PAGE_MASK;
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size = end - start;
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/* get the physical address the page is mapped to from the page
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* tables */
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pgd = pgd_offset(current->mm, start);
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if (!pgd || !pgd_val(*pgd))
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return;
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pud = pud_offset(pgd, start);
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if (!pud || !pud_val(*pud))
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return;
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pmd = pmd_offset(pud, start);
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if (!pmd || !pmd_val(*pmd))
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return;
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ppte = pte_offset_map(pmd, start);
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if (!ppte)
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return;
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pte = *ppte;
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pte_unmap(ppte);
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if (pte_none(pte))
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return;
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page = pte_page(pte);
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if (!page)
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return;
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addr = page_to_phys(page);
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/* flush the dcache and invalidate the icache coverage on that
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* region */
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mn10300_dcache_flush_range2(addr + off, size);
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mn10300_icache_inv_range2(addr + off, size);
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}
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/**
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* flush_icache_range - Globally flush dcache and invalidate icache for region
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* @start: The starting virtual address of the region.
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* @end: The ending virtual address of the region.
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*
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* This is used by the kernel to globally flush some code it has just written
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* from the dcache back to RAM and then to globally invalidate the icache over
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* that region so that that code can be run on all CPUs in the system.
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*/
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void flush_icache_range(unsigned long start, unsigned long end)
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{
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unsigned long start_page, end_page;
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if (end > 0x80000000UL) {
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/* addresses above 0xa0000000 do not go through the cache */
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if (end > 0xa0000000UL) {
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end = 0xa0000000UL;
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if (start >= end)
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return;
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}
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/* kernel addresses between 0x80000000 and 0x9fffffff do not
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* require page tables, so we just map such addresses
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* directly */
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start_page = (start >= 0x80000000UL) ? start : 0x80000000UL;
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mn10300_dcache_flush_range(start_page, end);
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mn10300_icache_inv_range(start_page, end);
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if (start_page == start)
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return;
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end = start_page;
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}
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start_page = start & PAGE_MASK;
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end_page = end & PAGE_MASK;
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if (start_page == end_page) {
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/* the first and last bytes are on the same page */
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flush_icache_page_range(start, end);
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} else if (start_page + 1 == end_page) {
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/* split over two virtually contiguous pages */
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flush_icache_page_range(start, end_page);
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flush_icache_page_range(end_page, end);
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} else {
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/* more than 2 pages; just flush the entire cache */
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mn10300_dcache_flush();
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mn10300_icache_inv();
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}
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}
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EXPORT_SYMBOL(flush_icache_range);
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119
arch/mn10300/mm/cache-inv-icache.c
Normal file
119
arch/mn10300/mm/cache-inv-icache.c
Normal file
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/* Invalidate icache when dcache doesn't need invalidation as it's in
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* write-through mode
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*
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* Copyright (C) 2010 Red Hat, Inc. All Rights Reserved.
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* Written by David Howells (dhowells@redhat.com)
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public Licence
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* as published by the Free Software Foundation; either version
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* 2 of the Licence, or (at your option) any later version.
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*/
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#include <linux/module.h>
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#include <linux/mm.h>
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#include <asm/cacheflush.h>
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/**
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* flush_icache_page_range - Flush dcache and invalidate icache for part of a
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* single page
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* @start: The starting virtual address of the page part.
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* @end: The ending virtual address of the page part.
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*
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* Invalidate the icache for part of a single page, as determined by the
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* virtual addresses given. The page must be in the paged area. The dcache is
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* not flushed as the cache must be in write-through mode to get here.
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*/
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static void flush_icache_page_range(unsigned long start, unsigned long end)
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{
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unsigned long addr, size, off;
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struct page *page;
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pgd_t *pgd;
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pud_t *pud;
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pmd_t *pmd;
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pte_t *ppte, pte;
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/* work out how much of the page to flush */
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off = start & ~PAGE_MASK;
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size = end - start;
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/* get the physical address the page is mapped to from the page
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* tables */
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pgd = pgd_offset(current->mm, start);
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if (!pgd || !pgd_val(*pgd))
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return;
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pud = pud_offset(pgd, start);
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if (!pud || !pud_val(*pud))
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return;
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pmd = pmd_offset(pud, start);
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if (!pmd || !pmd_val(*pmd))
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return;
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ppte = pte_offset_map(pmd, start);
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if (!ppte)
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return;
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pte = *ppte;
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pte_unmap(ppte);
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if (pte_none(pte))
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return;
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page = pte_page(pte);
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if (!page)
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return;
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addr = page_to_phys(page);
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/* invalidate the icache coverage on that region */
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mn10300_icache_inv_range2(addr + off, size);
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}
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/**
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* flush_icache_range - Globally flush dcache and invalidate icache for region
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* @start: The starting virtual address of the region.
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* @end: The ending virtual address of the region.
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*
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* This is used by the kernel to globally flush some code it has just written
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* from the dcache back to RAM and then to globally invalidate the icache over
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* that region so that that code can be run on all CPUs in the system.
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*/
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void flush_icache_range(unsigned long start, unsigned long end)
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{
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unsigned long start_page, end_page;
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if (end > 0x80000000UL) {
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/* addresses above 0xa0000000 do not go through the cache */
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if (end > 0xa0000000UL) {
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end = 0xa0000000UL;
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if (start >= end)
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return;
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}
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/* kernel addresses between 0x80000000 and 0x9fffffff do not
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* require page tables, so we just map such addresses
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* directly */
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start_page = (start >= 0x80000000UL) ? start : 0x80000000UL;
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mn10300_dcache_flush_range(start_page, end);
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mn10300_icache_inv_range(start_page, end);
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if (start_page == start)
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return;
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end = start_page;
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}
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start_page = start & PAGE_MASK;
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end_page = end & PAGE_MASK;
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if (start_page == end_page) {
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/* the first and last bytes are on the same page */
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flush_icache_page_range(start, end);
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} else if (start_page + 1 == end_page) {
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/* split over two virtually contiguous pages */
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flush_icache_page_range(start, end_page);
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flush_icache_page_range(end_page, end);
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} else {
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/* more than 2 pages; just flush the entire cache */
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mn10300_icache_inv();
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}
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}
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EXPORT_SYMBOL(flush_icache_range);
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@ -36,96 +36,6 @@ EXPORT_SYMBOL(mn10300_dcache_flush_range2);
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EXPORT_SYMBOL(mn10300_dcache_flush_page);
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#endif
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/*
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* write a page back from the dcache and invalidate the icache so that we can
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* run code from it that we've just written into it
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*/
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void flush_icache_page(struct vm_area_struct *vma, struct page *page)
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{
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mn10300_dcache_flush_page(page_to_phys(page));
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mn10300_icache_inv();
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}
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EXPORT_SYMBOL(flush_icache_page);
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/*
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* write some code we've just written back from the dcache and invalidate the
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* icache so that we can run that code
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*/
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void flush_icache_range(unsigned long start, unsigned long end)
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{
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#ifdef CONFIG_MN10300_CACHE_WBACK
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unsigned long addr, size, base, off;
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struct page *page;
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pgd_t *pgd;
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pud_t *pud;
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pmd_t *pmd;
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pte_t *ppte, pte;
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if (end > 0x80000000UL) {
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/* addresses above 0xa0000000 do not go through the cache */
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if (end > 0xa0000000UL) {
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end = 0xa0000000UL;
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if (start >= end)
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return;
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}
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/* kernel addresses between 0x80000000 and 0x9fffffff do not
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* require page tables, so we just map such addresses directly */
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base = (start >= 0x80000000UL) ? start : 0x80000000UL;
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mn10300_dcache_flush_range(base, end);
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if (base == start)
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goto invalidate;
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end = base;
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}
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for (; start < end; start += size) {
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/* work out how much of the page to flush */
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off = start & (PAGE_SIZE - 1);
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size = end - start;
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if (size > PAGE_SIZE - off)
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size = PAGE_SIZE - off;
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/* get the physical address the page is mapped to from the page
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* tables */
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pgd = pgd_offset(current->mm, start);
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if (!pgd || !pgd_val(*pgd))
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continue;
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pud = pud_offset(pgd, start);
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if (!pud || !pud_val(*pud))
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continue;
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pmd = pmd_offset(pud, start);
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if (!pmd || !pmd_val(*pmd))
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continue;
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ppte = pte_offset_map(pmd, start);
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if (!ppte)
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continue;
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pte = *ppte;
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pte_unmap(ppte);
|
||||
|
||||
if (pte_none(pte))
|
||||
continue;
|
||||
|
||||
page = pte_page(pte);
|
||||
if (!page)
|
||||
continue;
|
||||
|
||||
addr = page_to_phys(page);
|
||||
|
||||
/* flush the dcache and invalidate the icache coverage on that
|
||||
* region */
|
||||
mn10300_dcache_flush_range2(addr + off, size);
|
||||
}
|
||||
#endif
|
||||
|
||||
invalidate:
|
||||
mn10300_icache_inv();
|
||||
}
|
||||
EXPORT_SYMBOL(flush_icache_range);
|
||||
|
||||
/*
|
||||
* allow userspace to flush the instruction cache
|
||||
*/
|
||||
|
|
Loading…
Reference in a new issue