Merge branch 'imx-features-for-arnd' of git://git.pengutronix.de/git/imx/linux-2.6 into imx/devel
Conflicts: arch/arm/mach-mx5/clock-mx51-mx53.c arch/arm/mach-mx5/devices-imx53.h
This commit is contained in:
commit
b4cbb8a4e6
13
Documentation/ABI/testing/sysfs-class-scsi_host
Normal file
13
Documentation/ABI/testing/sysfs-class-scsi_host
Normal file
|
@ -0,0 +1,13 @@
|
|||
What: /sys/class/scsi_host/hostX/isci_id
|
||||
Date: June 2011
|
||||
Contact: Dave Jiang <dave.jiang@intel.com>
|
||||
Description:
|
||||
This file contains the enumerated host ID for the Intel
|
||||
SCU controller. The Intel(R) C600 Series Chipset SATA/SAS
|
||||
Storage Control Unit embeds up to two 4-port controllers in
|
||||
a single PCI device. The controllers are enumerated in order
|
||||
which usually means the lowest number scsi_host corresponds
|
||||
with the first controller, but this association is not
|
||||
guaranteed. The 'isci_id' attribute unambiguously identifies
|
||||
the controller index: '0' for the first controller,
|
||||
'1' for the second.
|
|
@ -1455,7 +1455,7 @@ Applicable to the H264 encoder.</entry>
|
|||
</row>
|
||||
|
||||
<row><entry></entry></row>
|
||||
<row>
|
||||
<row id="v4l2-mpeg-video-h264-vui-sar-idc">
|
||||
<entry spanname="id"><constant>V4L2_CID_MPEG_VIDEO_H264_VUI_SAR_IDC</constant> </entry>
|
||||
<entry>enum v4l2_mpeg_video_h264_vui_sar_idc</entry>
|
||||
</row>
|
||||
|
@ -1561,7 +1561,7 @@ Applicable to the H264 encoder.</entry>
|
|||
</row>
|
||||
|
||||
<row><entry></entry></row>
|
||||
<row>
|
||||
<row id="v4l2-mpeg-video-h264-level">
|
||||
<entry spanname="id"><constant>V4L2_CID_MPEG_VIDEO_H264_LEVEL</constant> </entry>
|
||||
<entry>enum v4l2_mpeg_video_h264_level</entry>
|
||||
</row>
|
||||
|
@ -1641,7 +1641,7 @@ Possible values are:</entry>
|
|||
</row>
|
||||
|
||||
<row><entry></entry></row>
|
||||
<row>
|
||||
<row id="v4l2-mpeg-video-mpeg4-level">
|
||||
<entry spanname="id"><constant>V4L2_CID_MPEG_VIDEO_MPEG4_LEVEL</constant> </entry>
|
||||
<entry>enum v4l2_mpeg_video_mpeg4_level</entry>
|
||||
</row>
|
||||
|
@ -1689,9 +1689,9 @@ Possible values are:</entry>
|
|||
</row>
|
||||
|
||||
<row><entry></entry></row>
|
||||
<row>
|
||||
<row id="v4l2-mpeg-video-h264-profile">
|
||||
<entry spanname="id"><constant>V4L2_CID_MPEG_VIDEO_H264_PROFILE</constant> </entry>
|
||||
<entry>enum v4l2_mpeg_h264_profile</entry>
|
||||
<entry>enum v4l2_mpeg_video_h264_profile</entry>
|
||||
</row>
|
||||
<row><entry spanname="descr">The profile information for H264.
|
||||
Applicable to the H264 encoder.
|
||||
|
@ -1774,9 +1774,9 @@ Possible values are:</entry>
|
|||
</row>
|
||||
|
||||
<row><entry></entry></row>
|
||||
<row>
|
||||
<row id="v4l2-mpeg-video-mpeg4-profile">
|
||||
<entry spanname="id"><constant>V4L2_CID_MPEG_VIDEO_MPEG4_PROFILE</constant> </entry>
|
||||
<entry>enum v4l2_mpeg_mpeg4_profile</entry>
|
||||
<entry>enum v4l2_mpeg_video_mpeg4_profile</entry>
|
||||
</row>
|
||||
<row><entry spanname="descr">The profile information for MPEG4.
|
||||
Applicable to the MPEG4 encoder.
|
||||
|
@ -1820,9 +1820,9 @@ Applicable to the encoder.
|
|||
</row>
|
||||
|
||||
<row><entry></entry></row>
|
||||
<row>
|
||||
<row id="v4l2-mpeg-video-multi-slice-mode">
|
||||
<entry spanname="id"><constant>V4L2_CID_MPEG_VIDEO_MULTI_SLICE_MODE</constant> </entry>
|
||||
<entry>enum v4l2_mpeg_multi_slice_mode</entry>
|
||||
<entry>enum v4l2_mpeg_video_multi_slice_mode</entry>
|
||||
</row>
|
||||
<row><entry spanname="descr">Determines how the encoder should handle division of frame into slices.
|
||||
Applicable to the encoder.
|
||||
|
@ -1868,9 +1868,9 @@ Applicable to the encoder.</entry>
|
|||
</row>
|
||||
|
||||
<row><entry></entry></row>
|
||||
<row>
|
||||
<row id="v4l2-mpeg-video-h264-loop-filter-mode">
|
||||
<entry spanname="id"><constant>V4L2_CID_MPEG_VIDEO_H264_LOOP_FILTER_MODE</constant> </entry>
|
||||
<entry>enum v4l2_mpeg_h264_loop_filter_mode</entry>
|
||||
<entry>enum v4l2_mpeg_video_h264_loop_filter_mode</entry>
|
||||
</row>
|
||||
<row><entry spanname="descr">Loop filter mode for H264 encoder.
|
||||
Possible values are:</entry>
|
||||
|
@ -1913,9 +1913,9 @@ Applicable to the H264 encoder.</entry>
|
|||
</row>
|
||||
|
||||
<row><entry></entry></row>
|
||||
<row>
|
||||
<row id="v4l2-mpeg-video-h264-entropy-mode">
|
||||
<entry spanname="id"><constant>V4L2_CID_MPEG_VIDEO_H264_ENTROPY_MODE</constant> </entry>
|
||||
<entry>enum v4l2_mpeg_h264_symbol_mode</entry>
|
||||
<entry>enum v4l2_mpeg_video_h264_entropy_mode</entry>
|
||||
</row>
|
||||
<row><entry spanname="descr">Entropy coding mode for H264 - CABAC/CAVALC.
|
||||
Applicable to the H264 encoder.
|
||||
|
@ -2140,9 +2140,9 @@ previous frames. Applicable to the H264 encoder.</entry>
|
|||
</row>
|
||||
|
||||
<row><entry></entry></row>
|
||||
<row>
|
||||
<row id="v4l2-mpeg-video-header-mode">
|
||||
<entry spanname="id"><constant>V4L2_CID_MPEG_VIDEO_HEADER_MODE</constant> </entry>
|
||||
<entry>enum v4l2_mpeg_header_mode</entry>
|
||||
<entry>enum v4l2_mpeg_video_header_mode</entry>
|
||||
</row>
|
||||
<row><entry spanname="descr">Determines whether the header is returned as the first buffer or is
|
||||
it returned together with the first frame. Applicable to encoders.
|
||||
|
@ -2320,9 +2320,9 @@ Valid only when H.264 and macroblock level RC is enabled (<constant>V4L2_CID_MPE
|
|||
Applicable to the H264 encoder.</entry>
|
||||
</row>
|
||||
<row><entry></entry></row>
|
||||
<row>
|
||||
<row id="v4l2-mpeg-mfc51-video-frame-skip-mode">
|
||||
<entry spanname="id"><constant>V4L2_CID_MPEG_MFC51_VIDEO_FRAME_SKIP_MODE</constant> </entry>
|
||||
<entry>enum v4l2_mpeg_mfc51_frame_skip_mode</entry>
|
||||
<entry>enum v4l2_mpeg_mfc51_video_frame_skip_mode</entry>
|
||||
</row>
|
||||
<row><entry spanname="descr">
|
||||
Indicates in what conditions the encoder should skip frames. If encoding a frame would cause the encoded stream to be larger then
|
||||
|
@ -2361,9 +2361,9 @@ the stream will meet tight bandwidth contraints. Applicable to encoders.
|
|||
</entry>
|
||||
</row>
|
||||
<row><entry></entry></row>
|
||||
<row>
|
||||
<row id="v4l2-mpeg-mfc51-video-force-frame-type">
|
||||
<entry spanname="id"><constant>V4L2_CID_MPEG_MFC51_VIDEO_FORCE_FRAME_TYPE</constant> </entry>
|
||||
<entry>enum v4l2_mpeg_mfc51_force_frame_type</entry>
|
||||
<entry>enum v4l2_mpeg_mfc51_video_force_frame_type</entry>
|
||||
</row>
|
||||
<row><entry spanname="descr">Force a frame type for the next queued buffer. Applicable to encoders.
|
||||
Possible values are:</entry>
|
||||
|
|
|
@ -380,7 +380,7 @@ will be charged as a new owner of it.
|
|||
|
||||
5.2 stat file
|
||||
|
||||
5.2.1 memory.stat file includes following statistics
|
||||
memory.stat file includes following statistics
|
||||
|
||||
# per-memory cgroup local status
|
||||
cache - # of bytes of page cache memory.
|
||||
|
@ -438,89 +438,6 @@ Note:
|
|||
file_mapped is accounted only when the memory cgroup is owner of page
|
||||
cache.)
|
||||
|
||||
5.2.2 memory.vmscan_stat
|
||||
|
||||
memory.vmscan_stat includes statistics information for memory scanning and
|
||||
freeing, reclaiming. The statistics shows memory scanning information since
|
||||
memory cgroup creation and can be reset to 0 by writing 0 as
|
||||
|
||||
#echo 0 > ../memory.vmscan_stat
|
||||
|
||||
This file contains following statistics.
|
||||
|
||||
[param]_[file_or_anon]_pages_by_[reason]_[under_heararchy]
|
||||
[param]_elapsed_ns_by_[reason]_[under_hierarchy]
|
||||
|
||||
For example,
|
||||
|
||||
scanned_file_pages_by_limit indicates the number of scanned
|
||||
file pages at vmscan.
|
||||
|
||||
Now, 3 parameters are supported
|
||||
|
||||
scanned - the number of pages scanned by vmscan
|
||||
rotated - the number of pages activated at vmscan
|
||||
freed - the number of pages freed by vmscan
|
||||
|
||||
If "rotated" is high against scanned/freed, the memcg seems busy.
|
||||
|
||||
Now, 2 reason are supported
|
||||
|
||||
limit - the memory cgroup's limit
|
||||
system - global memory pressure + softlimit
|
||||
(global memory pressure not under softlimit is not handled now)
|
||||
|
||||
When under_hierarchy is added in the tail, the number indicates the
|
||||
total memcg scan of its children and itself.
|
||||
|
||||
elapsed_ns is a elapsed time in nanosecond. This may include sleep time
|
||||
and not indicates CPU usage. So, please take this as just showing
|
||||
latency.
|
||||
|
||||
Here is an example.
|
||||
|
||||
# cat /cgroup/memory/A/memory.vmscan_stat
|
||||
scanned_pages_by_limit 9471864
|
||||
scanned_anon_pages_by_limit 6640629
|
||||
scanned_file_pages_by_limit 2831235
|
||||
rotated_pages_by_limit 4243974
|
||||
rotated_anon_pages_by_limit 3971968
|
||||
rotated_file_pages_by_limit 272006
|
||||
freed_pages_by_limit 2318492
|
||||
freed_anon_pages_by_limit 962052
|
||||
freed_file_pages_by_limit 1356440
|
||||
elapsed_ns_by_limit 351386416101
|
||||
scanned_pages_by_system 0
|
||||
scanned_anon_pages_by_system 0
|
||||
scanned_file_pages_by_system 0
|
||||
rotated_pages_by_system 0
|
||||
rotated_anon_pages_by_system 0
|
||||
rotated_file_pages_by_system 0
|
||||
freed_pages_by_system 0
|
||||
freed_anon_pages_by_system 0
|
||||
freed_file_pages_by_system 0
|
||||
elapsed_ns_by_system 0
|
||||
scanned_pages_by_limit_under_hierarchy 9471864
|
||||
scanned_anon_pages_by_limit_under_hierarchy 6640629
|
||||
scanned_file_pages_by_limit_under_hierarchy 2831235
|
||||
rotated_pages_by_limit_under_hierarchy 4243974
|
||||
rotated_anon_pages_by_limit_under_hierarchy 3971968
|
||||
rotated_file_pages_by_limit_under_hierarchy 272006
|
||||
freed_pages_by_limit_under_hierarchy 2318492
|
||||
freed_anon_pages_by_limit_under_hierarchy 962052
|
||||
freed_file_pages_by_limit_under_hierarchy 1356440
|
||||
elapsed_ns_by_limit_under_hierarchy 351386416101
|
||||
scanned_pages_by_system_under_hierarchy 0
|
||||
scanned_anon_pages_by_system_under_hierarchy 0
|
||||
scanned_file_pages_by_system_under_hierarchy 0
|
||||
rotated_pages_by_system_under_hierarchy 0
|
||||
rotated_anon_pages_by_system_under_hierarchy 0
|
||||
rotated_file_pages_by_system_under_hierarchy 0
|
||||
freed_pages_by_system_under_hierarchy 0
|
||||
freed_anon_pages_by_system_under_hierarchy 0
|
||||
freed_file_pages_by_system_under_hierarchy 0
|
||||
elapsed_ns_by_system_under_hierarchy 0
|
||||
|
||||
5.3 swappiness
|
||||
|
||||
Similar to /proc/sys/vm/swappiness, but affecting a hierarchy of groups only.
|
||||
|
|
|
@ -592,3 +592,11 @@ Why: In 3.0, we can now autodetect internal 3G device and already have
|
|||
interface that was used by acer-wmi driver. It will replaced by
|
||||
information log when acer-wmi initial.
|
||||
Who: Lee, Chun-Yi <jlee@novell.com>
|
||||
|
||||
----------------------------
|
||||
What: The XFS nodelaylog mount option
|
||||
When: 3.3
|
||||
Why: The delaylog mode that has been the default since 2.6.39 has proven
|
||||
stable, and the old code is in the way of additional improvements in
|
||||
the log code.
|
||||
Who: Christoph Hellwig <hch@lst.de>
|
||||
|
|
|
@ -35,13 +35,6 @@ the Out-Of-Spec bit. Following table summarizes the exported sysfs files:
|
|||
All Sysfs entries are named with their core_id (represented here by 'X').
|
||||
tempX_input - Core temperature (in millidegrees Celsius).
|
||||
tempX_max - All cooling devices should be turned on (on Core2).
|
||||
Initialized with IA32_THERM_INTERRUPT. When the CPU
|
||||
temperature reaches this temperature, an interrupt is
|
||||
generated and tempX_max_alarm is set.
|
||||
tempX_max_hyst - If the CPU temperature falls below than temperature,
|
||||
an interrupt is generated and tempX_max_alarm is reset.
|
||||
tempX_max_alarm - Set if the temperature reaches or exceeds tempX_max.
|
||||
Reset if the temperature drops to or below tempX_max_hyst.
|
||||
tempX_crit - Maximum junction temperature (in millidegrees Celsius).
|
||||
tempX_crit_alarm - Set when Out-of-spec bit is set, never clears.
|
||||
Correct CPU operation is no longer guaranteed.
|
||||
|
@ -49,9 +42,10 @@ tempX_label - Contains string "Core X", where X is processor
|
|||
number. For Package temp, this will be "Physical id Y",
|
||||
where Y is the package number.
|
||||
|
||||
The TjMax temperature is set to 85 degrees C if undocumented model specific
|
||||
register (UMSR) 0xee has bit 30 set. If not the TjMax is 100 degrees C as
|
||||
(sometimes) documented in processor datasheet.
|
||||
On CPU models which support it, TjMax is read from a model-specific register.
|
||||
On other models, it is set to an arbitrary value based on weak heuristics.
|
||||
If these heuristics don't work for you, you can pass the correct TjMax value
|
||||
as a module parameter (tjmax).
|
||||
|
||||
Appendix A. Known TjMax lists (TBD):
|
||||
Some information comes from ark.intel.com
|
||||
|
|
|
@ -62,6 +62,13 @@ can be safely used to identify the chip. You will have to instantiate
|
|||
the devices explicitly. Please see Documentation/i2c/instantiating-devices for
|
||||
details.
|
||||
|
||||
WARNING: Do not access chip registers using the i2cdump command, and do not use
|
||||
any of the i2ctools commands on a command register (0xa5 to 0xac). The chips
|
||||
supported by this driver interpret any access to a command register (including
|
||||
read commands) as request to execute the command in question. This may result in
|
||||
power loss, board resets, and/or Flash corruption. Worst case, your board may
|
||||
turn into a brick.
|
||||
|
||||
|
||||
Sysfs entries
|
||||
-------------
|
||||
|
|
|
@ -319,4 +319,6 @@ Code Seq#(hex) Include File Comments
|
|||
<mailto:thomas@winischhofer.net>
|
||||
0xF4 00-1F video/mbxfb.h mbxfb
|
||||
<mailto:raph@8d.com>
|
||||
0xF6 all LTTng Linux Trace Toolkit Next Generation
|
||||
<mailto:mathieu.desnoyers@efficios.com>
|
||||
0xFD all linux/dm-ioctl.h
|
||||
|
|
|
@ -2086,9 +2086,12 @@ bytes respectively. Such letter suffixes can also be entirely omitted.
|
|||
Override pmtimer IOPort with a hex value.
|
||||
e.g. pmtmr=0x508
|
||||
|
||||
pnp.debug [PNP]
|
||||
Enable PNP debug messages. This depends on the
|
||||
CONFIG_PNP_DEBUG_MESSAGES option.
|
||||
pnp.debug=1 [PNP]
|
||||
Enable PNP debug messages (depends on the
|
||||
CONFIG_PNP_DEBUG_MESSAGES option). Change at run-time
|
||||
via /sys/module/pnp/parameters/debug. We always show
|
||||
current resource usage; turning this on also shows
|
||||
possible settings and some assignment information.
|
||||
|
||||
pnpacpi= [ACPI]
|
||||
{ off }
|
||||
|
|
|
@ -1,13 +1,21 @@
|
|||
00-INDEX
|
||||
- this file
|
||||
3c359.txt
|
||||
- information on the 3Com TokenLink Velocity XL (3c5359) driver.
|
||||
3c505.txt
|
||||
- information on the 3Com EtherLink Plus (3c505) driver.
|
||||
3c509.txt
|
||||
- information on the 3Com Etherlink III Series Ethernet cards.
|
||||
6pack.txt
|
||||
- info on the 6pack protocol, an alternative to KISS for AX.25
|
||||
DLINK.txt
|
||||
- info on the D-Link DE-600/DE-620 parallel port pocket adapters
|
||||
PLIP.txt
|
||||
- PLIP: The Parallel Line Internet Protocol device driver
|
||||
README.ipw2100
|
||||
- README for the Intel PRO/Wireless 2100 driver.
|
||||
README.ipw2200
|
||||
- README for the Intel PRO/Wireless 2915ABG and 2200BG driver.
|
||||
README.sb1000
|
||||
- info on General Instrument/NextLevel SURFboard1000 cable modem.
|
||||
alias.txt
|
||||
|
@ -20,8 +28,12 @@ atm.txt
|
|||
- info on where to get ATM programs and support for Linux.
|
||||
ax25.txt
|
||||
- info on using AX.25 and NET/ROM code for Linux
|
||||
batman-adv.txt
|
||||
- B.A.T.M.A.N routing protocol on top of layer 2 Ethernet Frames.
|
||||
baycom.txt
|
||||
- info on the driver for Baycom style amateur radio modems
|
||||
bonding.txt
|
||||
- Linux Ethernet Bonding Driver HOWTO: link aggregation in Linux.
|
||||
bridge.txt
|
||||
- where to get user space programs for ethernet bridging with Linux.
|
||||
can.txt
|
||||
|
@ -34,32 +46,60 @@ cxacru.txt
|
|||
- Conexant AccessRunner USB ADSL Modem
|
||||
cxacru-cf.py
|
||||
- Conexant AccessRunner USB ADSL Modem configuration file parser
|
||||
cxgb.txt
|
||||
- Release Notes for the Chelsio N210 Linux device driver.
|
||||
dccp.txt
|
||||
- the Datagram Congestion Control Protocol (DCCP) (RFC 4340..42).
|
||||
de4x5.txt
|
||||
- the Digital EtherWORKS DE4?? and DE5?? PCI Ethernet driver
|
||||
decnet.txt
|
||||
- info on using the DECnet networking layer in Linux.
|
||||
depca.txt
|
||||
- the Digital DEPCA/EtherWORKS DE1?? and DE2?? LANCE Ethernet driver
|
||||
dl2k.txt
|
||||
- README for D-Link DL2000-based Gigabit Ethernet Adapters (dl2k.ko).
|
||||
dm9000.txt
|
||||
- README for the Simtec DM9000 Network driver.
|
||||
dmfe.txt
|
||||
- info on the Davicom DM9102(A)/DM9132/DM9801 fast ethernet driver.
|
||||
dns_resolver.txt
|
||||
- The DNS resolver module allows kernel servies to make DNS queries.
|
||||
driver.txt
|
||||
- Softnet driver issues.
|
||||
e100.txt
|
||||
- info on Intel's EtherExpress PRO/100 line of 10/100 boards
|
||||
e1000.txt
|
||||
- info on Intel's E1000 line of gigabit ethernet boards
|
||||
e1000e.txt
|
||||
- README for the Intel Gigabit Ethernet Driver (e1000e).
|
||||
eql.txt
|
||||
- serial IP load balancing
|
||||
ewrk3.txt
|
||||
- the Digital EtherWORKS 3 DE203/4/5 Ethernet driver
|
||||
fib_trie.txt
|
||||
- Level Compressed Trie (LC-trie) notes: a structure for routing.
|
||||
filter.txt
|
||||
- Linux Socket Filtering
|
||||
fore200e.txt
|
||||
- FORE Systems PCA-200E/SBA-200E ATM NIC driver info.
|
||||
framerelay.txt
|
||||
- info on using Frame Relay/Data Link Connection Identifier (DLCI).
|
||||
gen_stats.txt
|
||||
- Generic networking statistics for netlink users.
|
||||
generic_hdlc.txt
|
||||
- The generic High Level Data Link Control (HDLC) layer.
|
||||
generic_netlink.txt
|
||||
- info on Generic Netlink
|
||||
gianfar.txt
|
||||
- Gianfar Ethernet Driver.
|
||||
ieee802154.txt
|
||||
- Linux IEEE 802.15.4 implementation, API and drivers
|
||||
ifenslave.c
|
||||
- Configure network interfaces for parallel routing (bonding).
|
||||
igb.txt
|
||||
- README for the Intel Gigabit Ethernet Driver (igb).
|
||||
igbvf.txt
|
||||
- README for the Intel Gigabit Ethernet Driver (igbvf).
|
||||
ip-sysctl.txt
|
||||
- /proc/sys/net/ipv4/* variables
|
||||
ip_dynaddr.txt
|
||||
|
@ -68,41 +108,117 @@ ipddp.txt
|
|||
- AppleTalk-IP Decapsulation and AppleTalk-IP Encapsulation
|
||||
iphase.txt
|
||||
- Interphase PCI ATM (i)Chip IA Linux driver info.
|
||||
ipv6.txt
|
||||
- Options to the ipv6 kernel module.
|
||||
ipvs-sysctl.txt
|
||||
- Per-inode explanation of the /proc/sys/net/ipv4/vs interface.
|
||||
irda.txt
|
||||
- where to get IrDA (infrared) utilities and info for Linux.
|
||||
ixgb.txt
|
||||
- README for the Intel 10 Gigabit Ethernet Driver (ixgb).
|
||||
ixgbe.txt
|
||||
- README for the Intel 10 Gigabit Ethernet Driver (ixgbe).
|
||||
ixgbevf.txt
|
||||
- README for the Intel Virtual Function (VF) Driver (ixgbevf).
|
||||
l2tp.txt
|
||||
- User guide to the L2TP tunnel protocol.
|
||||
lapb-module.txt
|
||||
- programming information of the LAPB module.
|
||||
ltpc.txt
|
||||
- the Apple or Farallon LocalTalk PC card driver
|
||||
mac80211-injection.txt
|
||||
- HOWTO use packet injection with mac80211
|
||||
multicast.txt
|
||||
- Behaviour of cards under Multicast
|
||||
multiqueue.txt
|
||||
- HOWTO for multiqueue network device support.
|
||||
netconsole.txt
|
||||
- The network console module netconsole.ko: configuration and notes.
|
||||
netdev-features.txt
|
||||
- Network interface features API description.
|
||||
netdevices.txt
|
||||
- info on network device driver functions exported to the kernel.
|
||||
netif-msg.txt
|
||||
- Design of the network interface message level setting (NETIF_MSG_*).
|
||||
nfc.txt
|
||||
- The Linux Near Field Communication (NFS) subsystem.
|
||||
olympic.txt
|
||||
- IBM PCI Pit/Pit-Phy/Olympic Token Ring driver info.
|
||||
operstates.txt
|
||||
- Overview of network interface operational states.
|
||||
packet_mmap.txt
|
||||
- User guide to memory mapped packet socket rings (PACKET_[RT]X_RING).
|
||||
phonet.txt
|
||||
- The Phonet packet protocol used in Nokia cellular modems.
|
||||
phy.txt
|
||||
- The PHY abstraction layer.
|
||||
pktgen.txt
|
||||
- User guide to the kernel packet generator (pktgen.ko).
|
||||
policy-routing.txt
|
||||
- IP policy-based routing
|
||||
ppp_generic.txt
|
||||
- Information about the generic PPP driver.
|
||||
proc_net_tcp.txt
|
||||
- Per inode overview of the /proc/net/tcp and /proc/net/tcp6 interfaces.
|
||||
radiotap-headers.txt
|
||||
- Background on radiotap headers.
|
||||
ray_cs.txt
|
||||
- Raylink Wireless LAN card driver info.
|
||||
rds.txt
|
||||
- Background on the reliable, ordered datagram delivery method RDS.
|
||||
regulatory.txt
|
||||
- Overview of the Linux wireless regulatory infrastructure.
|
||||
rxrpc.txt
|
||||
- Guide to the RxRPC protocol.
|
||||
s2io.txt
|
||||
- Release notes for Neterion Xframe I/II 10GbE driver.
|
||||
scaling.txt
|
||||
- Explanation of network scaling techniques: RSS, RPS, RFS, aRFS, XPS.
|
||||
sctp.txt
|
||||
- Notes on the Linux kernel implementation of the SCTP protocol.
|
||||
secid.txt
|
||||
- Explanation of the secid member in flow structures.
|
||||
skfp.txt
|
||||
- SysKonnect FDDI (SK-5xxx, Compaq Netelligent) driver info.
|
||||
smc9.txt
|
||||
- the driver for SMC's 9000 series of Ethernet cards
|
||||
smctr.txt
|
||||
- SMC TokenCard TokenRing Linux driver info.
|
||||
spider-net.txt
|
||||
- README for the Spidernet Driver (as found in PS3 / Cell BE).
|
||||
stmmac.txt
|
||||
- README for the STMicro Synopsys Ethernet driver.
|
||||
tc-actions-env-rules.txt
|
||||
- rules for traffic control (tc) actions.
|
||||
timestamping.txt
|
||||
- overview of network packet timestamping variants.
|
||||
tcp.txt
|
||||
- short blurb on how TCP output takes place.
|
||||
tcp-thin.txt
|
||||
- kernel tuning options for low rate 'thin' TCP streams.
|
||||
tlan.txt
|
||||
- ThunderLAN (Compaq Netelligent 10/100, Olicom OC-2xxx) driver info.
|
||||
tms380tr.txt
|
||||
- SysKonnect Token Ring ISA/PCI adapter driver info.
|
||||
tproxy.txt
|
||||
- Transparent proxy support user guide.
|
||||
tuntap.txt
|
||||
- TUN/TAP device driver, allowing user space Rx/Tx of packets.
|
||||
udplite.txt
|
||||
- UDP-Lite protocol (RFC 3828) introduction.
|
||||
vortex.txt
|
||||
- info on using 3Com Vortex (3c590, 3c592, 3c595, 3c597) Ethernet cards.
|
||||
vxge.txt
|
||||
- README for the Neterion X3100 PCIe Server Adapter.
|
||||
x25.txt
|
||||
- general info on X.25 development.
|
||||
x25-iface.txt
|
||||
- description of the X.25 Packet Layer to LAPB device interface.
|
||||
xfrm_proc.txt
|
||||
- description of the statistics package for XFRM.
|
||||
xfrm_sync.txt
|
||||
- sync patches for XFRM enable migration of an SA between hosts.
|
||||
xfrm_sysctl.txt
|
||||
- description of the XFRM configuration options.
|
||||
z8530drv.txt
|
||||
- info about Linux driver for Z8530 based HDLC cards for AX.25
|
||||
|
|
|
@ -1,3 +1,5 @@
|
|||
Note: This driver doesn't have a maintainer.
|
||||
|
||||
Davicom DM9102(A)/DM9132/DM9801 fast ethernet driver for Linux.
|
||||
|
||||
This program is free software; you can redistribute it and/or
|
||||
|
@ -55,7 +57,6 @@ Test and make sure PCI latency is now correct for all cases.
|
|||
Authors:
|
||||
|
||||
Sten Wang <sten_wang@davicom.com.tw > : Original Author
|
||||
Tobias Ringstrom <tori@unhappy.mine.nu> : Current Maintainer
|
||||
|
||||
Contributors:
|
||||
|
||||
|
|
|
@ -992,7 +992,7 @@ bindv6only - BOOLEAN
|
|||
TRUE: disable IPv4-mapped address feature
|
||||
FALSE: enable IPv4-mapped address feature
|
||||
|
||||
Default: FALSE (as specified in RFC2553bis)
|
||||
Default: FALSE (as specified in RFC3493)
|
||||
|
||||
IPv6 Fragmentation:
|
||||
|
||||
|
@ -1042,7 +1042,7 @@ conf/interface/*:
|
|||
The functional behaviour for certain settings is different
|
||||
depending on whether local forwarding is enabled or not.
|
||||
|
||||
accept_ra - BOOLEAN
|
||||
accept_ra - INTEGER
|
||||
Accept Router Advertisements; autoconfigure using them.
|
||||
|
||||
Possible values are:
|
||||
|
@ -1106,7 +1106,7 @@ dad_transmits - INTEGER
|
|||
The amount of Duplicate Address Detection probes to send.
|
||||
Default: 1
|
||||
|
||||
forwarding - BOOLEAN
|
||||
forwarding - INTEGER
|
||||
Configure interface-specific Host/Router behaviour.
|
||||
|
||||
Note: It is recommended to have the same setting on all
|
||||
|
|
|
@ -52,7 +52,8 @@ module parameter for specifying the number of hardware queues to
|
|||
configure. In the bnx2x driver, for instance, this parameter is called
|
||||
num_queues. A typical RSS configuration would be to have one receive queue
|
||||
for each CPU if the device supports enough queues, or otherwise at least
|
||||
one for each cache domain at a particular cache level (L1, L2, etc.).
|
||||
one for each memory domain, where a memory domain is a set of CPUs that
|
||||
share a particular memory level (L1, L2, NUMA node, etc.).
|
||||
|
||||
The indirection table of an RSS device, which resolves a queue by masked
|
||||
hash, is usually programmed by the driver at initialization. The
|
||||
|
@ -82,11 +83,17 @@ RSS should be enabled when latency is a concern or whenever receive
|
|||
interrupt processing forms a bottleneck. Spreading load between CPUs
|
||||
decreases queue length. For low latency networking, the optimal setting
|
||||
is to allocate as many queues as there are CPUs in the system (or the
|
||||
NIC maximum, if lower). Because the aggregate number of interrupts grows
|
||||
with each additional queue, the most efficient high-rate configuration
|
||||
NIC maximum, if lower). The most efficient high-rate configuration
|
||||
is likely the one with the smallest number of receive queues where no
|
||||
CPU that processes receive interrupts reaches 100% utilization. Per-cpu
|
||||
load can be observed using the mpstat utility.
|
||||
receive queue overflows due to a saturated CPU, because in default
|
||||
mode with interrupt coalescing enabled, the aggregate number of
|
||||
interrupts (and thus work) grows with each additional queue.
|
||||
|
||||
Per-cpu load can be observed using the mpstat utility, but note that on
|
||||
processors with hyperthreading (HT), each hyperthread is represented as
|
||||
a separate CPU. For interrupt handling, HT has shown no benefit in
|
||||
initial tests, so limit the number of queues to the number of CPU cores
|
||||
in the system.
|
||||
|
||||
|
||||
RPS: Receive Packet Steering
|
||||
|
@ -145,7 +152,7 @@ the bitmap.
|
|||
== Suggested Configuration
|
||||
|
||||
For a single queue device, a typical RPS configuration would be to set
|
||||
the rps_cpus to the CPUs in the same cache domain of the interrupting
|
||||
the rps_cpus to the CPUs in the same memory domain of the interrupting
|
||||
CPU. If NUMA locality is not an issue, this could also be all CPUs in
|
||||
the system. At high interrupt rate, it might be wise to exclude the
|
||||
interrupting CPU from the map since that already performs much work.
|
||||
|
@ -154,7 +161,7 @@ For a multi-queue system, if RSS is configured so that a hardware
|
|||
receive queue is mapped to each CPU, then RPS is probably redundant
|
||||
and unnecessary. If there are fewer hardware queues than CPUs, then
|
||||
RPS might be beneficial if the rps_cpus for each queue are the ones that
|
||||
share the same cache domain as the interrupting CPU for that queue.
|
||||
share the same memory domain as the interrupting CPU for that queue.
|
||||
|
||||
|
||||
RFS: Receive Flow Steering
|
||||
|
@ -236,7 +243,7 @@ configured. The number of entries in the global flow table is set through:
|
|||
|
||||
The number of entries in the per-queue flow table are set through:
|
||||
|
||||
/sys/class/net/<dev>/queues/tx-<n>/rps_flow_cnt
|
||||
/sys/class/net/<dev>/queues/rx-<n>/rps_flow_cnt
|
||||
|
||||
== Suggested Configuration
|
||||
|
||||
|
@ -326,7 +333,7 @@ The queue chosen for transmitting a particular flow is saved in the
|
|||
corresponding socket structure for the flow (e.g. a TCP connection).
|
||||
This transmit queue is used for subsequent packets sent on the flow to
|
||||
prevent out of order (ooo) packets. The choice also amortizes the cost
|
||||
of calling get_xps_queues() over all packets in the connection. To avoid
|
||||
of calling get_xps_queues() over all packets in the flow. To avoid
|
||||
ooo packets, the queue for a flow can subsequently only be changed if
|
||||
skb->ooo_okay is set for a packet in the flow. This flag indicates that
|
||||
there are no outstanding packets in the flow, so the transmit queue can
|
||||
|
|
|
@ -431,8 +431,7 @@ drivers/base/power/runtime.c and include/linux/pm_runtime.h:
|
|||
|
||||
void pm_runtime_irq_safe(struct device *dev);
|
||||
- set the power.irq_safe flag for the device, causing the runtime-PM
|
||||
suspend and resume callbacks (but not the idle callback) to be invoked
|
||||
with interrupts disabled
|
||||
callbacks to be invoked with interrupts off
|
||||
|
||||
void pm_runtime_mark_last_busy(struct device *dev);
|
||||
- set the power.last_busy field to the current time
|
||||
|
|
|
@ -123,10 +123,11 @@ be automatically shutdown if it's set to "never".
|
|||
khugepaged runs usually at low frequency so while one may not want to
|
||||
invoke defrag algorithms synchronously during the page faults, it
|
||||
should be worth invoking defrag at least in khugepaged. However it's
|
||||
also possible to disable defrag in khugepaged:
|
||||
also possible to disable defrag in khugepaged by writing 0 or enable
|
||||
defrag in khugepaged by writing 1:
|
||||
|
||||
echo yes >/sys/kernel/mm/transparent_hugepage/khugepaged/defrag
|
||||
echo no >/sys/kernel/mm/transparent_hugepage/khugepaged/defrag
|
||||
echo 0 >/sys/kernel/mm/transparent_hugepage/khugepaged/defrag
|
||||
echo 1 >/sys/kernel/mm/transparent_hugepage/khugepaged/defrag
|
||||
|
||||
You can also control how many pages khugepaged should scan at each
|
||||
pass:
|
||||
|
|
39
MAINTAINERS
39
MAINTAINERS
|
@ -1278,7 +1278,6 @@ F: drivers/input/misc/ati_remote2.c
|
|||
ATLX ETHERNET DRIVERS
|
||||
M: Jay Cliburn <jcliburn@gmail.com>
|
||||
M: Chris Snook <chris.snook@gmail.com>
|
||||
M: Jie Yang <jie.yang@atheros.com>
|
||||
L: netdev@vger.kernel.org
|
||||
W: http://sourceforge.net/projects/atl1
|
||||
W: http://atl1.sourceforge.net
|
||||
|
@ -1574,7 +1573,6 @@ F: drivers/scsi/bfa/
|
|||
|
||||
BROCADE BNA 10 GIGABIT ETHERNET DRIVER
|
||||
M: Rasesh Mody <rmody@brocade.com>
|
||||
M: Debashis Dutt <ddutt@brocade.com>
|
||||
L: netdev@vger.kernel.org
|
||||
S: Supported
|
||||
F: drivers/net/bna/
|
||||
|
@ -1758,7 +1756,6 @@ F: Documentation/zh_CN/
|
|||
|
||||
CISCO VIC ETHERNET NIC DRIVER
|
||||
M: Christian Benvenuti <benve@cisco.com>
|
||||
M: Vasanthy Kolluri <vkolluri@cisco.com>
|
||||
M: Roopa Prabhu <roprabhu@cisco.com>
|
||||
M: David Wang <dwang2@cisco.com>
|
||||
S: Supported
|
||||
|
@ -1883,7 +1880,7 @@ S: Maintained
|
|||
F: drivers/connector/
|
||||
|
||||
CONTROL GROUPS (CGROUPS)
|
||||
M: Paul Menage <menage@google.com>
|
||||
M: Paul Menage <paul@paulmenage.org>
|
||||
M: Li Zefan <lizf@cn.fujitsu.com>
|
||||
L: containers@lists.linux-foundation.org
|
||||
S: Maintained
|
||||
|
@ -1932,7 +1929,7 @@ S: Maintained
|
|||
F: tools/power/cpupower
|
||||
|
||||
CPUSETS
|
||||
M: Paul Menage <menage@google.com>
|
||||
M: Paul Menage <paul@paulmenage.org>
|
||||
W: http://www.bullopensource.org/cpuset/
|
||||
W: http://oss.sgi.com/projects/cpusets/
|
||||
S: Supported
|
||||
|
@ -2649,11 +2646,11 @@ F: drivers/net/wan/dlci.c
|
|||
F: drivers/net/wan/sdla.c
|
||||
|
||||
FRAMEBUFFER LAYER
|
||||
M: Paul Mundt <lethal@linux-sh.org>
|
||||
M: Florian Tobias Schandinat <FlorianSchandinat@gmx.de>
|
||||
L: linux-fbdev@vger.kernel.org
|
||||
W: http://linux-fbdev.sourceforge.net/
|
||||
Q: http://patchwork.kernel.org/project/linux-fbdev/list/
|
||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/lethal/fbdev-2.6.git
|
||||
T: git git://github.com/schandinat/linux-2.6.git fbdev-next
|
||||
S: Maintained
|
||||
F: Documentation/fb/
|
||||
F: Documentation/devicetree/bindings/fb/
|
||||
|
@ -3262,6 +3259,17 @@ F: Documentation/input/multi-touch-protocol.txt
|
|||
F: drivers/input/input-mt.c
|
||||
K: \b(ABS|SYN)_MT_
|
||||
|
||||
INTEL C600 SERIES SAS CONTROLLER DRIVER
|
||||
M: Intel SCU Linux support <intel-linux-scu@intel.com>
|
||||
M: Dan Williams <dan.j.williams@intel.com>
|
||||
M: Dave Jiang <dave.jiang@intel.com>
|
||||
M: Ed Nadolski <edmund.nadolski@intel.com>
|
||||
L: linux-scsi@vger.kernel.org
|
||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/djbw/isci.git
|
||||
S: Maintained
|
||||
F: drivers/scsi/isci/
|
||||
F: firmware/isci/
|
||||
|
||||
INTEL IDLE DRIVER
|
||||
M: Len Brown <lenb@kernel.org>
|
||||
L: linux-pm@lists.linux-foundation.org
|
||||
|
@ -4404,7 +4412,8 @@ L: netfilter@vger.kernel.org
|
|||
L: coreteam@netfilter.org
|
||||
W: http://www.netfilter.org/
|
||||
W: http://www.iptables.org/
|
||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/kaber/nf-2.6.git
|
||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/netfilter/nf-2.6.git
|
||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/netfilter/nf-next-2.6.git
|
||||
S: Supported
|
||||
F: include/linux/netfilter*
|
||||
F: include/linux/netfilter/
|
||||
|
@ -4450,8 +4459,8 @@ M: "David S. Miller" <davem@davemloft.net>
|
|||
L: netdev@vger.kernel.org
|
||||
W: http://www.linuxfoundation.org/en/Net
|
||||
W: http://patchwork.ozlabs.org/project/netdev/list/
|
||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/davem/net-2.6.git
|
||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/davem/net-next-2.6.git
|
||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/davem/net.git
|
||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/davem/net-next.git
|
||||
S: Maintained
|
||||
F: net/
|
||||
F: include/net/
|
||||
|
@ -4774,7 +4783,7 @@ F: drivers/net/wireless/orinoco/
|
|||
|
||||
OSD LIBRARY and FILESYSTEM
|
||||
M: Boaz Harrosh <bharrosh@panasas.com>
|
||||
M: Benny Halevy <bhalevy@panasas.com>
|
||||
M: Benny Halevy <bhalevy@tonian.com>
|
||||
L: osd-dev@open-osd.org
|
||||
W: http://open-osd.org
|
||||
T: git git://git.open-osd.org/open-osd.git
|
||||
|
@ -5532,6 +5541,7 @@ F: include/media/*7146*
|
|||
|
||||
SAMSUNG AUDIO (ASoC) DRIVERS
|
||||
M: Jassi Brar <jassisinghbrar@gmail.com>
|
||||
M: Sangbeom Kim <sbkim73@samsung.com>
|
||||
L: alsa-devel@alsa-project.org (moderated for non-subscribers)
|
||||
S: Supported
|
||||
F: sound/soc/samsung
|
||||
|
@ -6364,7 +6374,6 @@ S: Supported
|
|||
F: arch/arm/mach-tegra
|
||||
|
||||
TEHUTI ETHERNET DRIVER
|
||||
M: Alexander Indenbaum <baum@tehutinetworks.net>
|
||||
M: Andy Gospodarek <andy@greyhouse.net>
|
||||
L: netdev@vger.kernel.org
|
||||
S: Supported
|
||||
|
@ -7087,7 +7096,7 @@ S: Supported
|
|||
F: drivers/mmc/host/vub300.c
|
||||
|
||||
W1 DALLAS'S 1-WIRE BUS
|
||||
M: Evgeniy Polyakov <johnpol@2ka.mipt.ru>
|
||||
M: Evgeniy Polyakov <zbr@ioremap.net>
|
||||
S: Maintained
|
||||
F: Documentation/w1/
|
||||
F: drivers/w1/
|
||||
|
@ -7199,6 +7208,9 @@ W: http://opensource.wolfsonmicro.com/content/linux-drivers-wolfson-devices
|
|||
S: Supported
|
||||
F: Documentation/hwmon/wm83??
|
||||
F: drivers/leds/leds-wm83*.c
|
||||
F: drivers/input/misc/wm831x-on.c
|
||||
F: drivers/input/touchscreen/wm831x-ts.c
|
||||
F: drivers/input/touchscreen/wm97*.c
|
||||
F: drivers/mfd/wm8*.c
|
||||
F: drivers/power/wm83*.c
|
||||
F: drivers/rtc/rtc-wm83*.c
|
||||
|
@ -7208,6 +7220,7 @@ F: drivers/watchdog/wm83*_wdt.c
|
|||
F: include/linux/mfd/wm831x/
|
||||
F: include/linux/mfd/wm8350/
|
||||
F: include/linux/mfd/wm8400*
|
||||
F: include/linux/wm97xx.h
|
||||
F: include/sound/wm????.h
|
||||
F: sound/soc/codecs/wm*
|
||||
|
||||
|
|
2
Makefile
2
Makefile
|
@ -1,7 +1,7 @@
|
|||
VERSION = 3
|
||||
PATCHLEVEL = 1
|
||||
SUBLEVEL = 0
|
||||
EXTRAVERSION = -rc3
|
||||
EXTRAVERSION = -rc9
|
||||
NAME = "Divemaster Edition"
|
||||
|
||||
# *DOCUMENTATION*
|
||||
|
|
|
@ -51,7 +51,7 @@ config GENERIC_CMOS_UPDATE
|
|||
def_bool y
|
||||
|
||||
config GENERIC_GPIO
|
||||
def_bool y
|
||||
bool
|
||||
|
||||
config ZONE_DMA
|
||||
bool
|
||||
|
|
|
@ -27,13 +27,4 @@
|
|||
#define UAC_NOFIX 2
|
||||
#define UAC_SIGBUS 4
|
||||
|
||||
|
||||
#ifdef __KERNEL__
|
||||
|
||||
/* This is the shift that is applied to the UAC bits as stored in the
|
||||
per-thread flags. See thread_info.h. */
|
||||
#define UAC_SHIFT 6
|
||||
|
||||
#endif
|
||||
|
||||
#endif /* __ASM_ALPHA_SYSINFO_H */
|
||||
|
|
|
@ -74,9 +74,9 @@ register struct thread_info *__current_thread_info __asm__("$8");
|
|||
#define TIF_NEED_RESCHED 3 /* rescheduling necessary */
|
||||
#define TIF_POLLING_NRFLAG 8 /* poll_idle is polling NEED_RESCHED */
|
||||
#define TIF_DIE_IF_KERNEL 9 /* dik recursion lock */
|
||||
#define TIF_UAC_NOPRINT 10 /* see sysinfo.h */
|
||||
#define TIF_UAC_NOFIX 11
|
||||
#define TIF_UAC_SIGBUS 12
|
||||
#define TIF_UAC_NOPRINT 10 /* ! Preserve sequence of following */
|
||||
#define TIF_UAC_NOFIX 11 /* ! flags as they match */
|
||||
#define TIF_UAC_SIGBUS 12 /* ! userspace part of 'osf_sysinfo' */
|
||||
#define TIF_MEMDIE 13 /* is terminating due to OOM killer */
|
||||
#define TIF_RESTORE_SIGMASK 14 /* restore signal mask in do_signal */
|
||||
#define TIF_FREEZE 16 /* is freezing for suspend */
|
||||
|
@ -97,7 +97,7 @@ register struct thread_info *__current_thread_info __asm__("$8");
|
|||
#define _TIF_ALLWORK_MASK (_TIF_WORK_MASK \
|
||||
| _TIF_SYSCALL_TRACE)
|
||||
|
||||
#define ALPHA_UAC_SHIFT 10
|
||||
#define ALPHA_UAC_SHIFT TIF_UAC_NOPRINT
|
||||
#define ALPHA_UAC_MASK (1 << TIF_UAC_NOPRINT | 1 << TIF_UAC_NOFIX | \
|
||||
1 << TIF_UAC_SIGBUS)
|
||||
|
||||
|
|
|
@ -42,6 +42,7 @@
|
|||
#include <asm/uaccess.h>
|
||||
#include <asm/system.h>
|
||||
#include <asm/sysinfo.h>
|
||||
#include <asm/thread_info.h>
|
||||
#include <asm/hwrpb.h>
|
||||
#include <asm/processor.h>
|
||||
|
||||
|
@ -633,9 +634,10 @@ SYSCALL_DEFINE5(osf_getsysinfo, unsigned long, op, void __user *, buffer,
|
|||
case GSI_UACPROC:
|
||||
if (nbytes < sizeof(unsigned int))
|
||||
return -EINVAL;
|
||||
w = (current_thread_info()->flags >> UAC_SHIFT) & UAC_BITMASK;
|
||||
if (put_user(w, (unsigned int __user *)buffer))
|
||||
return -EFAULT;
|
||||
w = (current_thread_info()->flags >> ALPHA_UAC_SHIFT) &
|
||||
UAC_BITMASK;
|
||||
if (put_user(w, (unsigned int __user *)buffer))
|
||||
return -EFAULT;
|
||||
return 1;
|
||||
|
||||
case GSI_PROC_TYPE:
|
||||
|
@ -756,8 +758,8 @@ SYSCALL_DEFINE5(osf_setsysinfo, unsigned long, op, void __user *, buffer,
|
|||
case SSIN_UACPROC:
|
||||
again:
|
||||
old = current_thread_info()->flags;
|
||||
new = old & ~(UAC_BITMASK << UAC_SHIFT);
|
||||
new = new | (w & UAC_BITMASK) << UAC_SHIFT;
|
||||
new = old & ~(UAC_BITMASK << ALPHA_UAC_SHIFT);
|
||||
new = new | (w & UAC_BITMASK) << ALPHA_UAC_SHIFT;
|
||||
if (cmpxchg(¤t_thread_info()->flags,
|
||||
old, new) != old)
|
||||
goto again;
|
||||
|
|
|
@ -360,7 +360,7 @@ sys_call_table:
|
|||
.quad sys_newuname
|
||||
.quad sys_nanosleep /* 340 */
|
||||
.quad sys_mremap
|
||||
.quad sys_nfsservctl
|
||||
.quad sys_ni_syscall /* old nfsservctl */
|
||||
.quad sys_setresuid
|
||||
.quad sys_getresuid
|
||||
.quad sys_pciconfig_read /* 345 */
|
||||
|
|
|
@ -1272,6 +1272,32 @@ config ARM_ERRATA_754327
|
|||
This workaround defines cpu_relax() as smp_mb(), preventing correctly
|
||||
written polling loops from denying visibility of updates to memory.
|
||||
|
||||
config ARM_ERRATA_364296
|
||||
bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
|
||||
depends on CPU_V6 && !SMP
|
||||
help
|
||||
This options enables the workaround for the 364296 ARM1136
|
||||
r0p2 erratum (possible cache data corruption with
|
||||
hit-under-miss enabled). It sets the undocumented bit 31 in
|
||||
the auxiliary control register and the FI bit in the control
|
||||
register, thus disabling hit-under-miss without putting the
|
||||
processor into full low interrupt latency mode. ARM11MPCore
|
||||
is not affected.
|
||||
|
||||
config ARM_ERRATA_764369
|
||||
bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
|
||||
depends on CPU_V7 && SMP
|
||||
help
|
||||
This option enables the workaround for erratum 764369
|
||||
affecting Cortex-A9 MPCore with two or more processors (all
|
||||
current revisions). Under certain timing circumstances, a data
|
||||
cache line maintenance operation by MVA targeting an Inner
|
||||
Shareable memory region may fail to proceed up to either the
|
||||
Point of Coherency or to the Point of Unification of the
|
||||
system. This workaround adds a DSB instruction before the
|
||||
relevant cache maintenance functions and sets a specific bit
|
||||
in the diagnostic control register of the SCU.
|
||||
|
||||
endmenu
|
||||
|
||||
source "arch/arm/common/Kconfig"
|
||||
|
|
|
@ -82,7 +82,7 @@ asmlinkage void mmc_loader(unsigned char *buf, unsigned long len)
|
|||
|
||||
|
||||
/* Disable clock to MMC hardware block */
|
||||
__raw_writel(__raw_readl(SMSTPCR3) & (1 << 12), SMSTPCR3);
|
||||
__raw_writel(__raw_readl(SMSTPCR3) | (1 << 12), SMSTPCR3);
|
||||
|
||||
mmc_update_progress(MMC_PROGRESS_DONE);
|
||||
}
|
||||
|
|
|
@ -85,7 +85,7 @@ asmlinkage void mmc_loader(unsigned short *buf, unsigned long len)
|
|||
goto err;
|
||||
|
||||
/* Disable clock to SDHI1 hardware block */
|
||||
__raw_writel(__raw_readl(SMSTPCR3) & (1 << 13), SMSTPCR3);
|
||||
__raw_writel(__raw_readl(SMSTPCR3) | (1 << 13), SMSTPCR3);
|
||||
|
||||
mmc_update_progress(MMC_PROGRESS_DONE);
|
||||
|
||||
|
|
|
@ -57,14 +57,14 @@
|
|||
};
|
||||
|
||||
sdhci@c8000200 {
|
||||
gpios = <&gpio 69 0>, /* cd, gpio PI5 */
|
||||
<&gpio 57 0>, /* wp, gpio PH1 */
|
||||
<&gpio 155 0>; /* power, gpio PT3 */
|
||||
cd-gpios = <&gpio 69 0>; /* gpio PI5 */
|
||||
wp-gpios = <&gpio 57 0>; /* gpio PH1 */
|
||||
power-gpios = <&gpio 155 0>; /* gpio PT3 */
|
||||
};
|
||||
|
||||
sdhci@c8000600 {
|
||||
gpios = <&gpio 58 0>, /* cd, gpio PH2 */
|
||||
<&gpio 59 0>, /* wp, gpio PH3 */
|
||||
<&gpio 70 0>; /* power, gpio PI6 */
|
||||
cd-gpios = <&gpio 58 0>; /* gpio PH2 */
|
||||
wp-gpios = <&gpio 59 0>; /* gpio PH3 */
|
||||
power-gpios = <&gpio 70 0>; /* gpio PI6 */
|
||||
};
|
||||
};
|
||||
|
|
|
@ -21,8 +21,8 @@
|
|||
};
|
||||
|
||||
sdhci@c8000400 {
|
||||
gpios = <&gpio 69 0>, /* cd, gpio PI5 */
|
||||
<&gpio 57 0>, /* wp, gpio PH1 */
|
||||
<&gpio 70 0>; /* power, gpio PI6 */
|
||||
cd-gpios = <&gpio 69 0>; /* gpio PI5 */
|
||||
wp-gpios = <&gpio 57 0>; /* gpio PH1 */
|
||||
power-gpios = <&gpio 70 0>; /* gpio PI6 */
|
||||
};
|
||||
};
|
||||
|
|
|
@ -26,6 +26,7 @@ CONFIG_MACH_MX23EVK=y
|
|||
CONFIG_MACH_MX28EVK=y
|
||||
CONFIG_MACH_STMP378X_DEVB=y
|
||||
CONFIG_MACH_TX28=y
|
||||
CONFIG_MACH_M28EVK=y
|
||||
# CONFIG_ARM_THUMB is not set
|
||||
CONFIG_NO_HZ=y
|
||||
CONFIG_HIGH_RES_TIMERS=y
|
||||
|
|
|
@ -25,17 +25,17 @@
|
|||
|
||||
#ifdef CONFIG_SMP
|
||||
|
||||
#define __futex_atomic_op(insn, ret, oldval, uaddr, oparg) \
|
||||
#define __futex_atomic_op(insn, ret, oldval, tmp, uaddr, oparg) \
|
||||
smp_mb(); \
|
||||
__asm__ __volatile__( \
|
||||
"1: ldrex %1, [%2]\n" \
|
||||
"1: ldrex %1, [%3]\n" \
|
||||
" " insn "\n" \
|
||||
"2: strex %1, %0, [%2]\n" \
|
||||
" teq %1, #0\n" \
|
||||
"2: strex %2, %0, [%3]\n" \
|
||||
" teq %2, #0\n" \
|
||||
" bne 1b\n" \
|
||||
" mov %0, #0\n" \
|
||||
__futex_atomic_ex_table("%4") \
|
||||
: "=&r" (ret), "=&r" (oldval) \
|
||||
__futex_atomic_ex_table("%5") \
|
||||
: "=&r" (ret), "=&r" (oldval), "=&r" (tmp) \
|
||||
: "r" (uaddr), "r" (oparg), "Ir" (-EFAULT) \
|
||||
: "cc", "memory")
|
||||
|
||||
|
@ -73,14 +73,14 @@ futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr,
|
|||
#include <linux/preempt.h>
|
||||
#include <asm/domain.h>
|
||||
|
||||
#define __futex_atomic_op(insn, ret, oldval, uaddr, oparg) \
|
||||
#define __futex_atomic_op(insn, ret, oldval, tmp, uaddr, oparg) \
|
||||
__asm__ __volatile__( \
|
||||
"1: " T(ldr) " %1, [%2]\n" \
|
||||
"1: " T(ldr) " %1, [%3]\n" \
|
||||
" " insn "\n" \
|
||||
"2: " T(str) " %0, [%2]\n" \
|
||||
"2: " T(str) " %0, [%3]\n" \
|
||||
" mov %0, #0\n" \
|
||||
__futex_atomic_ex_table("%4") \
|
||||
: "=&r" (ret), "=&r" (oldval) \
|
||||
__futex_atomic_ex_table("%5") \
|
||||
: "=&r" (ret), "=&r" (oldval), "=&r" (tmp) \
|
||||
: "r" (uaddr), "r" (oparg), "Ir" (-EFAULT) \
|
||||
: "cc", "memory")
|
||||
|
||||
|
@ -117,7 +117,7 @@ futex_atomic_op_inuser (int encoded_op, u32 __user *uaddr)
|
|||
int cmp = (encoded_op >> 24) & 15;
|
||||
int oparg = (encoded_op << 8) >> 20;
|
||||
int cmparg = (encoded_op << 20) >> 20;
|
||||
int oldval = 0, ret;
|
||||
int oldval = 0, ret, tmp;
|
||||
|
||||
if (encoded_op & (FUTEX_OP_OPARG_SHIFT << 28))
|
||||
oparg = 1 << oparg;
|
||||
|
@ -129,19 +129,19 @@ futex_atomic_op_inuser (int encoded_op, u32 __user *uaddr)
|
|||
|
||||
switch (op) {
|
||||
case FUTEX_OP_SET:
|
||||
__futex_atomic_op("mov %0, %3", ret, oldval, uaddr, oparg);
|
||||
__futex_atomic_op("mov %0, %4", ret, oldval, tmp, uaddr, oparg);
|
||||
break;
|
||||
case FUTEX_OP_ADD:
|
||||
__futex_atomic_op("add %0, %1, %3", ret, oldval, uaddr, oparg);
|
||||
__futex_atomic_op("add %0, %1, %4", ret, oldval, tmp, uaddr, oparg);
|
||||
break;
|
||||
case FUTEX_OP_OR:
|
||||
__futex_atomic_op("orr %0, %1, %3", ret, oldval, uaddr, oparg);
|
||||
__futex_atomic_op("orr %0, %1, %4", ret, oldval, tmp, uaddr, oparg);
|
||||
break;
|
||||
case FUTEX_OP_ANDN:
|
||||
__futex_atomic_op("and %0, %1, %3", ret, oldval, uaddr, ~oparg);
|
||||
__futex_atomic_op("and %0, %1, %4", ret, oldval, tmp, uaddr, ~oparg);
|
||||
break;
|
||||
case FUTEX_OP_XOR:
|
||||
__futex_atomic_op("eor %0, %1, %3", ret, oldval, uaddr, oparg);
|
||||
__futex_atomic_op("eor %0, %1, %4", ret, oldval, tmp, uaddr, oparg);
|
||||
break;
|
||||
default:
|
||||
ret = -ENOSYS;
|
||||
|
|
|
@ -45,8 +45,13 @@
|
|||
#define L2X0_CLEAN_INV_LINE_PA 0x7F0
|
||||
#define L2X0_CLEAN_INV_LINE_IDX 0x7F8
|
||||
#define L2X0_CLEAN_INV_WAY 0x7FC
|
||||
#define L2X0_LOCKDOWN_WAY_D 0x900
|
||||
#define L2X0_LOCKDOWN_WAY_I 0x904
|
||||
/*
|
||||
* The lockdown registers repeat 8 times for L310, the L210 has only one
|
||||
* D and one I lockdown register at 0x0900 and 0x0904.
|
||||
*/
|
||||
#define L2X0_LOCKDOWN_WAY_D_BASE 0x900
|
||||
#define L2X0_LOCKDOWN_WAY_I_BASE 0x904
|
||||
#define L2X0_LOCKDOWN_STRIDE 0x08
|
||||
#define L2X0_TEST_OPERATION 0xF00
|
||||
#define L2X0_LINE_DATA 0xF10
|
||||
#define L2X0_LINE_TAG 0xF30
|
||||
|
@ -64,7 +69,7 @@
|
|||
#define L2X0_AUX_CTRL_MASK 0xc0000fff
|
||||
#define L2X0_AUX_CTRL_ASSOCIATIVITY_SHIFT 16
|
||||
#define L2X0_AUX_CTRL_WAY_SIZE_SHIFT 17
|
||||
#define L2X0_AUX_CTRL_WAY_SIZE_MASK (0x3 << 17)
|
||||
#define L2X0_AUX_CTRL_WAY_SIZE_MASK (0x7 << 17)
|
||||
#define L2X0_AUX_CTRL_SHARE_OVERRIDE_SHIFT 22
|
||||
#define L2X0_AUX_CTRL_NS_LOCKDOWN_SHIFT 26
|
||||
#define L2X0_AUX_CTRL_NS_INT_CTRL_SHIFT 27
|
||||
|
|
|
@ -41,7 +41,7 @@ struct arm_pmu_platdata {
|
|||
* encoded error on failure.
|
||||
*/
|
||||
extern struct platform_device *
|
||||
reserve_pmu(enum arm_pmu_type device);
|
||||
reserve_pmu(enum arm_pmu_type type);
|
||||
|
||||
/**
|
||||
* release_pmu() - Relinquish control of the performance counters
|
||||
|
@ -62,26 +62,26 @@ release_pmu(enum arm_pmu_type type);
|
|||
* the actual hardware initialisation.
|
||||
*/
|
||||
extern int
|
||||
init_pmu(enum arm_pmu_type device);
|
||||
init_pmu(enum arm_pmu_type type);
|
||||
|
||||
#else /* CONFIG_CPU_HAS_PMU */
|
||||
|
||||
#include <linux/err.h>
|
||||
|
||||
static inline struct platform_device *
|
||||
reserve_pmu(enum arm_pmu_type device)
|
||||
reserve_pmu(enum arm_pmu_type type)
|
||||
{
|
||||
return ERR_PTR(-ENODEV);
|
||||
}
|
||||
|
||||
static inline int
|
||||
release_pmu(struct platform_device *pdev)
|
||||
release_pmu(enum arm_pmu_type type)
|
||||
{
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
static inline int
|
||||
init_pmu(enum arm_pmu_type device)
|
||||
init_pmu(enum arm_pmu_type type)
|
||||
{
|
||||
return -ENODEV;
|
||||
}
|
||||
|
|
|
@ -478,8 +478,8 @@
|
|||
/*
|
||||
* Unimplemented (or alternatively implemented) syscalls
|
||||
*/
|
||||
#define __IGNORE_fadvise64_64 1
|
||||
#define __IGNORE_migrate_pages 1
|
||||
#define __IGNORE_fadvise64_64
|
||||
#define __IGNORE_migrate_pages
|
||||
|
||||
#endif /* __KERNEL__ */
|
||||
#endif /* __ASM_ARM_UNISTD_H */
|
||||
|
|
|
@ -178,7 +178,7 @@
|
|||
CALL(sys_ni_syscall) /* vm86 */
|
||||
CALL(sys_ni_syscall) /* was sys_query_module */
|
||||
CALL(sys_poll)
|
||||
CALL(sys_nfsservctl)
|
||||
CALL(sys_ni_syscall) /* was nfsservctl */
|
||||
/* 170 */ CALL(sys_setresgid16)
|
||||
CALL(sys_getresgid16)
|
||||
CALL(sys_prctl)
|
||||
|
|
|
@ -31,7 +31,7 @@ static int __devinit pmu_register(struct platform_device *pdev,
|
|||
{
|
||||
if (type < 0 || type >= ARM_NUM_PMU_DEVICES) {
|
||||
pr_warning("received registration request for unknown "
|
||||
"device %d\n", type);
|
||||
"PMU device type %d\n", type);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
|
@ -112,17 +112,17 @@ static int __init register_pmu_driver(void)
|
|||
device_initcall(register_pmu_driver);
|
||||
|
||||
struct platform_device *
|
||||
reserve_pmu(enum arm_pmu_type device)
|
||||
reserve_pmu(enum arm_pmu_type type)
|
||||
{
|
||||
struct platform_device *pdev;
|
||||
|
||||
if (test_and_set_bit_lock(device, &pmu_lock)) {
|
||||
if (test_and_set_bit_lock(type, &pmu_lock)) {
|
||||
pdev = ERR_PTR(-EBUSY);
|
||||
} else if (pmu_devices[device] == NULL) {
|
||||
clear_bit_unlock(device, &pmu_lock);
|
||||
} else if (pmu_devices[type] == NULL) {
|
||||
clear_bit_unlock(type, &pmu_lock);
|
||||
pdev = ERR_PTR(-ENODEV);
|
||||
} else {
|
||||
pdev = pmu_devices[device];
|
||||
pdev = pmu_devices[type];
|
||||
}
|
||||
|
||||
return pdev;
|
||||
|
@ -130,11 +130,11 @@ reserve_pmu(enum arm_pmu_type device)
|
|||
EXPORT_SYMBOL_GPL(reserve_pmu);
|
||||
|
||||
int
|
||||
release_pmu(enum arm_pmu_type device)
|
||||
release_pmu(enum arm_pmu_type type)
|
||||
{
|
||||
if (WARN_ON(!pmu_devices[device]))
|
||||
if (WARN_ON(!pmu_devices[type]))
|
||||
return -EINVAL;
|
||||
clear_bit_unlock(device, &pmu_lock);
|
||||
clear_bit_unlock(type, &pmu_lock);
|
||||
return 0;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(release_pmu);
|
||||
|
@ -182,17 +182,17 @@ init_cpu_pmu(void)
|
|||
}
|
||||
|
||||
int
|
||||
init_pmu(enum arm_pmu_type device)
|
||||
init_pmu(enum arm_pmu_type type)
|
||||
{
|
||||
int err = 0;
|
||||
|
||||
switch (device) {
|
||||
switch (type) {
|
||||
case ARM_PMU_DEVICE_CPU:
|
||||
err = init_cpu_pmu();
|
||||
break;
|
||||
default:
|
||||
pr_warning("attempt to initialise unknown device %d\n",
|
||||
device);
|
||||
pr_warning("attempt to initialise PMU of unknown "
|
||||
"type %d\n", type);
|
||||
err = -EINVAL;
|
||||
}
|
||||
|
||||
|
|
|
@ -57,7 +57,8 @@ relocate_new_kernel:
|
|||
mov r0,#0
|
||||
ldr r1,kexec_mach_type
|
||||
ldr r2,kexec_boot_atags
|
||||
mov pc,lr
|
||||
ARM( mov pc, lr )
|
||||
THUMB( bx lr )
|
||||
|
||||
.align
|
||||
|
||||
|
|
|
@ -280,18 +280,19 @@ static void __init cacheid_init(void)
|
|||
if (arch >= CPU_ARCH_ARMv6) {
|
||||
if ((cachetype & (7 << 29)) == 4 << 29) {
|
||||
/* ARMv7 register format */
|
||||
arch = CPU_ARCH_ARMv7;
|
||||
cacheid = CACHEID_VIPT_NONALIASING;
|
||||
if ((cachetype & (3 << 14)) == 1 << 14)
|
||||
cacheid |= CACHEID_ASID_TAGGED;
|
||||
else if (cpu_has_aliasing_icache(CPU_ARCH_ARMv7))
|
||||
cacheid |= CACHEID_VIPT_I_ALIASING;
|
||||
} else if (cachetype & (1 << 23)) {
|
||||
cacheid = CACHEID_VIPT_ALIASING;
|
||||
} else {
|
||||
cacheid = CACHEID_VIPT_NONALIASING;
|
||||
if (cpu_has_aliasing_icache(CPU_ARCH_ARMv6))
|
||||
cacheid |= CACHEID_VIPT_I_ALIASING;
|
||||
arch = CPU_ARCH_ARMv6;
|
||||
if (cachetype & (1 << 23))
|
||||
cacheid = CACHEID_VIPT_ALIASING;
|
||||
else
|
||||
cacheid = CACHEID_VIPT_NONALIASING;
|
||||
}
|
||||
if (cpu_has_aliasing_icache(arch))
|
||||
cacheid |= CACHEID_VIPT_I_ALIASING;
|
||||
} else {
|
||||
cacheid = CACHEID_VIVT;
|
||||
}
|
||||
|
|
|
@ -13,6 +13,7 @@
|
|||
|
||||
#include <asm/smp_scu.h>
|
||||
#include <asm/cacheflush.h>
|
||||
#include <asm/cputype.h>
|
||||
|
||||
#define SCU_CTRL 0x00
|
||||
#define SCU_CONFIG 0x04
|
||||
|
@ -37,6 +38,15 @@ void __init scu_enable(void __iomem *scu_base)
|
|||
{
|
||||
u32 scu_ctrl;
|
||||
|
||||
#ifdef CONFIG_ARM_ERRATA_764369
|
||||
/* Cortex-A9 only */
|
||||
if ((read_cpuid(CPUID_ID) & 0xff0ffff0) == 0x410fc090) {
|
||||
scu_ctrl = __raw_readl(scu_base + 0x30);
|
||||
if (!(scu_ctrl & 1))
|
||||
__raw_writel(scu_ctrl | 0x1, scu_base + 0x30);
|
||||
}
|
||||
#endif
|
||||
|
||||
scu_ctrl = __raw_readl(scu_base + SCU_CTRL);
|
||||
/* already enabled? */
|
||||
if (scu_ctrl & 1)
|
||||
|
|
|
@ -137,8 +137,8 @@ void __cpuinit twd_timer_setup(struct clock_event_device *clk)
|
|||
clk->max_delta_ns = clockevent_delta2ns(0xffffffff, clk);
|
||||
clk->min_delta_ns = clockevent_delta2ns(0xf, clk);
|
||||
|
||||
clockevents_register_device(clk);
|
||||
|
||||
/* Make sure our local interrupt controller has this enabled */
|
||||
gic_enable_ppi(clk->irq);
|
||||
|
||||
clockevents_register_device(clk);
|
||||
}
|
||||
|
|
|
@ -23,8 +23,10 @@
|
|||
|
||||
#if defined(CONFIG_SMP_ON_UP) && !defined(CONFIG_DEBUG_SPINLOCK)
|
||||
#define ARM_EXIT_KEEP(x) x
|
||||
#define ARM_EXIT_DISCARD(x)
|
||||
#else
|
||||
#define ARM_EXIT_KEEP(x)
|
||||
#define ARM_EXIT_DISCARD(x) x
|
||||
#endif
|
||||
|
||||
OUTPUT_ARCH(arm)
|
||||
|
@ -39,6 +41,11 @@ jiffies = jiffies_64 + 4;
|
|||
SECTIONS
|
||||
{
|
||||
/*
|
||||
* XXX: The linker does not define how output sections are
|
||||
* assigned to input sections when there are multiple statements
|
||||
* matching the same input section name. There is no documented
|
||||
* order of matching.
|
||||
*
|
||||
* unwind exit sections must be discarded before the rest of the
|
||||
* unwind sections get included.
|
||||
*/
|
||||
|
@ -47,6 +54,9 @@ SECTIONS
|
|||
*(.ARM.extab.exit.text)
|
||||
ARM_CPU_DISCARD(*(.ARM.exidx.cpuexit.text))
|
||||
ARM_CPU_DISCARD(*(.ARM.extab.cpuexit.text))
|
||||
ARM_EXIT_DISCARD(EXIT_TEXT)
|
||||
ARM_EXIT_DISCARD(EXIT_DATA)
|
||||
EXIT_CALL
|
||||
#ifndef CONFIG_HOTPLUG
|
||||
*(.ARM.exidx.devexit.text)
|
||||
*(.ARM.extab.devexit.text)
|
||||
|
@ -58,6 +68,8 @@ SECTIONS
|
|||
#ifndef CONFIG_SMP_ON_UP
|
||||
*(.alt.smp.init)
|
||||
#endif
|
||||
*(.discard)
|
||||
*(.discard.*)
|
||||
}
|
||||
|
||||
#ifdef CONFIG_XIP_KERNEL
|
||||
|
@ -279,9 +291,6 @@ SECTIONS
|
|||
|
||||
STABS_DEBUG
|
||||
.comment 0 : { *(.comment) }
|
||||
|
||||
/* Default discards */
|
||||
DISCARDS
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
|
@ -157,7 +157,7 @@ static struct clk_lookup periph_clocks_lookups[] = {
|
|||
CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk),
|
||||
CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tc0_clk),
|
||||
CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.0", &tc1_clk),
|
||||
CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.0", &tc1_clk),
|
||||
CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.0", &tc2_clk),
|
||||
CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc0_clk),
|
||||
CLKDEV_CON_DEV_ID("pclk", "ssc.1", &ssc1_clk),
|
||||
CLKDEV_CON_DEV_ID("pclk", "ssc.2", &ssc2_clk),
|
||||
|
|
|
@ -8,7 +8,6 @@
|
|||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include <mach/hardware.h>
|
||||
#include <asm/hardware/entry-macro-gic.S>
|
||||
|
||||
.macro disable_fiq
|
||||
|
|
|
@ -13,7 +13,6 @@
|
|||
|
||||
#include <linux/io.h>
|
||||
#include <asm/proc-fns.h>
|
||||
#include <mach/hardware.h>
|
||||
|
||||
static inline void arch_idle(void)
|
||||
{
|
||||
|
|
|
@ -8,7 +8,6 @@
|
|||
*/
|
||||
|
||||
#include <asm/mach-types.h>
|
||||
#include <mach/hardware.h>
|
||||
#include <mach/cns3xxx.h>
|
||||
|
||||
#define AMBA_UART_DR(base) (*(volatile unsigned char *)((base) + 0x00))
|
||||
|
|
|
@ -49,7 +49,7 @@ static struct cns3xxx_pcie *sysdata_to_cnspci(void *sysdata)
|
|||
return &cns3xxx_pcie[root->domain];
|
||||
}
|
||||
|
||||
static struct cns3xxx_pcie *pdev_to_cnspci(struct pci_dev *dev)
|
||||
static struct cns3xxx_pcie *pdev_to_cnspci(const struct pci_dev *dev)
|
||||
{
|
||||
return sysdata_to_cnspci(dev->sysdata);
|
||||
}
|
||||
|
|
|
@ -115,6 +115,32 @@ static struct spi_board_info da850evm_spi_info[] = {
|
|||
},
|
||||
};
|
||||
|
||||
#ifdef CONFIG_MTD
|
||||
static void da850_evm_m25p80_notify_add(struct mtd_info *mtd)
|
||||
{
|
||||
char *mac_addr = davinci_soc_info.emac_pdata->mac_addr;
|
||||
size_t retlen;
|
||||
|
||||
if (!strcmp(mtd->name, "MAC-Address")) {
|
||||
mtd->read(mtd, 0, ETH_ALEN, &retlen, mac_addr);
|
||||
if (retlen == ETH_ALEN)
|
||||
pr_info("Read MAC addr from SPI Flash: %pM\n",
|
||||
mac_addr);
|
||||
}
|
||||
}
|
||||
|
||||
static struct mtd_notifier da850evm_spi_notifier = {
|
||||
.add = da850_evm_m25p80_notify_add,
|
||||
};
|
||||
|
||||
static void da850_evm_setup_mac_addr(void)
|
||||
{
|
||||
register_mtd_user(&da850evm_spi_notifier);
|
||||
}
|
||||
#else
|
||||
static void da850_evm_setup_mac_addr(void) { }
|
||||
#endif
|
||||
|
||||
static struct mtd_partition da850_evm_norflash_partition[] = {
|
||||
{
|
||||
.name = "bootloaders + env",
|
||||
|
@ -1244,6 +1270,8 @@ static __init void da850_evm_init(void)
|
|||
if (ret)
|
||||
pr_warning("da850_evm_init: sata registration failed: %d\n",
|
||||
ret);
|
||||
|
||||
da850_evm_setup_mac_addr();
|
||||
}
|
||||
|
||||
#ifdef CONFIG_SERIAL_8250_CONSOLE
|
||||
|
|
|
@ -243,7 +243,7 @@
|
|||
#define PSC_STATE_DISABLE 2
|
||||
#define PSC_STATE_ENABLE 3
|
||||
|
||||
#define MDSTAT_STATE_MASK 0x1f
|
||||
#define MDSTAT_STATE_MASK 0x3f
|
||||
#define MDCTL_FORCE BIT(31)
|
||||
|
||||
#ifndef __ASSEMBLER__
|
||||
|
|
|
@ -217,7 +217,11 @@ ddr2clk_stop_done:
|
|||
ENDPROC(davinci_ddr_psc_config)
|
||||
|
||||
CACHE_FLUSH:
|
||||
.word arm926_flush_kern_cache_all
|
||||
#ifdef CONFIG_CPU_V6
|
||||
.word v6_flush_kern_cache_all
|
||||
#else
|
||||
.word arm926_flush_kern_cache_all
|
||||
#endif
|
||||
|
||||
ENTRY(davinci_cpu_suspend_sz)
|
||||
.word . - davinci_cpu_suspend
|
||||
|
|
|
@ -158,7 +158,7 @@ void __init dove_spi0_init(void)
|
|||
|
||||
void __init dove_spi1_init(void)
|
||||
{
|
||||
orion_spi_init(DOVE_SPI1_PHYS_BASE, get_tclk());
|
||||
orion_spi_1_init(DOVE_SPI1_PHYS_BASE, get_tclk());
|
||||
}
|
||||
|
||||
/*****************************************************************************
|
||||
|
|
|
@ -6,7 +6,7 @@
|
|||
* TS72xx memory map:
|
||||
*
|
||||
* virt phys size
|
||||
* febff000 22000000 4K model number register
|
||||
* febff000 22000000 4K model number register (bits 0-2)
|
||||
* febfe000 22400000 4K options register
|
||||
* febfd000 22800000 4K options register #2
|
||||
* febf9000 10800000 4K TS-5620 RTC index register
|
||||
|
@ -20,6 +20,9 @@
|
|||
#define TS72XX_MODEL_TS7200 0x00
|
||||
#define TS72XX_MODEL_TS7250 0x01
|
||||
#define TS72XX_MODEL_TS7260 0x02
|
||||
#define TS72XX_MODEL_TS7300 0x03
|
||||
#define TS72XX_MODEL_TS7400 0x04
|
||||
#define TS72XX_MODEL_MASK 0x07
|
||||
|
||||
|
||||
#define TS72XX_OPTIONS_PHYS_BASE 0x22400000
|
||||
|
@ -51,19 +54,34 @@
|
|||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
static inline int ts72xx_model(void)
|
||||
{
|
||||
return __raw_readb(TS72XX_MODEL_VIRT_BASE) & TS72XX_MODEL_MASK;
|
||||
}
|
||||
|
||||
static inline int board_is_ts7200(void)
|
||||
{
|
||||
return __raw_readb(TS72XX_MODEL_VIRT_BASE) == TS72XX_MODEL_TS7200;
|
||||
return ts72xx_model() == TS72XX_MODEL_TS7200;
|
||||
}
|
||||
|
||||
static inline int board_is_ts7250(void)
|
||||
{
|
||||
return __raw_readb(TS72XX_MODEL_VIRT_BASE) == TS72XX_MODEL_TS7250;
|
||||
return ts72xx_model() == TS72XX_MODEL_TS7250;
|
||||
}
|
||||
|
||||
static inline int board_is_ts7260(void)
|
||||
{
|
||||
return __raw_readb(TS72XX_MODEL_VIRT_BASE) == TS72XX_MODEL_TS7260;
|
||||
return ts72xx_model() == TS72XX_MODEL_TS7260;
|
||||
}
|
||||
|
||||
static inline int board_is_ts7300(void)
|
||||
{
|
||||
return ts72xx_model() == TS72XX_MODEL_TS7300;
|
||||
}
|
||||
|
||||
static inline int board_is_ts7400(void)
|
||||
{
|
||||
return ts72xx_model() == TS72XX_MODEL_TS7400;
|
||||
}
|
||||
|
||||
static inline int is_max197_installed(void)
|
||||
|
|
|
@ -520,7 +520,7 @@ static struct clk init_clocks_off[] = {
|
|||
.ctrlbit = (1 << 21),
|
||||
}, {
|
||||
.name = "ac97",
|
||||
.id = -1,
|
||||
.devname = "samsung-ac97",
|
||||
.enable = exynos4_clk_ip_peril_ctrl,
|
||||
.ctrlbit = (1 << 27),
|
||||
}, {
|
||||
|
@ -899,8 +899,7 @@ static struct clksrc_clk clksrcs[] = {
|
|||
.reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 28, .size = 4 },
|
||||
}, {
|
||||
.clk = {
|
||||
.name = "sclk_cam",
|
||||
.devname = "exynos4-fimc.0",
|
||||
.name = "sclk_cam0",
|
||||
.enable = exynos4_clksrc_mask_cam_ctrl,
|
||||
.ctrlbit = (1 << 16),
|
||||
},
|
||||
|
@ -909,8 +908,7 @@ static struct clksrc_clk clksrcs[] = {
|
|||
.reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 16, .size = 4 },
|
||||
}, {
|
||||
.clk = {
|
||||
.name = "sclk_cam",
|
||||
.devname = "exynos4-fimc.1",
|
||||
.name = "sclk_cam1",
|
||||
.enable = exynos4_clksrc_mask_cam_ctrl,
|
||||
.ctrlbit = (1 << 20),
|
||||
},
|
||||
|
@ -1160,7 +1158,7 @@ void __init_or_cpufreq exynos4_setup_clocks(void)
|
|||
|
||||
vpllsrc = clk_get_rate(&clk_vpllsrc.clk);
|
||||
vpll = s5p_get_pll46xx(vpllsrc, __raw_readl(S5P_VPLL_CON0),
|
||||
__raw_readl(S5P_VPLL_CON1), pll_4650);
|
||||
__raw_readl(S5P_VPLL_CON1), pll_4650c);
|
||||
|
||||
clk_fout_apll.ops = &exynos4_fout_apll_ops;
|
||||
clk_fout_mpll.rate = mpll;
|
||||
|
|
|
@ -24,12 +24,13 @@
|
|||
#include <plat/exynos4.h>
|
||||
#include <plat/adc-core.h>
|
||||
#include <plat/sdhci.h>
|
||||
#include <plat/devs.h>
|
||||
#include <plat/fb-core.h>
|
||||
#include <plat/fimc-core.h>
|
||||
#include <plat/iic-core.h>
|
||||
#include <plat/reset.h>
|
||||
|
||||
#include <mach/regs-irq.h>
|
||||
#include <mach/regs-pmu.h>
|
||||
|
||||
extern int combiner_init(unsigned int combiner_nr, void __iomem *base,
|
||||
unsigned int irq_start);
|
||||
|
@ -128,6 +129,11 @@ static void exynos4_idle(void)
|
|||
local_irq_enable();
|
||||
}
|
||||
|
||||
static void exynos4_sw_reset(void)
|
||||
{
|
||||
__raw_writel(0x1, S5P_SWRESET);
|
||||
}
|
||||
|
||||
/*
|
||||
* exynos4_map_io
|
||||
*
|
||||
|
@ -241,5 +247,8 @@ int __init exynos4_init(void)
|
|||
/* set idle function */
|
||||
pm_idle = exynos4_idle;
|
||||
|
||||
/* set sw_reset function */
|
||||
s5p_reset_hook = exynos4_sw_reset;
|
||||
|
||||
return sysdev_register(&exynos4_sysdev);
|
||||
}
|
||||
|
|
|
@ -80,9 +80,8 @@
|
|||
#define IRQ_HSMMC3 IRQ_SPI(76)
|
||||
#define IRQ_DWMCI IRQ_SPI(77)
|
||||
|
||||
#define IRQ_MIPICSI0 IRQ_SPI(78)
|
||||
|
||||
#define IRQ_MIPICSI1 IRQ_SPI(80)
|
||||
#define IRQ_MIPI_CSIS0 IRQ_SPI(78)
|
||||
#define IRQ_MIPI_CSIS1 IRQ_SPI(80)
|
||||
|
||||
#define IRQ_ONENAND_AUDI IRQ_SPI(82)
|
||||
#define IRQ_ROTATOR IRQ_SPI(83)
|
||||
|
|
|
@ -29,6 +29,8 @@
|
|||
#define S5P_USE_STANDBY_WFE1 (1 << 25)
|
||||
#define S5P_USE_MASK ((0x3 << 16) | (0x3 << 24))
|
||||
|
||||
#define S5P_SWRESET S5P_PMUREG(0x0400)
|
||||
|
||||
#define S5P_WAKEUP_STAT S5P_PMUREG(0x0600)
|
||||
#define S5P_EINT_WAKEUP_MASK S5P_PMUREG(0x0604)
|
||||
#define S5P_WAKEUP_MASK S5P_PMUREG(0x0608)
|
||||
|
|
|
@ -23,6 +23,8 @@
|
|||
|
||||
#include <mach/regs-gpio.h>
|
||||
|
||||
#include <asm/mach/irq.h>
|
||||
|
||||
static DEFINE_SPINLOCK(eint_lock);
|
||||
|
||||
static unsigned int eint0_15_data[16];
|
||||
|
@ -184,8 +186,11 @@ static inline void exynos4_irq_demux_eint(unsigned int start)
|
|||
|
||||
static void exynos4_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc)
|
||||
{
|
||||
struct irq_chip *chip = irq_get_chip(irq);
|
||||
chained_irq_enter(chip, desc);
|
||||
exynos4_irq_demux_eint(IRQ_EINT(16));
|
||||
exynos4_irq_demux_eint(IRQ_EINT(24));
|
||||
chained_irq_exit(chip, desc);
|
||||
}
|
||||
|
||||
static void exynos4_irq_eint0_15(unsigned int irq, struct irq_desc *desc)
|
||||
|
@ -193,6 +198,7 @@ static void exynos4_irq_eint0_15(unsigned int irq, struct irq_desc *desc)
|
|||
u32 *irq_data = irq_get_handler_data(irq);
|
||||
struct irq_chip *chip = irq_get_chip(irq);
|
||||
|
||||
chained_irq_enter(chip, desc);
|
||||
chip->irq_mask(&desc->irq_data);
|
||||
|
||||
if (chip->irq_ack)
|
||||
|
@ -201,6 +207,7 @@ static void exynos4_irq_eint0_15(unsigned int irq, struct irq_desc *desc)
|
|||
generic_handle_irq(*irq_data);
|
||||
|
||||
chip->irq_unmask(&desc->irq_data);
|
||||
chained_irq_exit(chip, desc);
|
||||
}
|
||||
|
||||
int __init exynos4_init_irq_eint(void)
|
||||
|
|
|
@ -79,7 +79,7 @@ static struct s3c2410_uartcfg universal_uartcfgs[] __initdata = {
|
|||
};
|
||||
|
||||
static struct regulator_consumer_supply max8952_consumer =
|
||||
REGULATOR_SUPPLY("vddarm", NULL);
|
||||
REGULATOR_SUPPLY("vdd_arm", NULL);
|
||||
|
||||
static struct max8952_platform_data universal_max8952_pdata __initdata = {
|
||||
.gpio_vid0 = EXYNOS4_GPX0(3),
|
||||
|
@ -105,7 +105,7 @@ static struct max8952_platform_data universal_max8952_pdata __initdata = {
|
|||
};
|
||||
|
||||
static struct regulator_consumer_supply lp3974_buck1_consumer =
|
||||
REGULATOR_SUPPLY("vddint", NULL);
|
||||
REGULATOR_SUPPLY("vdd_int", NULL);
|
||||
|
||||
static struct regulator_consumer_supply lp3974_buck2_consumer =
|
||||
REGULATOR_SUPPLY("vddg3d", NULL);
|
||||
|
|
|
@ -132,12 +132,18 @@ static cycle_t exynos4_frc_read(struct clocksource *cs)
|
|||
return ((cycle_t)hi << 32) | lo;
|
||||
}
|
||||
|
||||
static void exynos4_frc_resume(struct clocksource *cs)
|
||||
{
|
||||
exynos4_mct_frc_start(0, 0);
|
||||
}
|
||||
|
||||
struct clocksource mct_frc = {
|
||||
.name = "mct-frc",
|
||||
.rating = 400,
|
||||
.read = exynos4_frc_read,
|
||||
.mask = CLOCKSOURCE_MASK(64),
|
||||
.flags = CLOCK_SOURCE_IS_CONTINUOUS,
|
||||
.resume = exynos4_frc_resume,
|
||||
};
|
||||
|
||||
static void __init exynos4_clocksource_init(void)
|
||||
|
@ -389,9 +395,11 @@ static void exynos4_mct_tick_init(struct clock_event_device *evt)
|
|||
}
|
||||
|
||||
/* Setup the local clock events for a CPU */
|
||||
void __cpuinit local_timer_setup(struct clock_event_device *evt)
|
||||
int __cpuinit local_timer_setup(struct clock_event_device *evt)
|
||||
{
|
||||
exynos4_mct_tick_init(evt);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int local_timer_ack(void)
|
||||
|
|
|
@ -106,6 +106,8 @@ void __cpuinit platform_secondary_init(unsigned int cpu)
|
|||
*/
|
||||
spin_lock(&boot_lock);
|
||||
spin_unlock(&boot_lock);
|
||||
|
||||
set_cpu_online(cpu, true);
|
||||
}
|
||||
|
||||
int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
|
||||
|
|
|
@ -19,15 +19,16 @@ void samsung_keypad_cfg_gpio(unsigned int rows, unsigned int cols)
|
|||
|
||||
if (rows > 8) {
|
||||
/* Set all the necessary GPX2 pins: KP_ROW[0~7] */
|
||||
s3c_gpio_cfgrange_nopull(EXYNOS4_GPX2(0), 8, S3C_GPIO_SFN(3));
|
||||
s3c_gpio_cfgall_range(EXYNOS4_GPX2(0), 8, S3C_GPIO_SFN(3),
|
||||
S3C_GPIO_PULL_UP);
|
||||
|
||||
/* Set all the necessary GPX3 pins: KP_ROW[8~] */
|
||||
s3c_gpio_cfgrange_nopull(EXYNOS4_GPX3(0), (rows - 8),
|
||||
S3C_GPIO_SFN(3));
|
||||
s3c_gpio_cfgall_range(EXYNOS4_GPX3(0), (rows - 8),
|
||||
S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP);
|
||||
} else {
|
||||
/* Set all the necessary GPX2 pins: KP_ROW[x] */
|
||||
s3c_gpio_cfgrange_nopull(EXYNOS4_GPX2(0), rows,
|
||||
S3C_GPIO_SFN(3));
|
||||
s3c_gpio_cfgall_range(EXYNOS4_GPX2(0), rows, S3C_GPIO_SFN(3),
|
||||
S3C_GPIO_PULL_UP);
|
||||
}
|
||||
|
||||
/* Set all the necessary GPX1 pins to special-function 3: KP_COL[x] */
|
||||
|
|
|
@ -82,7 +82,7 @@ static int exynos4_usb_phy1_init(struct platform_device *pdev)
|
|||
|
||||
rstcon &= ~(HOST_LINK_PORT_SWRST_MASK | PHY1_SWRST_MASK);
|
||||
writel(rstcon, EXYNOS4_RSTCON);
|
||||
udelay(50);
|
||||
udelay(80);
|
||||
|
||||
clk_disable(otg_clk);
|
||||
clk_put(otg_clk);
|
||||
|
|
|
@ -62,6 +62,7 @@ config ARCH_EBSA285_HOST
|
|||
config ARCH_NETWINDER
|
||||
bool "NetWinder"
|
||||
select CLKSRC_I8253
|
||||
select CLKEVT_I8253
|
||||
select FOOTBRIDGE_HOST
|
||||
select ISA
|
||||
select ISA_DMA
|
||||
|
|
|
@ -18,6 +18,7 @@
|
|||
#include <linux/irq.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/spinlock.h>
|
||||
#include <video/vga.h>
|
||||
|
||||
#include <asm/irq.h>
|
||||
#include <asm/system.h>
|
||||
|
|
|
@ -310,7 +310,7 @@ static struct sys_timer eukrea_cpuimx27_timer = {
|
|||
.init = eukrea_cpuimx27_timer_init,
|
||||
};
|
||||
|
||||
MACHINE_START(CPUIMX27, "EUKREA CPUIMX27")
|
||||
MACHINE_START(EUKREA_CPUIMX27, "EUKREA CPUIMX27")
|
||||
.boot_params = MX27_PHYS_OFFSET + 0x100,
|
||||
.map_io = mx27_map_io,
|
||||
.init_early = imx27_init_early,
|
||||
|
|
|
@ -192,7 +192,7 @@ struct sys_timer eukrea_cpuimx35_timer = {
|
|||
.init = eukrea_cpuimx35_timer_init,
|
||||
};
|
||||
|
||||
MACHINE_START(EUKREA_CPUIMX35, "Eukrea CPUIMX35")
|
||||
MACHINE_START(EUKREA_CPUIMX35SD, "Eukrea CPUIMX35")
|
||||
/* Maintainer: Eukrea Electromatique */
|
||||
.boot_params = MX3x_PHYS_OFFSET + 0x100,
|
||||
.map_io = mx35_map_io,
|
||||
|
|
|
@ -161,7 +161,7 @@ static struct sys_timer eukrea_cpuimx25_timer = {
|
|||
.init = eukrea_cpuimx25_timer_init,
|
||||
};
|
||||
|
||||
MACHINE_START(EUKREA_CPUIMX25, "Eukrea CPUIMX25")
|
||||
MACHINE_START(EUKREA_CPUIMX25SD, "Eukrea CPUIMX25")
|
||||
/* Maintainer: Eukrea Electromatique */
|
||||
.boot_params = MX25_PHYS_OFFSET + 0x100,
|
||||
.map_io = mx25_map_io,
|
||||
|
|
|
@ -32,6 +32,7 @@
|
|||
#include <linux/interrupt.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/mtd/physmap.h>
|
||||
#include <video/vga.h>
|
||||
|
||||
#include <mach/hardware.h>
|
||||
#include <mach/platform.h>
|
||||
|
@ -154,6 +155,7 @@ static struct map_desc ap_io_desc[] __initdata = {
|
|||
static void __init ap_map_io(void)
|
||||
{
|
||||
iotable_init(ap_io_desc, ARRAY_SIZE(ap_io_desc));
|
||||
vga_base = PCI_MEMORY_VADDR;
|
||||
}
|
||||
|
||||
#define INTEGRATOR_SC_VALID_INT 0x003fffff
|
||||
|
@ -337,15 +339,15 @@ static unsigned long timer_reload;
|
|||
static void integrator_clocksource_init(u32 khz)
|
||||
{
|
||||
void __iomem *base = (void __iomem *)TIMER2_VA_BASE;
|
||||
u32 ctrl = TIMER_CTRL_ENABLE;
|
||||
u32 ctrl = TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC;
|
||||
|
||||
if (khz >= 1500) {
|
||||
khz /= 16;
|
||||
ctrl = TIMER_CTRL_DIV16;
|
||||
ctrl |= TIMER_CTRL_DIV16;
|
||||
}
|
||||
|
||||
writel(ctrl, base + TIMER_CTRL);
|
||||
writel(0xffff, base + TIMER_LOAD);
|
||||
writel(ctrl, base + TIMER_CTRL);
|
||||
|
||||
clocksource_mmio_init(base + TIMER_VALUE, "timer2",
|
||||
khz * 1000, 200, 16, clocksource_mmio_readl_down);
|
||||
|
|
|
@ -27,7 +27,6 @@
|
|||
#include <linux/spinlock.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/io.h>
|
||||
#include <video/vga.h>
|
||||
|
||||
#include <mach/hardware.h>
|
||||
#include <mach/platform.h>
|
||||
|
@ -505,7 +504,6 @@ void __init pci_v3_preinit(void)
|
|||
|
||||
pcibios_min_io = 0x6000;
|
||||
pcibios_min_mem = 0x00100000;
|
||||
vga_base = PCI_MEMORY_VADDR;
|
||||
|
||||
/*
|
||||
* Hook in our fault handler for PCI errors
|
||||
|
|
|
@ -234,6 +234,7 @@ static void __init mx53_ard_board_init(void)
|
|||
imx53_add_imx_i2c(1, &mx53_ard_i2c2_data);
|
||||
imx53_add_imx_i2c(2, &mx53_ard_i2c3_data);
|
||||
imx_add_gpio_keys(&ard_button_data);
|
||||
imx53_add_ahci_imx();
|
||||
}
|
||||
|
||||
static void __init mx53_ard_timer_init(void)
|
||||
|
|
|
@ -293,6 +293,7 @@ static void __init mx53_loco_board_init(void)
|
|||
imx53_add_sdhci_esdhc_imx(2, &mx53_loco_sd3_data);
|
||||
imx_add_gpio_keys(&loco_button_data);
|
||||
gpio_led_register_device(-1, &mx53loco_leds_data);
|
||||
imx53_add_ahci_imx();
|
||||
}
|
||||
|
||||
static void __init mx53_loco_timer_init(void)
|
||||
|
|
|
@ -35,6 +35,7 @@
|
|||
#include "devices-imx53.h"
|
||||
|
||||
#define SMD_FEC_PHY_RST IMX_GPIO_NR(7, 6)
|
||||
#define MX53_SMD_SATA_PWR_EN IMX_GPIO_NR(3, 3)
|
||||
|
||||
static iomux_v3_cfg_t mx53_smd_pads[] = {
|
||||
MX53_PAD_CSI0_DAT10__UART1_TXD_MUX,
|
||||
|
@ -111,6 +112,19 @@ static const struct imxi2c_platform_data mx53_smd_i2c_data __initconst = {
|
|||
.bitrate = 100000,
|
||||
};
|
||||
|
||||
static inline void mx53_smd_ahci_pwr_on(void)
|
||||
{
|
||||
int ret;
|
||||
|
||||
/* Enable SATA PWR */
|
||||
ret = gpio_request_one(MX53_SMD_SATA_PWR_EN,
|
||||
GPIOF_DIR_OUT | GPIOF_INIT_HIGH, "ahci-sata-pwr");
|
||||
if (ret) {
|
||||
pr_err("failed to enable SATA_PWR_EN: %d\n", ret);
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
static void __init mx53_smd_board_init(void)
|
||||
{
|
||||
imx53_soc_init();
|
||||
|
@ -125,6 +139,8 @@ static void __init mx53_smd_board_init(void)
|
|||
imx53_add_sdhci_esdhc_imx(0, NULL);
|
||||
imx53_add_sdhci_esdhc_imx(1, NULL);
|
||||
imx53_add_sdhci_esdhc_imx(2, NULL);
|
||||
mx53_smd_ahci_pwr_on();
|
||||
imx53_add_ahci_imx();
|
||||
}
|
||||
|
||||
static void __init mx53_smd_timer_init(void)
|
||||
|
|
|
@ -1401,6 +1401,22 @@ static struct clk esdhc4_mx53_clk = {
|
|||
.secondary = &esdhc4_ipg_clk,
|
||||
};
|
||||
|
||||
static struct clk sata_clk = {
|
||||
.parent = &ipg_clk,
|
||||
.enable = _clk_max_enable,
|
||||
.enable_reg = MXC_CCM_CCGR4,
|
||||
.enable_shift = MXC_CCM_CCGRx_CG1_OFFSET,
|
||||
.disable = _clk_max_disable,
|
||||
};
|
||||
|
||||
static struct clk ahci_phy_clk = {
|
||||
.parent = &usb_phy1_clk,
|
||||
};
|
||||
|
||||
static struct clk ahci_dma_clk = {
|
||||
.parent = &ahb_clk,
|
||||
};
|
||||
|
||||
DEFINE_CLOCK(mipi_esc_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG5_OFFSET, NULL, NULL, NULL, &pll2_sw_clk);
|
||||
DEFINE_CLOCK(mipi_hsc2_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG4_OFFSET, NULL, NULL, &mipi_esc_clk, &pll2_sw_clk);
|
||||
DEFINE_CLOCK(mipi_hsc1_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG3_OFFSET, NULL, NULL, &mipi_hsc2_clk, &pll2_sw_clk);
|
||||
|
@ -1513,6 +1529,9 @@ static struct clk_lookup mx53_lookups[] = {
|
|||
_REGISTER_CLOCK("imx-ssi.2", NULL, ssi3_clk)
|
||||
_REGISTER_CLOCK("imx-keypad", NULL, dummy_clk)
|
||||
_REGISTER_CLOCK("pata_imx", NULL, pata_clk)
|
||||
_REGISTER_CLOCK("imx53-ahci.0", "ahci", sata_clk)
|
||||
_REGISTER_CLOCK("imx53-ahci.0", "ahci_phy", ahci_phy_clk)
|
||||
_REGISTER_CLOCK("imx53-ahci.0", "ahci_dma", ahci_dma_clk)
|
||||
};
|
||||
|
||||
static void clk_tree_init(void)
|
||||
|
|
|
@ -44,3 +44,5 @@ extern const struct imx_imx_keypad_data imx53_imx_keypad_data;
|
|||
extern const struct imx_pata_imx_data imx53_pata_imx_data;
|
||||
#define imx53_add_pata_imx() \
|
||||
imx_add_pata_imx(&imx53_pata_imx_data)
|
||||
|
||||
extern struct platform_device *__init imx53_add_ahci_imx(void);
|
||||
|
|
|
@ -70,8 +70,25 @@ config MODULE_TX28
|
|||
select MXS_HAVE_PLATFORM_MXS_PWM
|
||||
select MXS_HAVE_PLATFORM_RTC_STMP3XXX
|
||||
|
||||
config MODULE_M28
|
||||
bool
|
||||
select SOC_IMX28
|
||||
select LEDS_GPIO_REGISTER
|
||||
select MXS_HAVE_AMBA_DUART
|
||||
select MXS_HAVE_PLATFORM_AUART
|
||||
select MXS_HAVE_PLATFORM_FEC
|
||||
select MXS_HAVE_PLATFORM_FLEXCAN
|
||||
select MXS_HAVE_PLATFORM_MXS_I2C
|
||||
select MXS_HAVE_PLATFORM_MXS_MMC
|
||||
select MXS_HAVE_PLATFORM_MXSFB
|
||||
select MXS_OCOTP
|
||||
|
||||
config MACH_TX28
|
||||
bool "Ka-Ro TX28 module"
|
||||
select MODULE_TX28
|
||||
|
||||
config MACH_M28EVK
|
||||
bool "Support DENX M28EVK Platform"
|
||||
select MODULE_M28
|
||||
|
||||
endif
|
||||
|
|
|
@ -10,6 +10,7 @@ obj-$(CONFIG_SOC_IMX28) += clock-mx28.o
|
|||
obj-$(CONFIG_MACH_STMP378X_DEVB) += mach-stmp378x_devb.o
|
||||
obj-$(CONFIG_MACH_MX23EVK) += mach-mx23evk.o
|
||||
obj-$(CONFIG_MACH_MX28EVK) += mach-mx28evk.o
|
||||
obj-$(CONFIG_MACH_M28EVK) += mach-m28evk.o
|
||||
obj-$(CONFIG_MODULE_TX28) += module-tx28.o
|
||||
obj-$(CONFIG_MACH_TX28) += mach-tx28.o
|
||||
|
||||
|
|
|
@ -740,11 +740,17 @@ static int clk_misc_init(void)
|
|||
__raw_writel(BM_CLKCTRL_CPU_INTERRUPT_WAIT,
|
||||
CLKCTRL_BASE_ADDR + HW_CLKCTRL_CPU_SET);
|
||||
|
||||
/* Extra fec clock setting */
|
||||
reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_ENET);
|
||||
reg &= ~BM_CLKCTRL_ENET_SLEEP;
|
||||
reg |= BM_CLKCTRL_ENET_CLK_OUT_EN;
|
||||
__raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_ENET);
|
||||
/*
|
||||
* Extra fec clock setting
|
||||
* The DENX M28 uses an external clock source
|
||||
* and the clock output must not be enabled
|
||||
*/
|
||||
if (!machine_is_m28evk()) {
|
||||
reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_ENET);
|
||||
reg &= ~BM_CLKCTRL_ENET_SLEEP;
|
||||
reg |= BM_CLKCTRL_ENET_CLK_OUT_EN;
|
||||
__raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_ENET);
|
||||
}
|
||||
|
||||
/*
|
||||
* 480 MHz seems too high to be ssp clock source directly,
|
||||
|
|
|
@ -33,6 +33,7 @@
|
|||
0)
|
||||
#define cpu_is_mx28() ( \
|
||||
machine_is_mx28evk() || \
|
||||
machine_is_m28evk() || \
|
||||
machine_is_tx28() || \
|
||||
0)
|
||||
|
||||
|
|
|
@ -63,6 +63,7 @@ static inline void __arch_decomp_setup(unsigned long arch_id)
|
|||
mxs_duart_base = MX23_DUART_BASE_ADDR;
|
||||
break;
|
||||
case MACH_TYPE_MX28EVK:
|
||||
case MACH_TYPE_M28EVK:
|
||||
case MACH_TYPE_TX28:
|
||||
mxs_duart_base = MX28_DUART_BASE_ADDR;
|
||||
break;
|
||||
|
|
366
arch/arm/mach-mxs/mach-m28evk.c
Normal file
366
arch/arm/mach-mxs/mach-m28evk.c
Normal file
|
@ -0,0 +1,366 @@
|
|||
/*
|
||||
* Copyright (C) 2011
|
||||
* Stefano Babic, DENX Software Engineering, <sbabic@denx.de>
|
||||
*
|
||||
* based on: mach-mx28_evk.c
|
||||
* Copyright 2010 Freescale Semiconductor, Inc. All Rights Reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <linux/delay.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/gpio.h>
|
||||
#include <linux/leds.h>
|
||||
#include <linux/irq.h>
|
||||
#include <linux/clk.h>
|
||||
#include <linux/i2c.h>
|
||||
#include <linux/i2c/at24.h>
|
||||
|
||||
#include <asm/mach-types.h>
|
||||
#include <asm/mach/arch.h>
|
||||
#include <asm/mach/time.h>
|
||||
|
||||
#include <mach/common.h>
|
||||
#include <mach/iomux-mx28.h>
|
||||
|
||||
#include "devices-mx28.h"
|
||||
|
||||
#define M28EVK_GPIO_USERLED1 MXS_GPIO_NR(3, 16)
|
||||
#define M28EVK_GPIO_USERLED2 MXS_GPIO_NR(3, 17)
|
||||
|
||||
#define MX28EVK_BL_ENABLE MXS_GPIO_NR(3, 18)
|
||||
#define M28EVK_LCD_ENABLE MXS_GPIO_NR(3, 28)
|
||||
|
||||
#define MX28EVK_MMC0_WRITE_PROTECT MXS_GPIO_NR(2, 12)
|
||||
#define MX28EVK_MMC1_WRITE_PROTECT MXS_GPIO_NR(0, 28)
|
||||
|
||||
static const iomux_cfg_t m28evk_pads[] __initconst = {
|
||||
/* duart */
|
||||
MX28_PAD_AUART0_CTS__DUART_RX | MXS_PAD_CTRL,
|
||||
MX28_PAD_AUART0_RTS__DUART_TX | MXS_PAD_CTRL,
|
||||
|
||||
/* auart0 */
|
||||
MX28_PAD_AUART0_RX__AUART0_RX | MXS_PAD_CTRL,
|
||||
MX28_PAD_AUART0_TX__AUART0_TX | MXS_PAD_CTRL,
|
||||
|
||||
/* auart3 */
|
||||
MX28_PAD_AUART3_RX__AUART3_RX | MXS_PAD_CTRL,
|
||||
MX28_PAD_AUART3_TX__AUART3_TX | MXS_PAD_CTRL,
|
||||
MX28_PAD_AUART3_CTS__AUART3_CTS | MXS_PAD_CTRL,
|
||||
MX28_PAD_AUART3_RTS__AUART3_RTS | MXS_PAD_CTRL,
|
||||
|
||||
#define MXS_PAD_FEC (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP)
|
||||
/* fec0 */
|
||||
MX28_PAD_ENET0_MDC__ENET0_MDC | MXS_PAD_FEC,
|
||||
MX28_PAD_ENET0_MDIO__ENET0_MDIO | MXS_PAD_FEC,
|
||||
MX28_PAD_ENET0_RX_EN__ENET0_RX_EN | MXS_PAD_FEC,
|
||||
MX28_PAD_ENET0_RXD0__ENET0_RXD0 | MXS_PAD_FEC,
|
||||
MX28_PAD_ENET0_RXD1__ENET0_RXD1 | MXS_PAD_FEC,
|
||||
MX28_PAD_ENET0_TX_EN__ENET0_TX_EN | MXS_PAD_FEC,
|
||||
MX28_PAD_ENET0_TXD0__ENET0_TXD0 | MXS_PAD_FEC,
|
||||
MX28_PAD_ENET0_TXD1__ENET0_TXD1 | MXS_PAD_FEC,
|
||||
MX28_PAD_ENET_CLK__CLKCTRL_ENET | MXS_PAD_FEC,
|
||||
/* fec1 */
|
||||
MX28_PAD_ENET0_CRS__ENET1_RX_EN | MXS_PAD_FEC,
|
||||
MX28_PAD_ENET0_RXD2__ENET1_RXD0 | MXS_PAD_FEC,
|
||||
MX28_PAD_ENET0_RXD3__ENET1_RXD1 | MXS_PAD_FEC,
|
||||
MX28_PAD_ENET0_COL__ENET1_TX_EN | MXS_PAD_FEC,
|
||||
MX28_PAD_ENET0_TXD2__ENET1_TXD0 | MXS_PAD_FEC,
|
||||
MX28_PAD_ENET0_TXD3__ENET1_TXD1 | MXS_PAD_FEC,
|
||||
|
||||
/* flexcan0 */
|
||||
MX28_PAD_GPMI_RDY2__CAN0_TX,
|
||||
MX28_PAD_GPMI_RDY3__CAN0_RX,
|
||||
|
||||
/* flexcan1 */
|
||||
MX28_PAD_GPMI_CE2N__CAN1_TX,
|
||||
MX28_PAD_GPMI_CE3N__CAN1_RX,
|
||||
|
||||
/* I2C */
|
||||
MX28_PAD_I2C0_SCL__I2C0_SCL,
|
||||
MX28_PAD_I2C0_SDA__I2C0_SDA,
|
||||
|
||||
/* mxsfb (lcdif) */
|
||||
MX28_PAD_LCD_D00__LCD_D0 | MXS_PAD_CTRL,
|
||||
MX28_PAD_LCD_D01__LCD_D1 | MXS_PAD_CTRL,
|
||||
MX28_PAD_LCD_D02__LCD_D2 | MXS_PAD_CTRL,
|
||||
MX28_PAD_LCD_D03__LCD_D3 | MXS_PAD_CTRL,
|
||||
MX28_PAD_LCD_D04__LCD_D4 | MXS_PAD_CTRL,
|
||||
MX28_PAD_LCD_D05__LCD_D5 | MXS_PAD_CTRL,
|
||||
MX28_PAD_LCD_D06__LCD_D6 | MXS_PAD_CTRL,
|
||||
MX28_PAD_LCD_D07__LCD_D7 | MXS_PAD_CTRL,
|
||||
MX28_PAD_LCD_D08__LCD_D8 | MXS_PAD_CTRL,
|
||||
MX28_PAD_LCD_D09__LCD_D9 | MXS_PAD_CTRL,
|
||||
MX28_PAD_LCD_D10__LCD_D10 | MXS_PAD_CTRL,
|
||||
MX28_PAD_LCD_D11__LCD_D11 | MXS_PAD_CTRL,
|
||||
MX28_PAD_LCD_D12__LCD_D12 | MXS_PAD_CTRL,
|
||||
MX28_PAD_LCD_D13__LCD_D13 | MXS_PAD_CTRL,
|
||||
MX28_PAD_LCD_D14__LCD_D14 | MXS_PAD_CTRL,
|
||||
MX28_PAD_LCD_D15__LCD_D15 | MXS_PAD_CTRL,
|
||||
MX28_PAD_LCD_D16__LCD_D16 | MXS_PAD_CTRL,
|
||||
MX28_PAD_LCD_D17__LCD_D17 | MXS_PAD_CTRL,
|
||||
MX28_PAD_LCD_D18__LCD_D18 | MXS_PAD_CTRL,
|
||||
MX28_PAD_LCD_D19__LCD_D19 | MXS_PAD_CTRL,
|
||||
MX28_PAD_LCD_D20__LCD_D20 | MXS_PAD_CTRL,
|
||||
MX28_PAD_LCD_D21__LCD_D21 | MXS_PAD_CTRL,
|
||||
MX28_PAD_LCD_D22__LCD_D22 | MXS_PAD_CTRL,
|
||||
MX28_PAD_LCD_D23__LCD_D23 | MXS_PAD_CTRL,
|
||||
|
||||
MX28_PAD_LCD_ENABLE__LCD_ENABLE | MXS_PAD_CTRL,
|
||||
MX28_PAD_LCD_DOTCLK__LCD_DOTCLK | MXS_PAD_CTRL,
|
||||
|
||||
/* mmc0 */
|
||||
MX28_PAD_SSP0_DATA0__SSP0_D0 |
|
||||
(MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
|
||||
MX28_PAD_SSP0_DATA1__SSP0_D1 |
|
||||
(MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
|
||||
MX28_PAD_SSP0_DATA2__SSP0_D2 |
|
||||
(MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
|
||||
MX28_PAD_SSP0_DATA3__SSP0_D3 |
|
||||
(MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
|
||||
MX28_PAD_SSP0_DATA4__SSP0_D4 |
|
||||
(MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
|
||||
MX28_PAD_SSP0_DATA5__SSP0_D5 |
|
||||
(MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
|
||||
MX28_PAD_SSP0_DATA6__SSP0_D6 |
|
||||
(MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
|
||||
MX28_PAD_SSP0_DATA7__SSP0_D7 |
|
||||
(MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
|
||||
MX28_PAD_SSP0_CMD__SSP0_CMD |
|
||||
(MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
|
||||
MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT |
|
||||
(MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
|
||||
MX28_PAD_SSP0_SCK__SSP0_SCK |
|
||||
(MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
|
||||
|
||||
/* mmc1 */
|
||||
MX28_PAD_GPMI_D00__SSP1_D0 |
|
||||
(MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
|
||||
MX28_PAD_GPMI_D01__SSP1_D1 |
|
||||
(MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
|
||||
MX28_PAD_GPMI_D02__SSP1_D2 |
|
||||
(MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
|
||||
MX28_PAD_GPMI_D03__SSP1_D3 |
|
||||
(MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
|
||||
MX28_PAD_GPMI_D04__SSP1_D4 |
|
||||
(MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
|
||||
MX28_PAD_GPMI_D05__SSP1_D5 |
|
||||
(MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
|
||||
MX28_PAD_GPMI_D06__SSP1_D6 |
|
||||
(MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
|
||||
MX28_PAD_GPMI_D07__SSP1_D7 |
|
||||
(MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
|
||||
MX28_PAD_GPMI_RDY1__SSP1_CMD |
|
||||
(MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
|
||||
MX28_PAD_GPMI_RDY0__SSP1_CARD_DETECT |
|
||||
(MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
|
||||
MX28_PAD_GPMI_WRN__SSP1_SCK |
|
||||
(MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
|
||||
/* write protect */
|
||||
MX28_PAD_GPMI_RESETN__GPIO_0_28 |
|
||||
(MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
|
||||
/* slot power enable */
|
||||
MX28_PAD_PWM4__GPIO_3_29 |
|
||||
(MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
|
||||
|
||||
/* led */
|
||||
MX28_PAD_PWM0__GPIO_3_16 | MXS_PAD_CTRL,
|
||||
MX28_PAD_PWM1__GPIO_3_17 | MXS_PAD_CTRL,
|
||||
|
||||
/* nand */
|
||||
MX28_PAD_GPMI_D00__GPMI_D0 |
|
||||
(MXS_PAD_4MA | MXS_PAD_1V8 | MXS_PAD_NOPULL),
|
||||
MX28_PAD_GPMI_D01__GPMI_D1 |
|
||||
(MXS_PAD_4MA | MXS_PAD_1V8 | MXS_PAD_NOPULL),
|
||||
MX28_PAD_GPMI_D02__GPMI_D2 |
|
||||
(MXS_PAD_4MA | MXS_PAD_1V8 | MXS_PAD_NOPULL),
|
||||
MX28_PAD_GPMI_D03__GPMI_D3 |
|
||||
(MXS_PAD_4MA | MXS_PAD_1V8 | MXS_PAD_NOPULL),
|
||||
MX28_PAD_GPMI_D04__GPMI_D4 |
|
||||
(MXS_PAD_4MA | MXS_PAD_1V8 | MXS_PAD_NOPULL),
|
||||
MX28_PAD_GPMI_D05__GPMI_D5 |
|
||||
(MXS_PAD_4MA | MXS_PAD_1V8 | MXS_PAD_NOPULL),
|
||||
MX28_PAD_GPMI_D06__GPMI_D6 |
|
||||
(MXS_PAD_4MA | MXS_PAD_1V8 | MXS_PAD_NOPULL),
|
||||
MX28_PAD_GPMI_D07__GPMI_D7 |
|
||||
(MXS_PAD_4MA | MXS_PAD_1V8 | MXS_PAD_NOPULL),
|
||||
MX28_PAD_GPMI_CE0N__GPMI_CE0N |
|
||||
(MXS_PAD_4MA | MXS_PAD_1V8 | MXS_PAD_NOPULL),
|
||||
MX28_PAD_GPMI_RDY0__GPMI_READY0 |
|
||||
(MXS_PAD_4MA | MXS_PAD_1V8 | MXS_PAD_NOPULL),
|
||||
MX28_PAD_GPMI_RDN__GPMI_RDN |
|
||||
(MXS_PAD_12MA | MXS_PAD_1V8 | MXS_PAD_PULLUP),
|
||||
MX28_PAD_GPMI_WRN__GPMI_WRN |
|
||||
(MXS_PAD_12MA | MXS_PAD_1V8 | MXS_PAD_PULLUP),
|
||||
MX28_PAD_GPMI_ALE__GPMI_ALE |
|
||||
(MXS_PAD_4MA | MXS_PAD_1V8 | MXS_PAD_PULLUP),
|
||||
MX28_PAD_GPMI_CLE__GPMI_CLE |
|
||||
(MXS_PAD_4MA | MXS_PAD_1V8 | MXS_PAD_PULLUP),
|
||||
MX28_PAD_GPMI_RESETN__GPMI_RESETN |
|
||||
(MXS_PAD_12MA | MXS_PAD_1V8 | MXS_PAD_PULLUP),
|
||||
|
||||
/* Backlight */
|
||||
MX28_PAD_PWM3__GPIO_3_28 | MXS_PAD_CTRL,
|
||||
};
|
||||
|
||||
/* led */
|
||||
static const struct gpio_led m28evk_leds[] __initconst = {
|
||||
{
|
||||
.name = "user-led1",
|
||||
.default_trigger = "heartbeat",
|
||||
.gpio = M28EVK_GPIO_USERLED1,
|
||||
},
|
||||
{
|
||||
.name = "user-led2",
|
||||
.default_trigger = "heartbeat",
|
||||
.gpio = M28EVK_GPIO_USERLED2,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct gpio_led_platform_data m28evk_led_data __initconst = {
|
||||
.leds = m28evk_leds,
|
||||
.num_leds = ARRAY_SIZE(m28evk_leds),
|
||||
};
|
||||
|
||||
static struct fec_platform_data mx28_fec_pdata[] __initdata = {
|
||||
{
|
||||
/* fec0 */
|
||||
.phy = PHY_INTERFACE_MODE_RMII,
|
||||
}, {
|
||||
/* fec1 */
|
||||
.phy = PHY_INTERFACE_MODE_RMII,
|
||||
},
|
||||
};
|
||||
|
||||
static int __init m28evk_fec_get_mac(void)
|
||||
{
|
||||
int i;
|
||||
u32 val;
|
||||
const u32 *ocotp = mxs_get_ocotp();
|
||||
|
||||
if (!ocotp) {
|
||||
pr_err("%s: timeout when reading fec mac from OCOTP\n",
|
||||
__func__);
|
||||
return -ETIMEDOUT;
|
||||
}
|
||||
|
||||
/*
|
||||
* OCOTP only stores the last 4 octets for each mac address,
|
||||
* so hard-code DENX OUI (C0:E5:4E) here.
|
||||
*/
|
||||
for (i = 0; i < 2; i++) {
|
||||
val = ocotp[i * 4];
|
||||
mx28_fec_pdata[i].mac[0] = 0xC0;
|
||||
mx28_fec_pdata[i].mac[1] = 0xE5;
|
||||
mx28_fec_pdata[i].mac[2] = 0x4E;
|
||||
mx28_fec_pdata[i].mac[3] = (val >> 16) & 0xff;
|
||||
mx28_fec_pdata[i].mac[4] = (val >> 8) & 0xff;
|
||||
mx28_fec_pdata[i].mac[5] = (val >> 0) & 0xff;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* mxsfb (lcdif) */
|
||||
static struct fb_videomode m28evk_video_modes[] = {
|
||||
{
|
||||
.name = "Ampire AM-800480R2TMQW-T01H",
|
||||
.refresh = 60,
|
||||
.xres = 800,
|
||||
.yres = 480,
|
||||
.pixclock = 30066, /* picosecond (33.26 MHz) */
|
||||
.left_margin = 0,
|
||||
.right_margin = 256,
|
||||
.upper_margin = 0,
|
||||
.lower_margin = 45,
|
||||
.hsync_len = 1,
|
||||
.vsync_len = 1,
|
||||
.sync = FB_SYNC_DATA_ENABLE_HIGH_ACT,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct mxsfb_platform_data m28evk_mxsfb_pdata __initconst = {
|
||||
.mode_list = m28evk_video_modes,
|
||||
.mode_count = ARRAY_SIZE(m28evk_video_modes),
|
||||
.default_bpp = 16,
|
||||
.ld_intf_width = STMLCDIF_18BIT,
|
||||
};
|
||||
|
||||
static struct at24_platform_data m28evk_eeprom = {
|
||||
.byte_len = 16384,
|
||||
.page_size = 32,
|
||||
.flags = AT24_FLAG_ADDR16,
|
||||
};
|
||||
|
||||
static struct i2c_board_info m28_stk5v3_i2c_boardinfo[] __initdata = {
|
||||
{
|
||||
I2C_BOARD_INFO("at24", 0x51), /* E0=1, E1=0, E2=0 */
|
||||
.platform_data = &m28evk_eeprom,
|
||||
},
|
||||
};
|
||||
|
||||
static struct mxs_mmc_platform_data m28evk_mmc_pdata[] __initdata = {
|
||||
{
|
||||
/* mmc0 */
|
||||
.wp_gpio = MX28EVK_MMC0_WRITE_PROTECT,
|
||||
.flags = SLOTF_8_BIT_CAPABLE,
|
||||
}, {
|
||||
/* mmc1 */
|
||||
.wp_gpio = MX28EVK_MMC1_WRITE_PROTECT,
|
||||
.flags = SLOTF_8_BIT_CAPABLE,
|
||||
},
|
||||
};
|
||||
|
||||
static void __init m28evk_init(void)
|
||||
{
|
||||
mxs_iomux_setup_multiple_pads(m28evk_pads, ARRAY_SIZE(m28evk_pads));
|
||||
|
||||
mx28_add_duart();
|
||||
mx28_add_auart0();
|
||||
mx28_add_auart3();
|
||||
|
||||
if (!m28evk_fec_get_mac()) {
|
||||
mx28_add_fec(0, &mx28_fec_pdata[0]);
|
||||
mx28_add_fec(1, &mx28_fec_pdata[1]);
|
||||
}
|
||||
|
||||
mx28_add_flexcan(0, NULL);
|
||||
mx28_add_flexcan(1, NULL);
|
||||
|
||||
mx28_add_mxsfb(&m28evk_mxsfb_pdata);
|
||||
|
||||
mx28_add_mxs_mmc(0, &m28evk_mmc_pdata[0]);
|
||||
mx28_add_mxs_mmc(1, &m28evk_mmc_pdata[1]);
|
||||
|
||||
gpio_led_register_device(0, &m28evk_led_data);
|
||||
|
||||
/* I2C */
|
||||
mx28_add_mxs_i2c(0);
|
||||
i2c_register_board_info(0, m28_stk5v3_i2c_boardinfo,
|
||||
ARRAY_SIZE(m28_stk5v3_i2c_boardinfo));
|
||||
}
|
||||
|
||||
static void __init m28evk_timer_init(void)
|
||||
{
|
||||
mx28_clocks_init();
|
||||
}
|
||||
|
||||
static struct sys_timer m28evk_timer = {
|
||||
.init = m28evk_timer_init,
|
||||
};
|
||||
|
||||
MACHINE_START(M28EVK, "DENX M28 EVK")
|
||||
.map_io = mx28_map_io,
|
||||
.init_irq = mx28_init_irq,
|
||||
.init_machine = m28evk_init,
|
||||
.timer = &m28evk_timer,
|
||||
MACHINE_END
|
|
@ -3078,6 +3078,7 @@ static struct clk gpt12_fck = {
|
|||
.name = "gpt12_fck",
|
||||
.ops = &clkops_null,
|
||||
.parent = &secure_32k_fck,
|
||||
.clkdm_name = "wkup_clkdm",
|
||||
.recalc = &followparent_recalc,
|
||||
};
|
||||
|
||||
|
@ -3085,6 +3086,7 @@ static struct clk wdt1_fck = {
|
|||
.name = "wdt1_fck",
|
||||
.ops = &clkops_null,
|
||||
.parent = &secure_32k_fck,
|
||||
.clkdm_name = "wkup_clkdm",
|
||||
.recalc = &followparent_recalc,
|
||||
};
|
||||
|
||||
|
|
|
@ -3376,10 +3376,18 @@ int __init omap4xxx_clk_init(void)
|
|||
} else if (cpu_is_omap446x()) {
|
||||
cpu_mask = RATE_IN_4460;
|
||||
cpu_clkflg = CK_446X;
|
||||
} else {
|
||||
return 0;
|
||||
}
|
||||
|
||||
clk_init(&omap2_clk_functions);
|
||||
omap2_clk_disable_clkdm_control();
|
||||
|
||||
/*
|
||||
* Must stay commented until all OMAP SoC drivers are
|
||||
* converted to runtime PM, or drivers may start crashing
|
||||
*
|
||||
* omap2_clk_disable_clkdm_control();
|
||||
*/
|
||||
|
||||
for (c = omap44xx_clks; c < omap44xx_clks + ARRAY_SIZE(omap44xx_clks);
|
||||
c++)
|
||||
|
|
|
@ -747,6 +747,7 @@ int clkdm_wakeup(struct clockdomain *clkdm)
|
|||
spin_lock_irqsave(&clkdm->lock, flags);
|
||||
clkdm->_flags &= ~_CLKDM_FLAG_HWSUP_ENABLED;
|
||||
ret = arch_clkdm->clkdm_wakeup(clkdm);
|
||||
ret |= pwrdm_state_switch(clkdm->pwrdm.ptr);
|
||||
spin_unlock_irqrestore(&clkdm->lock, flags);
|
||||
return ret;
|
||||
}
|
||||
|
@ -818,6 +819,7 @@ void clkdm_deny_idle(struct clockdomain *clkdm)
|
|||
spin_lock_irqsave(&clkdm->lock, flags);
|
||||
clkdm->_flags &= ~_CLKDM_FLAG_HWSUP_ENABLED;
|
||||
arch_clkdm->clkdm_deny_idle(clkdm);
|
||||
pwrdm_state_switch(clkdm->pwrdm.ptr);
|
||||
spin_unlock_irqrestore(&clkdm->lock, flags);
|
||||
}
|
||||
|
||||
|
|
|
@ -192,6 +192,7 @@ static struct omap_hwmod_addr_space omap2430_usbhsotg_addrs[] = {
|
|||
.pa_end = OMAP243X_HS_BASE + SZ_4K - 1,
|
||||
.flags = ADDR_TYPE_RT
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
/* l4_core ->usbhsotg interface */
|
||||
|
|
|
@ -130,7 +130,6 @@ int omap_set_pwrdm_state(struct powerdomain *pwrdm, u32 state)
|
|||
} else {
|
||||
hwsup = clkdm_in_hwsup(pwrdm->pwrdm_clkdms[0]);
|
||||
clkdm_wakeup(pwrdm->pwrdm_clkdms[0]);
|
||||
pwrdm_wait_transition(pwrdm);
|
||||
sleep_switch = FORCEWAKEUP_SWITCH;
|
||||
}
|
||||
}
|
||||
|
@ -156,7 +155,6 @@ int omap_set_pwrdm_state(struct powerdomain *pwrdm, u32 state)
|
|||
return ret;
|
||||
}
|
||||
|
||||
pwrdm_wait_transition(pwrdm);
|
||||
pwrdm_state_switch(pwrdm);
|
||||
err:
|
||||
return ret;
|
||||
|
|
|
@ -195,28 +195,35 @@ static int _pwrdm_post_transition_cb(struct powerdomain *pwrdm, void *unused)
|
|||
|
||||
/**
|
||||
* pwrdm_init - set up the powerdomain layer
|
||||
* @pwrdm_list: array of struct powerdomain pointers to register
|
||||
* @pwrdms: array of struct powerdomain pointers to register
|
||||
* @custom_funcs: func pointers for arch specific implementations
|
||||
*
|
||||
* Loop through the array of powerdomains @pwrdm_list, registering all
|
||||
* that are available on the current CPU. If pwrdm_list is supplied
|
||||
* and not null, all of the referenced powerdomains will be
|
||||
* registered. No return value. XXX pwrdm_list is not really a
|
||||
* "list"; it is an array. Rename appropriately.
|
||||
* Loop through the array of powerdomains @pwrdms, registering all
|
||||
* that are available on the current CPU. Also, program all
|
||||
* powerdomain target state as ON; this is to prevent domains from
|
||||
* hitting low power states (if bootloader has target states set to
|
||||
* something other than ON) and potentially even losing context while
|
||||
* PM is not fully initialized. The PM late init code can then program
|
||||
* the desired target state for all the power domains. No return
|
||||
* value.
|
||||
*/
|
||||
void pwrdm_init(struct powerdomain **pwrdm_list, struct pwrdm_ops *custom_funcs)
|
||||
void pwrdm_init(struct powerdomain **pwrdms, struct pwrdm_ops *custom_funcs)
|
||||
{
|
||||
struct powerdomain **p = NULL;
|
||||
struct powerdomain *temp_p;
|
||||
|
||||
if (!custom_funcs)
|
||||
WARN(1, "powerdomain: No custom pwrdm functions registered\n");
|
||||
else
|
||||
arch_pwrdm = custom_funcs;
|
||||
|
||||
if (pwrdm_list) {
|
||||
for (p = pwrdm_list; *p; p++)
|
||||
if (pwrdms) {
|
||||
for (p = pwrdms; *p; p++)
|
||||
_pwrdm_register(*p);
|
||||
}
|
||||
|
||||
list_for_each_entry(temp_p, &pwrdm_list, node)
|
||||
pwrdm_set_next_pwrst(temp_p, PWRDM_POWER_ON);
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
|
@ -77,7 +77,7 @@ static int __init dns323_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
|
|||
/*
|
||||
* Check for devices with hard-wired IRQs.
|
||||
*/
|
||||
irq = orion5x_pci_map_irq(const dev, slot, pin);
|
||||
irq = orion5x_pci_map_irq(dev, slot, pin);
|
||||
if (irq != -1)
|
||||
return irq;
|
||||
|
||||
|
|
|
@ -14,6 +14,7 @@
|
|||
#include <linux/pci.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/mbus.h>
|
||||
#include <video/vga.h>
|
||||
#include <asm/irq.h>
|
||||
#include <asm/mach/pci.h>
|
||||
#include <plat/pcie.h>
|
||||
|
|
|
@ -481,6 +481,7 @@ static void __init sirfsoc_clk_init(void)
|
|||
|
||||
static struct of_device_id clkc_ids[] = {
|
||||
{ .compatible = "sirf,prima2-clkc" },
|
||||
{},
|
||||
};
|
||||
|
||||
void __init sirfsoc_of_clk_init(void)
|
||||
|
|
|
@ -51,6 +51,7 @@ static __init void sirfsoc_irq_init(void)
|
|||
|
||||
static struct of_device_id intc_ids[] = {
|
||||
{ .compatible = "sirf,prima2-intc" },
|
||||
{},
|
||||
};
|
||||
|
||||
void __init sirfsoc_of_irq_init(void)
|
||||
|
|
|
@ -19,6 +19,7 @@ static DEFINE_MUTEX(rstc_lock);
|
|||
|
||||
static struct of_device_id rstc_ids[] = {
|
||||
{ .compatible = "sirf,prima2-rstc" },
|
||||
{},
|
||||
};
|
||||
|
||||
static int __init sirfsoc_of_rstc_init(void)
|
||||
|
|
|
@ -190,6 +190,7 @@ static void __init sirfsoc_timer_init(void)
|
|||
|
||||
static struct of_device_id timer_ids[] = {
|
||||
{ .compatible = "sirf,prima2-tick" },
|
||||
{},
|
||||
};
|
||||
|
||||
static void __init sirfsoc_of_timer_map(void)
|
||||
|
|
|
@ -44,6 +44,7 @@ static inline void arch_reset(char mode, const char *cmd)
|
|||
*/
|
||||
if (realview_reset)
|
||||
realview_reset(mode);
|
||||
dsb();
|
||||
}
|
||||
|
||||
#endif
|
||||
|
|
|
@ -128,7 +128,7 @@ static int s3c2443_armclk_setrate(struct clk *clk, unsigned long rate)
|
|||
unsigned long clkcon0;
|
||||
|
||||
clkcon0 = __raw_readl(S3C2443_CLKDIV0);
|
||||
clkcon0 &= S3C2443_CLKDIV0_ARMDIV_MASK;
|
||||
clkcon0 &= ~S3C2443_CLKDIV0_ARMDIV_MASK;
|
||||
clkcon0 |= val << S3C2443_CLKDIV0_ARMDIV_SHIFT;
|
||||
__raw_writel(clkcon0, S3C2443_CLKDIV0);
|
||||
}
|
||||
|
|
|
@ -262,45 +262,6 @@ static struct samsung_keypad_platdata smdk6410_keypad_data __initdata = {
|
|||
.cols = 8,
|
||||
};
|
||||
|
||||
static int smdk6410_backlight_init(struct device *dev)
|
||||
{
|
||||
int ret;
|
||||
|
||||
ret = gpio_request(S3C64XX_GPF(15), "Backlight");
|
||||
if (ret) {
|
||||
printk(KERN_ERR "failed to request GPF for PWM-OUT1\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* Configure GPIO pin with S3C64XX_GPF15_PWM_TOUT1 */
|
||||
s3c_gpio_cfgpin(S3C64XX_GPF(15), S3C_GPIO_SFN(2));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void smdk6410_backlight_exit(struct device *dev)
|
||||
{
|
||||
s3c_gpio_cfgpin(S3C64XX_GPF(15), S3C_GPIO_OUTPUT);
|
||||
gpio_free(S3C64XX_GPF(15));
|
||||
}
|
||||
|
||||
static struct platform_pwm_backlight_data smdk6410_backlight_data = {
|
||||
.pwm_id = 1,
|
||||
.max_brightness = 255,
|
||||
.dft_brightness = 255,
|
||||
.pwm_period_ns = 78770,
|
||||
.init = smdk6410_backlight_init,
|
||||
.exit = smdk6410_backlight_exit,
|
||||
};
|
||||
|
||||
static struct platform_device smdk6410_backlight_device = {
|
||||
.name = "pwm-backlight",
|
||||
.dev = {
|
||||
.parent = &s3c_device_timer[1].dev,
|
||||
.platform_data = &smdk6410_backlight_data,
|
||||
},
|
||||
};
|
||||
|
||||
static struct map_desc smdk6410_iodesc[] = {};
|
||||
|
||||
static struct platform_device *smdk6410_devices[] __initdata = {
|
||||
|
|
|
@ -16,6 +16,7 @@
|
|||
#include <linux/suspend.h>
|
||||
#include <linux/serial_core.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/gpio.h>
|
||||
|
||||
#include <mach/map.h>
|
||||
#include <mach/irqs.h>
|
||||
|
|
|
@ -129,7 +129,7 @@ static int s5p64x0_alloc_gc(void)
|
|||
}
|
||||
|
||||
ct = gc->chip_types;
|
||||
ct->chip.irq_ack = irq_gc_ack;
|
||||
ct->chip.irq_ack = irq_gc_ack_set_bit;
|
||||
ct->chip.irq_mask = irq_gc_mask_set_bit;
|
||||
ct->chip.irq_unmask = irq_gc_mask_clr_bit;
|
||||
ct->chip.irq_set_type = s5p64x0_irq_eint_set_type;
|
||||
|
|
|
@ -815,8 +815,7 @@ static struct clksrc_clk clksrcs[] = {
|
|||
.reg_div = { .reg = S5P_CLK_DIV3, .shift = 20, .size = 4 },
|
||||
}, {
|
||||
.clk = {
|
||||
.name = "sclk_cam",
|
||||
.devname = "s5pv210-fimc.0",
|
||||
.name = "sclk_cam0",
|
||||
.enable = s5pv210_clk_mask0_ctrl,
|
||||
.ctrlbit = (1 << 3),
|
||||
},
|
||||
|
@ -825,8 +824,7 @@ static struct clksrc_clk clksrcs[] = {
|
|||
.reg_div = { .reg = S5P_CLK_DIV1, .shift = 12, .size = 4 },
|
||||
}, {
|
||||
.clk = {
|
||||
.name = "sclk_cam",
|
||||
.devname = "s5pv210-fimc.1",
|
||||
.name = "sclk_cam1",
|
||||
.enable = s5pv210_clk_mask0_ctrl,
|
||||
.ctrlbit = (1 << 4),
|
||||
},
|
||||
|
|
|
@ -88,7 +88,7 @@ static struct sleep_save s5pv210_core_save[] = {
|
|||
SAVE_ITEM(S3C2410_TCNTO(0)),
|
||||
};
|
||||
|
||||
void s5pv210_cpu_suspend(unsigned long arg)
|
||||
static int s5pv210_cpu_suspend(unsigned long arg)
|
||||
{
|
||||
unsigned long tmp;
|
||||
|
||||
|
|
|
@ -341,6 +341,7 @@ static struct platform_device mipidsi0_device = {
|
|||
static struct sh_mobile_sdhi_info sdhi0_info = {
|
||||
.dma_slave_tx = SHDMA_SLAVE_SDHI0_TX,
|
||||
.dma_slave_rx = SHDMA_SLAVE_SDHI0_RX,
|
||||
.tmio_flags = TMIO_MMC_HAS_IDLE_WAIT,
|
||||
.tmio_caps = MMC_CAP_SD_HIGHSPEED,
|
||||
.tmio_ocr_mask = MMC_VDD_27_28 | MMC_VDD_28_29,
|
||||
};
|
||||
|
@ -382,7 +383,7 @@ void ag5evm_sdhi1_set_pwr(struct platform_device *pdev, int state)
|
|||
}
|
||||
|
||||
static struct sh_mobile_sdhi_info sh_sdhi1_info = {
|
||||
.tmio_flags = TMIO_MMC_WRPROTECT_DISABLE,
|
||||
.tmio_flags = TMIO_MMC_WRPROTECT_DISABLE | TMIO_MMC_HAS_IDLE_WAIT,
|
||||
.tmio_caps = MMC_CAP_NONREMOVABLE | MMC_CAP_SDIO_IRQ,
|
||||
.tmio_ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34,
|
||||
.set_pwr = ag5evm_sdhi1_set_pwr,
|
||||
|
|
|
@ -1412,6 +1412,7 @@ static void __init ap4evb_init(void)
|
|||
fsi_init_pm_clock();
|
||||
sh7372_pm_init();
|
||||
pm_clk_add(&fsi_device.dev, "spu2");
|
||||
pm_clk_add(&lcdc1_device.dev, "hdmi");
|
||||
}
|
||||
|
||||
static void __init ap4evb_timer_init(void)
|
||||
|
|
|
@ -641,6 +641,8 @@ static struct usbhs_private usbhs0_private = {
|
|||
},
|
||||
.driver_param = {
|
||||
.buswait_bwait = 4,
|
||||
.d0_tx_id = SHDMA_SLAVE_USB0_TX,
|
||||
.d1_rx_id = SHDMA_SLAVE_USB0_RX,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
@ -810,6 +812,8 @@ static struct usbhs_private usbhs1_private = {
|
|||
.buswait_bwait = 4,
|
||||
.pipe_type = usbhs1_pipe_cfg,
|
||||
.pipe_size = ARRAY_SIZE(usbhs1_pipe_cfg),
|
||||
.d0_tx_id = SHDMA_SLAVE_USB1_TX,
|
||||
.d1_rx_id = SHDMA_SLAVE_USB1_RX,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
@ -1588,6 +1592,7 @@ static void __init mackerel_init(void)
|
|||
hdmi_init_pm_clock();
|
||||
sh7372_pm_init();
|
||||
pm_clk_add(&fsi_device.dev, "spu2");
|
||||
pm_clk_add(&hdmi_lcdc_device.dev, "hdmi");
|
||||
}
|
||||
|
||||
static void __init mackerel_timer_init(void)
|
||||
|
|
|
@ -503,16 +503,17 @@ static struct clk *late_main_clks[] = {
|
|||
&sh7372_fsidivb_clk,
|
||||
};
|
||||
|
||||
enum { MSTP001,
|
||||
enum { MSTP001, MSTP000,
|
||||
MSTP131, MSTP130,
|
||||
MSTP129, MSTP128, MSTP127, MSTP126, MSTP125,
|
||||
MSTP118, MSTP117, MSTP116, MSTP113,
|
||||
MSTP106, MSTP101, MSTP100,
|
||||
MSTP223,
|
||||
MSTP218, MSTP217, MSTP216,
|
||||
MSTP207, MSTP206, MSTP204, MSTP203, MSTP202, MSTP201, MSTP200,
|
||||
MSTP329, MSTP328, MSTP323, MSTP322, MSTP314, MSTP313, MSTP312,
|
||||
MSTP423, MSTP415, MSTP413, MSTP411, MSTP410, MSTP406, MSTP403,
|
||||
MSTP218, MSTP217, MSTP216, MSTP214, MSTP208, MSTP207,
|
||||
MSTP206, MSTP205, MSTP204, MSTP203, MSTP202, MSTP201, MSTP200,
|
||||
MSTP328, MSTP323, MSTP322, MSTP314, MSTP313, MSTP312,
|
||||
MSTP423, MSTP415, MSTP413, MSTP411, MSTP410, MSTP407, MSTP406,
|
||||
MSTP405, MSTP404, MSTP403, MSTP400,
|
||||
MSTP_NR };
|
||||
|
||||
#define MSTP(_parent, _reg, _bit, _flags) \
|
||||
|
@ -520,6 +521,7 @@ enum { MSTP001,
|
|||
|
||||
static struct clk mstp_clks[MSTP_NR] = {
|
||||
[MSTP001] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR0, 1, 0), /* IIC2 */
|
||||
[MSTP000] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR0, 0, 0), /* MSIOF0 */
|
||||
[MSTP131] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 31, 0), /* VEU3 */
|
||||
[MSTP130] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 30, 0), /* VEU2 */
|
||||
[MSTP129] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 29, 0), /* VEU1 */
|
||||
|
@ -538,14 +540,16 @@ static struct clk mstp_clks[MSTP_NR] = {
|
|||
[MSTP218] = MSTP(&div4_clks[DIV4_HP], SMSTPCR2, 18, 0), /* DMAC1 */
|
||||
[MSTP217] = MSTP(&div4_clks[DIV4_HP], SMSTPCR2, 17, 0), /* DMAC2 */
|
||||
[MSTP216] = MSTP(&div4_clks[DIV4_HP], SMSTPCR2, 16, 0), /* DMAC3 */
|
||||
[MSTP214] = MSTP(&div4_clks[DIV4_HP], SMSTPCR2, 14, 0), /* USBDMAC */
|
||||
[MSTP208] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 8, 0), /* MSIOF1 */
|
||||
[MSTP207] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 7, 0), /* SCIFA5 */
|
||||
[MSTP206] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 6, 0), /* SCIFB */
|
||||
[MSTP205] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 5, 0), /* MSIOF2 */
|
||||
[MSTP204] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 4, 0), /* SCIFA0 */
|
||||
[MSTP203] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 3, 0), /* SCIFA1 */
|
||||
[MSTP202] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 2, 0), /* SCIFA2 */
|
||||
[MSTP201] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 1, 0), /* SCIFA3 */
|
||||
[MSTP200] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 0, 0), /* SCIFA4 */
|
||||
[MSTP329] = MSTP(&r_clk, SMSTPCR3, 29, 0), /* CMT10 */
|
||||
[MSTP328] = MSTP(&div6_clks[DIV6_SPU], SMSTPCR3, 28, 0), /* FSI2 */
|
||||
[MSTP323] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR3, 23, 0), /* IIC1 */
|
||||
[MSTP322] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR3, 22, 0), /* USB0 */
|
||||
|
@ -557,8 +561,12 @@ static struct clk mstp_clks[MSTP_NR] = {
|
|||
[MSTP413] = MSTP(&pllc1_div2_clk, SMSTPCR4, 13, 0), /* HDMI */
|
||||
[MSTP411] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR4, 11, 0), /* IIC3 */
|
||||
[MSTP410] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR4, 10, 0), /* IIC4 */
|
||||
[MSTP407] = MSTP(&div4_clks[DIV4_HP], SMSTPCR4, 7, 0), /* USB-DMAC1 */
|
||||
[MSTP406] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR4, 6, 0), /* USB1 */
|
||||
[MSTP405] = MSTP(&r_clk, SMSTPCR4, 5, 0), /* CMT4 */
|
||||
[MSTP404] = MSTP(&r_clk, SMSTPCR4, 4, 0), /* CMT3 */
|
||||
[MSTP403] = MSTP(&r_clk, SMSTPCR4, 3, 0), /* KEYSC */
|
||||
[MSTP400] = MSTP(&r_clk, SMSTPCR4, 0, 0), /* CMT2 */
|
||||
};
|
||||
|
||||
static struct clk_lookup lookups[] = {
|
||||
|
@ -609,6 +617,7 @@ static struct clk_lookup lookups[] = {
|
|||
|
||||
/* MSTP32 clocks */
|
||||
CLKDEV_DEV_ID("i2c-sh_mobile.2", &mstp_clks[MSTP001]), /* IIC2 */
|
||||
CLKDEV_DEV_ID("spi_sh_msiof.0", &mstp_clks[MSTP000]), /* MSIOF0 */
|
||||
CLKDEV_DEV_ID("uio_pdrv_genirq.4", &mstp_clks[MSTP131]), /* VEU3 */
|
||||
CLKDEV_DEV_ID("uio_pdrv_genirq.3", &mstp_clks[MSTP130]), /* VEU2 */
|
||||
CLKDEV_DEV_ID("uio_pdrv_genirq.2", &mstp_clks[MSTP129]), /* VEU1 */
|
||||
|
@ -629,14 +638,16 @@ static struct clk_lookup lookups[] = {
|
|||
CLKDEV_DEV_ID("sh-dma-engine.0", &mstp_clks[MSTP218]), /* DMAC1 */
|
||||
CLKDEV_DEV_ID("sh-dma-engine.1", &mstp_clks[MSTP217]), /* DMAC2 */
|
||||
CLKDEV_DEV_ID("sh-dma-engine.2", &mstp_clks[MSTP216]), /* DMAC3 */
|
||||
CLKDEV_DEV_ID("sh-dma-engine.3", &mstp_clks[MSTP214]), /* USB-DMAC0 */
|
||||
CLKDEV_DEV_ID("spi_sh_msiof.1", &mstp_clks[MSTP208]), /* MSIOF1 */
|
||||
CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP207]), /* SCIFA5 */
|
||||
CLKDEV_DEV_ID("sh-sci.6", &mstp_clks[MSTP206]), /* SCIFB */
|
||||
CLKDEV_DEV_ID("spi_sh_msiof.2", &mstp_clks[MSTP205]), /* MSIOF2 */
|
||||
CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]), /* SCIFA0 */
|
||||
CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]), /* SCIFA1 */
|
||||
CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP202]), /* SCIFA2 */
|
||||
CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP201]), /* SCIFA3 */
|
||||
CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP200]), /* SCIFA4 */
|
||||
CLKDEV_DEV_ID("sh_cmt.10", &mstp_clks[MSTP329]), /* CMT10 */
|
||||
CLKDEV_DEV_ID("sh_fsi2", &mstp_clks[MSTP328]), /* FSI2 */
|
||||
CLKDEV_DEV_ID("i2c-sh_mobile.1", &mstp_clks[MSTP323]), /* IIC1 */
|
||||
CLKDEV_DEV_ID("r8a66597_hcd.0", &mstp_clks[MSTP322]), /* USB0 */
|
||||
|
@ -650,11 +661,17 @@ static struct clk_lookup lookups[] = {
|
|||
CLKDEV_DEV_ID("sh-mobile-hdmi", &mstp_clks[MSTP413]), /* HDMI */
|
||||
CLKDEV_DEV_ID("i2c-sh_mobile.3", &mstp_clks[MSTP411]), /* IIC3 */
|
||||
CLKDEV_DEV_ID("i2c-sh_mobile.4", &mstp_clks[MSTP410]), /* IIC4 */
|
||||
CLKDEV_DEV_ID("sh-dma-engine.4", &mstp_clks[MSTP407]), /* USB-DMAC1 */
|
||||
CLKDEV_DEV_ID("r8a66597_hcd.1", &mstp_clks[MSTP406]), /* USB1 */
|
||||
CLKDEV_DEV_ID("r8a66597_udc.1", &mstp_clks[MSTP406]), /* USB1 */
|
||||
CLKDEV_DEV_ID("renesas_usbhs.1", &mstp_clks[MSTP406]), /* USB1 */
|
||||
CLKDEV_DEV_ID("sh_cmt.4", &mstp_clks[MSTP405]), /* CMT4 */
|
||||
CLKDEV_DEV_ID("sh_cmt.3", &mstp_clks[MSTP404]), /* CMT3 */
|
||||
CLKDEV_DEV_ID("sh_keysc.0", &mstp_clks[MSTP403]), /* KEYSC */
|
||||
CLKDEV_DEV_ID("sh_cmt.2", &mstp_clks[MSTP400]), /* CMT2 */
|
||||
|
||||
CLKDEV_ICK_ID("hdmi", "sh_mobile_lcdc_fb.1",
|
||||
&div6_reparent_clks[DIV6_HDMI]),
|
||||
CLKDEV_ICK_ID("ick", "sh-mobile-hdmi", &div6_reparent_clks[DIV6_HDMI]),
|
||||
CLKDEV_ICK_ID("icka", "sh_fsi2", &div6_reparent_clks[DIV6_FSIA]),
|
||||
CLKDEV_ICK_ID("ickb", "sh_fsi2", &div6_reparent_clks[DIV6_FSIB]),
|
||||
|
|
|
@ -365,7 +365,7 @@ void __init sh73a0_clock_init(void)
|
|||
__raw_writel(0x108, SD2CKCR);
|
||||
|
||||
/* detect main clock parent */
|
||||
switch ((__raw_readl(CKSCR) >> 24) & 0x03) {
|
||||
switch ((__raw_readl(CKSCR) >> 28) & 0x03) {
|
||||
case 0:
|
||||
main_clk.parent = &sh73a0_extal1_clk;
|
||||
break;
|
||||
|
|
Some files were not shown because too many files have changed in this diff Show more
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Reference in a new issue