staging: tidspbridge: set1 remove hungarian from structs
hungarian notation will be removed from the elements inside structures, the next varibles will be renamed: dw_api_reg_base api_reg_base dw_brd_state brd_state dw_chnl_buf_size chnl_buf_size dw_chnl_offset chnl_offset dw_cmd cmd dw_core_pm_base core_pm_base dw_dsp_base dsp_base dw_dsp_base_va dsp_base_va dw_dsp_bufs dsp_bufs dw_dsp_buf_size dsp_buf_size dw_dsp_clk_m2_base dsp_clk_m2_base dw_dsp_ext_base_addr dsp_ext_base_addr dw_dsp_phys_addr_offset dsp_phys_addr_offset dw_dsp_start_add dsp_start_add dw_err_mask err_mask dw_gpp_base_pa gpp_base_pa dw_api_clk_base api_clk_base dw_api_reg_base api_reg_base dw_arg arg dw_arg1 arg1 dw_arg2 arg2 dw_chnl_buf_size chnl_buf_size Signed-off-by: Rene Sapiens <rene.sapiens@ti.com> Signed-off-by: Armando Uribe <x0095078@ti.com> Signed-off-by: Omar Ramirez Luna <omar.ramirez@ti.com>
This commit is contained in:
parent
92d0293038
commit
b4da7fc381
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@ -320,22 +320,22 @@ static const struct bpwr_clk_t bpwr_clks[] = {
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/* This Bridge driver's device context: */
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struct bridge_dev_context {
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struct dev_object *hdev_obj; /* Handle to Bridge device object. */
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u32 dw_dsp_base_addr; /* Arm's API to DSP virt base addr */
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u32 dsp_base_addr; /* Arm's API to DSP virt base addr */
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/*
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* DSP External memory prog address as seen virtually by the OS on
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* the host side.
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*/
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u32 dw_dsp_ext_base_addr; /* See the comment above */
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u32 dw_api_reg_base; /* API mem map'd registers */
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u32 dsp_ext_base_addr; /* See the comment above */
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u32 api_reg_base; /* API mem map'd registers */
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void __iomem *dw_dsp_mmu_base; /* DSP MMU Mapped registers */
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u32 dw_api_clk_base; /* CLK Registers */
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u32 dw_dsp_clk_m2_base; /* DSP Clock Module m2 */
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u32 api_clk_base; /* CLK Registers */
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u32 dsp_clk_m2_base; /* DSP Clock Module m2 */
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u32 dw_public_rhea; /* Pub Rhea */
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u32 dw_int_addr; /* MB INTR reg */
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u32 dw_tc_endianism; /* TC Endianism register */
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u32 dw_test_base; /* DSP MMU Mapped registers */
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u32 dw_self_loop; /* Pointer to the selfloop */
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u32 dw_dsp_start_add; /* API Boot vector */
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u32 dsp_start_add; /* API Boot vector */
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u32 dw_internal_size; /* Internal memory size */
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struct omap_mbox *mbox; /* Mail box handle */
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@ -348,7 +348,7 @@ struct bridge_dev_context {
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*/
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/* DMMU TLB entries */
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struct bridge_ioctl_extproc atlb_entry[BRDIOCTL_NUMOFMMUTLB];
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u32 dw_brd_state; /* Last known board state. */
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u32 brd_state; /* Last known board state. */
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/* TC Settings */
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bool tc_word_swap_on; /* Traffic Controller Word Swap */
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@ -196,7 +196,7 @@ func_cont:
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chnl_packet_obj->byte_size = byte_size;
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chnl_packet_obj->buf_size = buf_size;
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/* Only valid for output channel */
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chnl_packet_obj->dw_arg = dw_arg;
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chnl_packet_obj->arg = dw_arg;
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chnl_packet_obj->status = (is_eos ? CHNL_IOCSTATEOS :
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CHNL_IOCSTATCOMPLETE);
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list_add_tail(&chnl_packet_obj->link, &pchnl->pio_requests);
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@ -607,7 +607,7 @@ int bridge_chnl_get_ioc(struct chnl_object *chnl_obj, u32 timeout,
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ioc.pbuf = chnl_packet_obj->host_user_buf;
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ioc.byte_size = chnl_packet_obj->byte_size;
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ioc.buf_size = chnl_packet_obj->buf_size;
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ioc.dw_arg = chnl_packet_obj->dw_arg;
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ioc.arg = chnl_packet_obj->arg;
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ioc.status |= chnl_packet_obj->status;
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/* Place the used chirp on the free list: */
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list_add_tail(&chnl_packet_obj->link,
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@ -615,7 +615,7 @@ int bridge_chnl_get_ioc(struct chnl_object *chnl_obj, u32 timeout,
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} else {
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ioc.pbuf = NULL;
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ioc.byte_size = 0;
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ioc.dw_arg = 0;
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ioc.arg = 0;
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ioc.buf_size = 0;
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}
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/* Ensure invariant: If any IOC's are queued for this channel... */
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@ -1113,7 +1113,7 @@ static void input_chnl(struct io_mgr *pio_mgr, struct chnl_object *pchnl,
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pio_mgr->input, bytes);
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pchnl->bytes_moved += bytes;
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chnl_packet_obj->byte_size = bytes;
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chnl_packet_obj->dw_arg = dw_arg;
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chnl_packet_obj->arg = dw_arg;
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chnl_packet_obj->status = CHNL_IOCSTATCOMPLETE;
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if (bytes == 0) {
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@ -1200,14 +1200,14 @@ static void input_msg(struct io_mgr *pio_mgr, struct msg_mgr *hmsg_mgr)
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msg_input = pio_mgr->msg_input;
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for (i = 0; i < num_msgs; i++) {
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/* Read the next message */
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addr = (u32) &(((struct msg_dspmsg *)msg_input)->msg.dw_cmd);
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msg.msg.dw_cmd =
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addr = (u32) &(((struct msg_dspmsg *)msg_input)->msg.cmd);
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msg.msg.cmd =
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read_ext32_bit_dsp_data(pio_mgr->hbridge_context, addr);
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addr = (u32) &(((struct msg_dspmsg *)msg_input)->msg.dw_arg1);
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msg.msg.dw_arg1 =
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addr = (u32) &(((struct msg_dspmsg *)msg_input)->msg.arg1);
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msg.msg.arg1 =
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read_ext32_bit_dsp_data(pio_mgr->hbridge_context, addr);
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addr = (u32) &(((struct msg_dspmsg *)msg_input)->msg.dw_arg2);
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msg.msg.dw_arg2 =
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addr = (u32) &(((struct msg_dspmsg *)msg_input)->msg.arg2);
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msg.msg.arg2 =
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read_ext32_bit_dsp_data(pio_mgr->hbridge_context, addr);
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addr = (u32) &(((struct msg_dspmsg *)msg_input)->msgq_id);
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msg.msgq_id =
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@ -1215,9 +1215,9 @@ static void input_msg(struct io_mgr *pio_mgr, struct msg_mgr *hmsg_mgr)
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msg_input += sizeof(struct msg_dspmsg);
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/* Determine which queue to put the message in */
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dev_dbg(bridge, "input msg: dw_cmd=0x%x dw_arg1=0x%x "
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"dw_arg2=0x%x msgq_id=0x%x\n", msg.msg.dw_cmd,
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msg.msg.dw_arg1, msg.msg.dw_arg2, msg.msgq_id);
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dev_dbg(bridge, "input msg: cmd=0x%x arg1=0x%x "
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"arg2=0x%x msgq_id=0x%x\n", msg.msg.cmd,
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msg.msg.arg1, msg.msg.arg2, msg.msgq_id);
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/*
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* Interrupt may occur before shared memory and message
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* input locations have been set up. If all nodes were
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@ -1228,14 +1228,14 @@ static void input_msg(struct io_mgr *pio_mgr, struct msg_mgr *hmsg_mgr)
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if (msg.msgq_id != msg_queue_obj->msgq_id)
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continue;
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/* Found it */
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if (msg.msg.dw_cmd == RMS_EXITACK) {
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if (msg.msg.cmd == RMS_EXITACK) {
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/*
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* Call the node exit notification.
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* The exit message does not get
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* queued.
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*/
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(*hmsg_mgr->on_exit)(msg_queue_obj->arg,
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msg.msg.dw_arg1);
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msg.msg.arg1);
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break;
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}
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/*
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@ -1367,7 +1367,7 @@ static void output_chnl(struct io_mgr *pio_mgr, struct chnl_object *pchnl,
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chnl_packet_obj->byte_size);
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pchnl->bytes_moved += chnl_packet_obj->byte_size;
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/* Write all 32 bits of arg */
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sm->arg = chnl_packet_obj->dw_arg;
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sm->arg = chnl_packet_obj->arg;
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#if _CHNL_WORDSIZE == 2
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/* Access can be different SM access word size (e.g. 16/32 bit words) */
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sm->output_id = (u16) chnl_id;
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@ -1430,16 +1430,16 @@ static void output_msg(struct io_mgr *pio_mgr, struct msg_mgr *hmsg_mgr)
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addr = (u32) &msg_output->msgq_id;
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write_ext32_bit_dsp_data(pio_mgr->hbridge_context, addr, val);
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val = (pmsg->msg_data).msg.dw_cmd;
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addr = (u32) &msg_output->msg.dw_cmd;
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val = (pmsg->msg_data).msg.cmd;
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addr = (u32) &msg_output->msg.cmd;
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write_ext32_bit_dsp_data(pio_mgr->hbridge_context, addr, val);
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val = (pmsg->msg_data).msg.dw_arg1;
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addr = (u32) &msg_output->msg.dw_arg1;
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val = (pmsg->msg_data).msg.arg1;
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addr = (u32) &msg_output->msg.arg1;
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write_ext32_bit_dsp_data(pio_mgr->hbridge_context, addr, val);
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val = (pmsg->msg_data).msg.dw_arg2;
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addr = (u32) &msg_output->msg.dw_arg2;
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val = (pmsg->msg_data).msg.arg2;
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addr = (u32) &msg_output->msg.arg2;
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write_ext32_bit_dsp_data(pio_mgr->hbridge_context, addr, val);
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msg_output++;
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@ -229,8 +229,8 @@ static struct notifier_block dsp_mbox_notifier = {
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static inline void flush_all(struct bridge_dev_context *dev_context)
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{
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if (dev_context->dw_brd_state == BRD_DSP_HIBERNATION ||
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dev_context->dw_brd_state == BRD_HIBERNATION)
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if (dev_context->brd_state == BRD_DSP_HIBERNATION ||
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dev_context->brd_state == BRD_HIBERNATION)
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wake_dsp(dev_context, NULL);
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hw_mmu_tlb_flush_all(dev_context->dw_dsp_mmu_base);
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@ -306,7 +306,7 @@ static int bridge_brd_monitor(struct bridge_dev_context *dev_ctxt)
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dsp_clk_enable(DSP_CLK_IVA2);
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/* set the device state to IDLE */
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dev_context->dw_brd_state = BRD_IDLE;
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dev_context->brd_state = BRD_IDLE;
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return 0;
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}
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@ -323,16 +323,16 @@ static int bridge_brd_read(struct bridge_dev_context *dev_ctxt,
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int status = 0;
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struct bridge_dev_context *dev_context = dev_ctxt;
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u32 offset;
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u32 dsp_base_addr = dev_ctxt->dw_dsp_base_addr;
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u32 dsp_base_addr = dev_ctxt->dsp_base_addr;
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if (dsp_addr < dev_context->dw_dsp_start_add) {
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if (dsp_addr < dev_context->dsp_start_add) {
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status = -EPERM;
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return status;
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}
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/* change here to account for the 3 bands of the DSP internal memory */
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if ((dsp_addr - dev_context->dw_dsp_start_add) <
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if ((dsp_addr - dev_context->dsp_start_add) <
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dev_context->dw_internal_size) {
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offset = dsp_addr - dev_context->dw_dsp_start_add;
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offset = dsp_addr - dev_context->dsp_start_add;
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} else {
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status = read_ext_dsp_data(dev_context, host_buff, dsp_addr,
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ul_num_bytes, mem_type);
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@ -354,7 +354,7 @@ static int bridge_brd_set_state(struct bridge_dev_context *dev_ctxt,
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int status = 0;
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struct bridge_dev_context *dev_context = dev_ctxt;
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dev_context->dw_brd_state = brd_state;
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dev_context->brd_state = brd_state;
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return status;
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}
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@ -616,10 +616,10 @@ static int bridge_brd_start(struct bridge_dev_context *dev_ctxt,
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__raw_writel(0XCAFECAFE, dw_sync_addr);
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/* update board state */
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dev_context->dw_brd_state = BRD_RUNNING;
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dev_context->brd_state = BRD_RUNNING;
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/* (void)chnlsm_enable_interrupt(dev_context); */
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} else {
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dev_context->dw_brd_state = BRD_UNKNOWN;
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dev_context->brd_state = BRD_UNKNOWN;
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}
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}
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return status;
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@ -642,7 +642,7 @@ static int bridge_brd_stop(struct bridge_dev_context *dev_ctxt)
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struct omap_dsp_platform_data *pdata =
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omap_dspbridge_dev->dev.platform_data;
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if (dev_context->dw_brd_state == BRD_STOPPED)
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if (dev_context->brd_state == BRD_STOPPED)
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return status;
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/* as per TRM, it is advised to first drive the IVA2 to 'Standby' mode,
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@ -667,10 +667,10 @@ static int bridge_brd_stop(struct bridge_dev_context *dev_ctxt)
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udelay(10);
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/* Release the Ext Base virtual Address as the next DSP Program
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* may have a different load address */
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if (dev_context->dw_dsp_ext_base_addr)
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dev_context->dw_dsp_ext_base_addr = 0;
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if (dev_context->dsp_ext_base_addr)
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dev_context->dsp_ext_base_addr = 0;
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dev_context->dw_brd_state = BRD_STOPPED; /* update board state */
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dev_context->brd_state = BRD_STOPPED; /* update board state */
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dsp_wdt_enable(false);
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@ -706,7 +706,7 @@ static int bridge_brd_status(struct bridge_dev_context *dev_ctxt,
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int *board_state)
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{
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struct bridge_dev_context *dev_context = dev_ctxt;
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*board_state = dev_context->dw_brd_state;
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*board_state = dev_context->brd_state;
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return 0;
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}
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@ -721,11 +721,11 @@ static int bridge_brd_write(struct bridge_dev_context *dev_ctxt,
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int status = 0;
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struct bridge_dev_context *dev_context = dev_ctxt;
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if (dsp_addr < dev_context->dw_dsp_start_add) {
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if (dsp_addr < dev_context->dsp_start_add) {
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status = -EPERM;
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return status;
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}
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if ((dsp_addr - dev_context->dw_dsp_start_add) <
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if ((dsp_addr - dev_context->dsp_start_add) <
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dev_context->dw_internal_size) {
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status = write_dsp_data(dev_ctxt, host_buff, dsp_addr,
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ul_num_bytes, mem_type);
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@ -764,7 +764,7 @@ static int bridge_dev_create(struct bridge_dev_context
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goto func_end;
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}
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dev_context->dw_dsp_start_add = (u32) OMAP_GEM_BASE;
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dev_context->dsp_start_add = (u32) OMAP_GEM_BASE;
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dev_context->dw_self_loop = (u32) NULL;
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dev_context->dsp_per_clks = 0;
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dev_context->dw_internal_size = OMAP_DSP_SIZE;
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@ -774,14 +774,14 @@ static int bridge_dev_create(struct bridge_dev_context
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dev_context->atlb_entry[entry_ndx].ul_gpp_pa =
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dev_context->atlb_entry[entry_ndx].ul_dsp_va = 0;
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}
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dev_context->dw_dsp_base_addr = (u32) MEM_LINEAR_ADDRESS((void *)
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dev_context->dsp_base_addr = (u32) MEM_LINEAR_ADDRESS((void *)
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(config_param->
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dw_mem_base
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[3]),
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config_param->
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dw_mem_length
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[3]);
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if (!dev_context->dw_dsp_base_addr)
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if (!dev_context->dsp_base_addr)
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status = -EPERM;
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pt_attrs = kzalloc(sizeof(struct pg_table_attrs), GFP_KERNEL);
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@ -874,7 +874,7 @@ static int bridge_dev_create(struct bridge_dev_context
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if (!status) {
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dev_context->hdev_obj = hdev_obj;
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/* Store current board state. */
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dev_context->dw_brd_state = BRD_UNKNOWN;
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dev_context->brd_state = BRD_UNKNOWN;
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dev_context->resources = resources;
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dsp_clk_enable(DSP_CLK_IVA2);
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bridge_brd_stop(dev_context);
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@ -1032,8 +1032,8 @@ static int bridge_dev_destroy(struct bridge_dev_context *dev_ctxt)
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iounmap(host_res->dw_per_base);
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if (host_res->dw_per_pm_base)
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iounmap((void *)host_res->dw_per_pm_base);
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if (host_res->dw_core_pm_base)
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iounmap((void *)host_res->dw_core_pm_base);
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if (host_res->core_pm_base)
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iounmap((void *)host_res->core_pm_base);
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host_res->dw_mem_base[0] = (u32) NULL;
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host_res->dw_mem_base[2] = (u32) NULL;
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@ -1070,7 +1070,7 @@ static int bridge_brd_mem_copy(struct bridge_dev_context *dev_ctxt,
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status = read_ext_dsp_data(dev_ctxt, host_buf, src_addr,
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copy_bytes, mem_type);
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if (!status) {
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if (dest_addr < (dev_context->dw_dsp_start_add +
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if (dest_addr < (dev_context->dsp_start_add +
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dev_context->dw_internal_size)) {
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/* Write to Internal memory */
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status = write_dsp_data(dev_ctxt, host_buf,
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@ -1104,7 +1104,7 @@ static int bridge_brd_mem_write(struct bridge_dev_context *dev_ctxt,
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while (ul_remain_bytes > 0 && !status) {
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ul_bytes =
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ul_remain_bytes > BUFFERSIZE ? BUFFERSIZE : ul_remain_bytes;
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if (dsp_addr < (dev_context->dw_dsp_start_add +
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if (dsp_addr < (dev_context->dsp_start_add +
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dev_context->dw_internal_size)) {
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status =
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write_dsp_data(dev_ctxt, host_buff, dsp_addr,
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@ -118,7 +118,7 @@ int handle_hibernation_from_dsp(struct bridge_dev_context *dev_context)
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if (!status) {
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/* Update the Bridger Driver state */
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dev_context->dw_brd_state = BRD_DSP_HIBERNATION;
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dev_context->brd_state = BRD_DSP_HIBERNATION;
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#ifdef CONFIG_TIDSPBRIDGE_DVFS
|
||||
status =
|
||||
dev_get_io_mgr(dev_context->hdev_obj, &hio_mgr);
|
||||
|
@ -163,7 +163,7 @@ int sleep_dsp(struct bridge_dev_context *dev_context, u32 dw_cmd,
|
|||
if ((dw_cmd != PWR_DEEPSLEEP) && (dw_cmd != PWR_EMERGENCYDEEPSLEEP))
|
||||
return -EINVAL;
|
||||
|
||||
switch (dev_context->dw_brd_state) {
|
||||
switch (dev_context->brd_state) {
|
||||
case BRD_RUNNING:
|
||||
omap_mbox_save_ctx(dev_context->mbox);
|
||||
if (dsp_test_sleepstate == PWRDM_POWER_OFF) {
|
||||
|
@ -223,9 +223,9 @@ int sleep_dsp(struct bridge_dev_context *dev_context, u32 dw_cmd,
|
|||
} else {
|
||||
/* Update the Bridger Driver state */
|
||||
if (dsp_test_sleepstate == PWRDM_POWER_OFF)
|
||||
dev_context->dw_brd_state = BRD_HIBERNATION;
|
||||
dev_context->brd_state = BRD_HIBERNATION;
|
||||
else
|
||||
dev_context->dw_brd_state = BRD_RETENTION;
|
||||
dev_context->brd_state = BRD_RETENTION;
|
||||
|
||||
/* Disable wdt on hibernation. */
|
||||
dsp_wdt_enable(false);
|
||||
|
@ -258,8 +258,8 @@ int wake_dsp(struct bridge_dev_context *dev_context, void *pargs)
|
|||
#ifdef CONFIG_PM
|
||||
|
||||
/* Check the board state, if it is not 'SLEEP' then return */
|
||||
if (dev_context->dw_brd_state == BRD_RUNNING ||
|
||||
dev_context->dw_brd_state == BRD_STOPPED) {
|
||||
if (dev_context->brd_state == BRD_RUNNING ||
|
||||
dev_context->brd_state == BRD_STOPPED) {
|
||||
/* The Device is in 'RET' or 'OFF' state and Bridge state is not
|
||||
* 'SLEEP', this means state inconsistency, so return */
|
||||
return 0;
|
||||
|
@ -269,7 +269,7 @@ int wake_dsp(struct bridge_dev_context *dev_context, void *pargs)
|
|||
sm_interrupt_dsp(dev_context, MBX_PM_DSPWAKEUP);
|
||||
|
||||
/* Set the device state to RUNNIG */
|
||||
dev_context->dw_brd_state = BRD_RUNNING;
|
||||
dev_context->brd_state = BRD_RUNNING;
|
||||
#endif /* CONFIG_PM */
|
||||
return status;
|
||||
}
|
||||
|
@ -351,12 +351,12 @@ int pre_scale_dsp(struct bridge_dev_context *dev_context, void *pargs)
|
|||
|
||||
dev_dbg(bridge, "OPP: %s voltage_domain = %x, level = 0x%x\n",
|
||||
__func__, voltage_domain, level);
|
||||
if ((dev_context->dw_brd_state == BRD_HIBERNATION) ||
|
||||
(dev_context->dw_brd_state == BRD_RETENTION) ||
|
||||
(dev_context->dw_brd_state == BRD_DSP_HIBERNATION)) {
|
||||
if ((dev_context->brd_state == BRD_HIBERNATION) ||
|
||||
(dev_context->brd_state == BRD_RETENTION) ||
|
||||
(dev_context->brd_state == BRD_DSP_HIBERNATION)) {
|
||||
dev_dbg(bridge, "OPP: %s IVA in sleep. No message to DSP\n");
|
||||
return 0;
|
||||
} else if ((dev_context->dw_brd_state == BRD_RUNNING)) {
|
||||
} else if ((dev_context->brd_state == BRD_RUNNING)) {
|
||||
/* Send a prenotificatio to DSP */
|
||||
dev_dbg(bridge, "OPP: %s sent notification to DSP\n", __func__);
|
||||
sm_interrupt_dsp(dev_context, MBX_PM_SETPOINT_PRENOTIFY);
|
||||
|
@ -390,14 +390,14 @@ int post_scale_dsp(struct bridge_dev_context *dev_context,
|
|||
level = *((u32 *) pargs + 1);
|
||||
dev_dbg(bridge, "OPP: %s voltage_domain = %x, level = 0x%x\n",
|
||||
__func__, voltage_domain, level);
|
||||
if ((dev_context->dw_brd_state == BRD_HIBERNATION) ||
|
||||
(dev_context->dw_brd_state == BRD_RETENTION) ||
|
||||
(dev_context->dw_brd_state == BRD_DSP_HIBERNATION)) {
|
||||
if ((dev_context->brd_state == BRD_HIBERNATION) ||
|
||||
(dev_context->brd_state == BRD_RETENTION) ||
|
||||
(dev_context->brd_state == BRD_DSP_HIBERNATION)) {
|
||||
/* Update the OPP value in shared memory */
|
||||
io_sh_msetting(hio_mgr, SHM_CURROPP, &level);
|
||||
dev_dbg(bridge, "OPP: %s IVA in sleep. Wrote to shm\n",
|
||||
__func__);
|
||||
} else if ((dev_context->dw_brd_state == BRD_RUNNING)) {
|
||||
} else if ((dev_context->brd_state == BRD_RUNNING)) {
|
||||
/* Update the OPP value in shared memory */
|
||||
io_sh_msetting(hio_mgr, SHM_CURROPP, &level);
|
||||
/* Send a post notification to DSP */
|
||||
|
@ -486,8 +486,8 @@ void dsp_clk_wakeup_event_ctrl(u32 clock_id, bool enable)
|
|||
writel(mpu_grpsel, resources->dw_per_pm_base + 0xA4);
|
||||
break;
|
||||
case BPWR_MCBSP1:
|
||||
iva2_grpsel = readl(resources->dw_core_pm_base + 0xA8);
|
||||
mpu_grpsel = readl(resources->dw_core_pm_base + 0xA4);
|
||||
iva2_grpsel = readl(resources->core_pm_base + 0xA8);
|
||||
mpu_grpsel = readl(resources->core_pm_base + 0xA4);
|
||||
if (enable) {
|
||||
iva2_grpsel |= OMAP3430_GRPSEL_MCBSP1_MASK;
|
||||
mpu_grpsel &= ~OMAP3430_GRPSEL_MCBSP1_MASK;
|
||||
|
@ -495,8 +495,8 @@ void dsp_clk_wakeup_event_ctrl(u32 clock_id, bool enable)
|
|||
mpu_grpsel |= OMAP3430_GRPSEL_MCBSP1_MASK;
|
||||
iva2_grpsel &= ~OMAP3430_GRPSEL_MCBSP1_MASK;
|
||||
}
|
||||
writel(iva2_grpsel, resources->dw_core_pm_base + 0xA8);
|
||||
writel(mpu_grpsel, resources->dw_core_pm_base + 0xA4);
|
||||
writel(iva2_grpsel, resources->core_pm_base + 0xA8);
|
||||
writel(mpu_grpsel, resources->core_pm_base + 0xA4);
|
||||
break;
|
||||
case BPWR_MCBSP2:
|
||||
iva2_grpsel = readl(resources->dw_per_pm_base + 0xA8);
|
||||
|
|
|
@ -61,7 +61,7 @@ int read_ext_dsp_data(struct bridge_dev_context *dev_ctxt,
|
|||
u32 ul_tlb_base_virt = 0;
|
||||
u32 ul_shm_offset_virt = 0;
|
||||
u32 dw_ext_prog_virt_mem;
|
||||
u32 dw_base_addr = dev_context->dw_dsp_ext_base_addr;
|
||||
u32 dw_base_addr = dev_context->dsp_ext_base_addr;
|
||||
bool trace_read = false;
|
||||
|
||||
if (!ul_shm_base_virt) {
|
||||
|
@ -92,7 +92,7 @@ int read_ext_dsp_data(struct bridge_dev_context *dev_ctxt,
|
|||
/* If reading from TRACE, force remap/unmap */
|
||||
if (trace_read && dw_base_addr) {
|
||||
dw_base_addr = 0;
|
||||
dev_context->dw_dsp_ext_base_addr = 0;
|
||||
dev_context->dsp_ext_base_addr = 0;
|
||||
}
|
||||
|
||||
if (!dw_base_addr) {
|
||||
|
@ -148,14 +148,14 @@ int read_ext_dsp_data(struct bridge_dev_context *dev_ctxt,
|
|||
dw_ext_prog_virt_mem -= ul_shm_offset_virt;
|
||||
dw_ext_prog_virt_mem +=
|
||||
(ul_ext_base - ul_dyn_ext_base);
|
||||
dev_context->dw_dsp_ext_base_addr =
|
||||
dev_context->dsp_ext_base_addr =
|
||||
dw_ext_prog_virt_mem;
|
||||
|
||||
/*
|
||||
* This dw_dsp_ext_base_addr will get cleared
|
||||
* This dsp_ext_base_addr will get cleared
|
||||
* only when the board is stopped.
|
||||
*/
|
||||
if (!dev_context->dw_dsp_ext_base_addr)
|
||||
if (!dev_context->dsp_ext_base_addr)
|
||||
status = -EPERM;
|
||||
}
|
||||
|
||||
|
@ -184,7 +184,7 @@ int write_dsp_data(struct bridge_dev_context *dev_context,
|
|||
u32 mem_type)
|
||||
{
|
||||
u32 offset;
|
||||
u32 dw_base_addr = dev_context->dw_dsp_base_addr;
|
||||
u32 dw_base_addr = dev_context->dsp_base_addr;
|
||||
struct cfg_hostres *resources = dev_context->resources;
|
||||
int status = 0;
|
||||
u32 base1, base2, base3;
|
||||
|
@ -195,7 +195,7 @@ int write_dsp_data(struct bridge_dev_context *dev_context,
|
|||
if (!resources)
|
||||
return -EPERM;
|
||||
|
||||
offset = dsp_addr - dev_context->dw_dsp_start_add;
|
||||
offset = dsp_addr - dev_context->dsp_start_add;
|
||||
if (offset < base1) {
|
||||
dw_base_addr = MEM_LINEAR_ADDRESS(resources->dw_mem_base[2],
|
||||
resources->dw_mem_length[2]);
|
||||
|
@ -230,7 +230,7 @@ int write_ext_dsp_data(struct bridge_dev_context *dev_context,
|
|||
u32 ul_num_bytes, u32 mem_type,
|
||||
bool dynamic_load)
|
||||
{
|
||||
u32 dw_base_addr = dev_context->dw_dsp_ext_base_addr;
|
||||
u32 dw_base_addr = dev_context->dsp_ext_base_addr;
|
||||
u32 dw_offset = 0;
|
||||
u8 temp_byte1, temp_byte2;
|
||||
u8 remain_byte[4];
|
||||
|
@ -263,8 +263,8 @@ int write_ext_dsp_data(struct bridge_dev_context *dev_context,
|
|||
if ((dynamic_load || trace_load) && dw_base_addr) {
|
||||
dw_base_addr = 0;
|
||||
MEM_UNMAP_LINEAR_ADDRESS((void *)
|
||||
dev_context->dw_dsp_ext_base_addr);
|
||||
dev_context->dw_dsp_ext_base_addr = 0x0;
|
||||
dev_context->dsp_ext_base_addr);
|
||||
dev_context->dsp_ext_base_addr = 0x0;
|
||||
}
|
||||
if (!dw_base_addr) {
|
||||
if (symbols_reloaded)
|
||||
|
@ -344,14 +344,14 @@ int write_ext_dsp_data(struct bridge_dev_context *dev_context,
|
|||
(ul_ext_base - ul_dyn_ext_base);
|
||||
}
|
||||
|
||||
dev_context->dw_dsp_ext_base_addr =
|
||||
dev_context->dsp_ext_base_addr =
|
||||
(u32) MEM_LINEAR_ADDRESS((void *)
|
||||
dw_ext_prog_virt_mem,
|
||||
ul_ext_end - ul_ext_base);
|
||||
dw_base_addr += dev_context->dw_dsp_ext_base_addr;
|
||||
/* This dw_dsp_ext_base_addr will get cleared only when
|
||||
dw_base_addr += dev_context->dsp_ext_base_addr;
|
||||
/* This dsp_ext_base_addr will get cleared only when
|
||||
* the board is stopped. */
|
||||
if (!dev_context->dw_dsp_ext_base_addr)
|
||||
if (!dev_context->dsp_ext_base_addr)
|
||||
ret = -EPERM;
|
||||
}
|
||||
}
|
||||
|
@ -375,10 +375,10 @@ int write_ext_dsp_data(struct bridge_dev_context *dev_context,
|
|||
*((u32 *) host_buff) = dw_base_addr + dw_offset;
|
||||
}
|
||||
/* Unmap here to force remap for other Ext loads */
|
||||
if ((dynamic_load || trace_load) && dev_context->dw_dsp_ext_base_addr) {
|
||||
if ((dynamic_load || trace_load) && dev_context->dsp_ext_base_addr) {
|
||||
MEM_UNMAP_LINEAR_ADDRESS((void *)
|
||||
dev_context->dw_dsp_ext_base_addr);
|
||||
dev_context->dw_dsp_ext_base_addr = 0x0;
|
||||
dev_context->dsp_ext_base_addr);
|
||||
dev_context->dsp_ext_base_addr = 0x0;
|
||||
}
|
||||
symbols_reloaded = false;
|
||||
return ret;
|
||||
|
@ -401,8 +401,8 @@ int sm_interrupt_dsp(struct bridge_dev_context *dev_context, u16 mb_val)
|
|||
if (!resources)
|
||||
return -EPERM;
|
||||
|
||||
if (dev_context->dw_brd_state == BRD_DSP_HIBERNATION ||
|
||||
dev_context->dw_brd_state == BRD_HIBERNATION) {
|
||||
if (dev_context->brd_state == BRD_DSP_HIBERNATION ||
|
||||
dev_context->brd_state == BRD_HIBERNATION) {
|
||||
#ifdef CONFIG_TIDSPBRIDGE_DVFS
|
||||
if (pdata->dsp_get_opp)
|
||||
opplevel = (*pdata->dsp_get_opp) ();
|
||||
|
@ -439,8 +439,8 @@ int sm_interrupt_dsp(struct bridge_dev_context *dev_context, u16 mb_val)
|
|||
/* Access MMU SYS CONFIG register to generate a short wakeup */
|
||||
temp = readl(resources->dw_dmmu_base + 0x10);
|
||||
|
||||
dev_context->dw_brd_state = BRD_RUNNING;
|
||||
} else if (dev_context->dw_brd_state == BRD_RETENTION) {
|
||||
dev_context->brd_state = BRD_RUNNING;
|
||||
} else if (dev_context->brd_state == BRD_RETENTION) {
|
||||
/* Restart the peripheral clocks */
|
||||
dsp_clock_enable_all(dev_context->dsp_per_clks);
|
||||
}
|
||||
|
|
|
@ -254,7 +254,7 @@ void bridge_deh_notify(struct deh_mgr *deh, int event, int info)
|
|||
}
|
||||
|
||||
/* Filter subsequent notifications when an error occurs */
|
||||
if (dev_context->dw_brd_state != BRD_ERROR) {
|
||||
if (dev_context->brd_state != BRD_ERROR) {
|
||||
ntfy_notify(deh->ntfy_obj, event);
|
||||
#ifdef CONFIG_TIDSPBRIDGE_RECOVERY
|
||||
bridge_recover_schedule();
|
||||
|
@ -262,7 +262,7 @@ void bridge_deh_notify(struct deh_mgr *deh, int event, int info)
|
|||
}
|
||||
|
||||
/* Set the Board state as ERROR */
|
||||
dev_context->dw_brd_state = BRD_ERROR;
|
||||
dev_context->brd_state = BRD_ERROR;
|
||||
/* Disable all the clocks that were enabled by DSP */
|
||||
dsp_clock_disable_all(dev_context->dsp_per_clks);
|
||||
/*
|
||||
|
|
|
@ -171,7 +171,7 @@ struct chnl_irp {
|
|||
u8 *host_user_buf;
|
||||
/* Buffer to be filled/emptied. (System) */
|
||||
u8 *host_sys_buf;
|
||||
u32 dw_arg; /* Issue/Reclaim argument. */
|
||||
u32 arg; /* Issue/Reclaim argument. */
|
||||
u32 dsp_tx_addr; /* Transfer address on DSP side. */
|
||||
u32 byte_size; /* Bytes transferred. */
|
||||
u32 buf_size; /* Actual buffer size when allocated. */
|
||||
|
|
|
@ -43,18 +43,18 @@ struct cfg_hostres {
|
|||
* dw_mem_base + this offset */
|
||||
/*
|
||||
* Info needed by NODE for allocating channels to communicate with RMS:
|
||||
* dw_chnl_offset: Offset of RMS channels. Lower channels are
|
||||
* chnl_offset: Offset of RMS channels. Lower channels are
|
||||
* reserved.
|
||||
* dw_chnl_buf_size: Size of channel buffer to send to RMS
|
||||
* chnl_buf_size: Size of channel buffer to send to RMS
|
||||
* dw_num_chnls: Total number of channels
|
||||
* (including reserved).
|
||||
*/
|
||||
u32 dw_chnl_offset;
|
||||
u32 dw_chnl_buf_size;
|
||||
u32 chnl_offset;
|
||||
u32 chnl_buf_size;
|
||||
u32 dw_num_chnls;
|
||||
void __iomem *dw_per_base;
|
||||
u32 dw_per_pm_base;
|
||||
u32 dw_core_pm_base;
|
||||
u32 core_pm_base;
|
||||
void __iomem *dw_dmmu_base;
|
||||
};
|
||||
|
||||
|
|
|
@ -57,7 +57,7 @@ struct chnl_ioc {
|
|||
u32 byte_size; /* Bytes transferred. */
|
||||
u32 buf_size; /* Actual buffer size in bytes */
|
||||
u32 status; /* Status of IO completion. */
|
||||
u32 dw_arg; /* User argument associated with pbuf. */
|
||||
u32 arg; /* User argument associated with pbuf. */
|
||||
};
|
||||
|
||||
#endif /* CHNLDEFS_ */
|
||||
|
|
|
@ -54,9 +54,9 @@ struct cmm_seginfo {
|
|||
u32 dw_seg_base_pa; /* Start Phys address of SM segment */
|
||||
/* Total size in bytes of segment: DSP+GPP */
|
||||
u32 ul_total_seg_size;
|
||||
u32 dw_gpp_base_pa; /* Start Phys addr of Gpp SM seg */
|
||||
u32 gpp_base_pa; /* Start Phys addr of Gpp SM seg */
|
||||
u32 ul_gpp_size; /* Size of Gpp SM seg in bytes */
|
||||
u32 dw_dsp_base_va; /* DSP virt base byte address */
|
||||
u32 dsp_base_va; /* DSP virt base byte address */
|
||||
u32 ul_dsp_size; /* DSP seg size in bytes */
|
||||
/* # of current GPP allocations from this segment */
|
||||
u32 ul_in_use_cnt;
|
||||
|
@ -79,8 +79,8 @@ struct cmm_info {
|
|||
/* XlatorCreate attributes */
|
||||
struct cmm_xlatorattrs {
|
||||
u32 ul_seg_id; /* segment Id used for SM allocations */
|
||||
u32 dw_dsp_bufs; /* # of DSP-side bufs */
|
||||
u32 dw_dsp_buf_size; /* size of DSP-side bufs in GPP bytes */
|
||||
u32 dsp_bufs; /* # of DSP-side bufs */
|
||||
u32 dsp_buf_size; /* size of DSP-side bufs in GPP bytes */
|
||||
/* Vm base address alloc'd in client process context */
|
||||
void *vm_base;
|
||||
/* dw_vm_size must be >= (dwMaxNumBufs * dwMaxSize) */
|
||||
|
|
|
@ -244,9 +244,9 @@ struct dsp_cbdata {
|
|||
|
||||
/* The dsp_msg structure */
|
||||
struct dsp_msg {
|
||||
u32 dw_cmd;
|
||||
u32 dw_arg1;
|
||||
u32 dw_arg2;
|
||||
u32 cmd;
|
||||
u32 arg1;
|
||||
u32 arg2;
|
||||
};
|
||||
|
||||
/* The dsp_resourcereqmts structure for node's resource requirements */
|
||||
|
@ -368,7 +368,7 @@ struct dsp_processorinfo {
|
|||
|
||||
/* Error information of last DSP exception signalled to the GPP */
|
||||
struct dsp_errorinfo {
|
||||
u32 dw_err_mask;
|
||||
u32 err_mask;
|
||||
u32 dw_val1;
|
||||
u32 dw_val2;
|
||||
u32 dw_val3;
|
||||
|
|
|
@ -68,7 +68,7 @@ union trapped_args {
|
|||
|
||||
struct {
|
||||
void *hprocessor;
|
||||
u32 dw_cmd;
|
||||
u32 cmd;
|
||||
struct dsp_cbdata __user *pargs;
|
||||
} args_proc_ctrl;
|
||||
|
||||
|
@ -293,7 +293,7 @@ union trapped_args {
|
|||
u8 *pbuffer;
|
||||
u32 dw_bytes;
|
||||
u32 dw_buf_size;
|
||||
u32 dw_arg;
|
||||
u32 arg;
|
||||
} args_strm_issue;
|
||||
|
||||
struct {
|
||||
|
|
|
@ -66,10 +66,10 @@ struct cmm_allocator { /* sma */
|
|||
u32 ul_sm_size; /* Size of SM block in bytes */
|
||||
unsigned int dw_vm_base; /* Start of VM block. (Dev driver
|
||||
* context for 'sma') */
|
||||
u32 dw_dsp_phys_addr_offset; /* DSP PA to GPP PA offset for this
|
||||
u32 dsp_phys_addr_offset; /* DSP PA to GPP PA offset for this
|
||||
* SM space */
|
||||
s8 c_factor; /* DSPPa to GPPPa Conversion Factor */
|
||||
unsigned int dw_dsp_base; /* DSP virt base byte address */
|
||||
unsigned int dsp_base; /* DSP virt base byte address */
|
||||
u32 ul_dsp_size; /* DSP seg size in bytes */
|
||||
struct cmm_object *hcmm_mgr; /* back ref to parent mgr */
|
||||
/* node list of available memory */
|
||||
|
@ -119,8 +119,8 @@ static struct cmm_attrs cmm_dfltalctattrs = {
|
|||
static struct cmm_xlatorattrs cmm_dfltxlatorattrs = {
|
||||
/* ul_seg_id, does not have to match cmm_dfltalctattrs ul_seg_id */
|
||||
1,
|
||||
0, /* dw_dsp_bufs */
|
||||
0, /* dw_dsp_buf_size */
|
||||
0, /* dsp_bufs */
|
||||
0, /* dsp_buf_size */
|
||||
NULL, /* vm_base */
|
||||
0, /* dw_vm_size */
|
||||
};
|
||||
|
@ -442,12 +442,12 @@ int cmm_get_info(struct cmm_object *hcmm_mgr,
|
|||
altr->shm_base - altr->ul_dsp_size;
|
||||
cmm_info_obj->seg_info[ul_seg - 1].ul_total_seg_size =
|
||||
altr->ul_dsp_size + altr->ul_sm_size;
|
||||
cmm_info_obj->seg_info[ul_seg - 1].dw_gpp_base_pa =
|
||||
cmm_info_obj->seg_info[ul_seg - 1].gpp_base_pa =
|
||||
altr->shm_base;
|
||||
cmm_info_obj->seg_info[ul_seg - 1].ul_gpp_size =
|
||||
altr->ul_sm_size;
|
||||
cmm_info_obj->seg_info[ul_seg - 1].dw_dsp_base_va =
|
||||
altr->dw_dsp_base;
|
||||
cmm_info_obj->seg_info[ul_seg - 1].dsp_base_va =
|
||||
altr->dsp_base;
|
||||
cmm_info_obj->seg_info[ul_seg - 1].ul_dsp_size =
|
||||
altr->ul_dsp_size;
|
||||
cmm_info_obj->seg_info[ul_seg - 1].dw_seg_base_va =
|
||||
|
@ -540,9 +540,9 @@ int cmm_register_gppsm_seg(struct cmm_object *hcmm_mgr,
|
|||
psma->shm_base = dw_gpp_base_pa; /* SM Base phys */
|
||||
psma->ul_sm_size = ul_size; /* SM segment size in bytes */
|
||||
psma->dw_vm_base = gpp_base_va;
|
||||
psma->dw_dsp_phys_addr_offset = dsp_addr_offset;
|
||||
psma->dsp_phys_addr_offset = dsp_addr_offset;
|
||||
psma->c_factor = c_factor;
|
||||
psma->dw_dsp_base = dw_dsp_base;
|
||||
psma->dsp_base = dw_dsp_base;
|
||||
psma->ul_dsp_size = ul_dsp_size;
|
||||
if (psma->dw_vm_base == 0) {
|
||||
status = -EPERM;
|
||||
|
@ -994,14 +994,14 @@ void *cmm_xlator_translate(struct cmm_xlatorobject *xlator, void *paddr,
|
|||
dw_addr_xlate =
|
||||
GPPPA2DSPPA((allocator->shm_base - allocator->ul_dsp_size),
|
||||
dw_addr_xlate,
|
||||
allocator->dw_dsp_phys_addr_offset *
|
||||
allocator->dsp_phys_addr_offset *
|
||||
allocator->c_factor);
|
||||
} else if (xtype == CMM_DSPPA2PA) {
|
||||
/* Got DSP Pa, convert to GPP Pa */
|
||||
dw_addr_xlate =
|
||||
DSPPA2GPPPA(allocator->shm_base - allocator->ul_dsp_size,
|
||||
dw_addr_xlate,
|
||||
allocator->dw_dsp_phys_addr_offset *
|
||||
allocator->dsp_phys_addr_offset *
|
||||
allocator->c_factor);
|
||||
}
|
||||
loop_cont:
|
||||
|
|
|
@ -639,7 +639,7 @@ u32 procwrap_ctrl(union trapped_args *args, void *pr_ctxt)
|
|||
}
|
||||
if (!status) {
|
||||
status = proc_ctrl(hprocessor,
|
||||
args->args_proc_ctrl.dw_cmd,
|
||||
args->args_proc_ctrl.cmd,
|
||||
(struct dsp_cbdata *)pargs);
|
||||
}
|
||||
|
||||
|
@ -1717,7 +1717,7 @@ u32 strmwrap_issue(union trapped_args *args, void *pr_ctxt)
|
|||
args->args_strm_issue.pbuffer,
|
||||
args->args_strm_issue.dw_bytes,
|
||||
args->args_strm_issue.dw_buf_size,
|
||||
args->args_strm_issue.dw_arg);
|
||||
args->args_strm_issue.arg);
|
||||
|
||||
return status;
|
||||
}
|
||||
|
|
|
@ -699,10 +699,10 @@ static int request_bridge_resources(struct cfg_hostres *res)
|
|||
host_res->birq_registers = 0;
|
||||
host_res->birq_attrib = 0;
|
||||
host_res->dw_offset_for_monitor = 0;
|
||||
host_res->dw_chnl_offset = 0;
|
||||
host_res->chnl_offset = 0;
|
||||
/* CHNL_MAXCHANNELS */
|
||||
host_res->dw_num_chnls = CHNL_MAXCHANNELS;
|
||||
host_res->dw_chnl_buf_size = 0x400;
|
||||
host_res->chnl_buf_size = 0x400;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
@ -741,7 +741,7 @@ int drv_request_bridge_res_dsp(void **phost_resources)
|
|||
OMAP_PER_CM_SIZE);
|
||||
host_res->dw_per_pm_base = (u32) ioremap(OMAP_PER_PRM_BASE,
|
||||
OMAP_PER_PRM_SIZE);
|
||||
host_res->dw_core_pm_base = (u32) ioremap(OMAP_CORE_PRM_BASE,
|
||||
host_res->core_pm_base = (u32) ioremap(OMAP_CORE_PRM_BASE,
|
||||
OMAP_CORE_PRM_SIZE);
|
||||
host_res->dw_dmmu_base = ioremap(OMAP_DMMU_BASE,
|
||||
OMAP_DMMU_SIZE);
|
||||
|
@ -783,10 +783,10 @@ int drv_request_bridge_res_dsp(void **phost_resources)
|
|||
host_res->birq_registers = 0;
|
||||
host_res->birq_attrib = 0;
|
||||
host_res->dw_offset_for_monitor = 0;
|
||||
host_res->dw_chnl_offset = 0;
|
||||
host_res->chnl_offset = 0;
|
||||
/* CHNL_MAXCHANNELS */
|
||||
host_res->dw_num_chnls = CHNL_MAXCHANNELS;
|
||||
host_res->dw_chnl_buf_size = 0x400;
|
||||
host_res->chnl_buf_size = 0x400;
|
||||
dw_buff_size = sizeof(struct cfg_hostres);
|
||||
}
|
||||
*phost_resources = host_res;
|
||||
|
|
|
@ -1795,12 +1795,12 @@ int node_get_message(struct node_object *hnode,
|
|||
status =
|
||||
(*intf_fxns->pfn_msg_get) (hnode->msg_queue_obj, message, utimeout);
|
||||
/* Check if message contains SM descriptor */
|
||||
if (status || !(message->dw_cmd & DSP_RMSBUFDESC))
|
||||
if (status || !(message->cmd & DSP_RMSBUFDESC))
|
||||
goto func_end;
|
||||
|
||||
/* Translate DSP byte addr to GPP Va. */
|
||||
tmp_buf = cmm_xlator_translate(hnode->xlator,
|
||||
(void *)(message->dw_arg1 *
|
||||
(void *)(message->arg1 *
|
||||
hnode->hnode_mgr->
|
||||
udsp_word_size), CMM_DSPPA2PA);
|
||||
if (tmp_buf != NULL) {
|
||||
|
@ -1809,8 +1809,8 @@ int node_get_message(struct node_object *hnode,
|
|||
CMM_PA2VA);
|
||||
if (tmp_buf != NULL) {
|
||||
/* Adjust SM size in msg */
|
||||
message->dw_arg1 = (u32) tmp_buf;
|
||||
message->dw_arg2 *= hnode->hnode_mgr->udsp_word_size;
|
||||
message->arg1 = (u32) tmp_buf;
|
||||
message->arg2 *= hnode->hnode_mgr->udsp_word_size;
|
||||
} else {
|
||||
status = -ESRCH;
|
||||
}
|
||||
|
@ -2100,19 +2100,19 @@ int node_put_message(struct node_object *hnode,
|
|||
/* assign pmsg values to new msg */
|
||||
new_msg = *pmsg;
|
||||
/* Now, check if message contains a SM buffer descriptor */
|
||||
if (pmsg->dw_cmd & DSP_RMSBUFDESC) {
|
||||
if (pmsg->cmd & DSP_RMSBUFDESC) {
|
||||
/* Translate GPP Va to DSP physical buf Ptr. */
|
||||
tmp_buf = cmm_xlator_translate(hnode->xlator,
|
||||
(void *)new_msg.dw_arg1,
|
||||
(void *)new_msg.arg1,
|
||||
CMM_VA2DSPPA);
|
||||
if (tmp_buf != NULL) {
|
||||
/* got translation, convert to MAUs in msg */
|
||||
if (hnode->hnode_mgr->udsp_word_size != 0) {
|
||||
new_msg.dw_arg1 =
|
||||
new_msg.arg1 =
|
||||
(u32) tmp_buf /
|
||||
hnode->hnode_mgr->udsp_word_size;
|
||||
/* MAUs */
|
||||
new_msg.dw_arg2 /= hnode->hnode_mgr->
|
||||
new_msg.arg2 /= hnode->hnode_mgr->
|
||||
udsp_word_size;
|
||||
} else {
|
||||
pr_err("%s: udsp_word_size is zero!\n",
|
||||
|
@ -2378,10 +2378,10 @@ int node_terminate(struct node_object *hnode, int *pstatus)
|
|||
goto func_cont;
|
||||
}
|
||||
|
||||
msg.dw_cmd = RMS_EXIT;
|
||||
msg.dw_arg1 = hnode->node_env;
|
||||
killmsg.dw_cmd = RMS_KILLTASK;
|
||||
killmsg.dw_arg1 = hnode->node_env;
|
||||
msg.cmd = RMS_EXIT;
|
||||
msg.arg1 = hnode->node_env;
|
||||
killmsg.cmd = RMS_KILLTASK;
|
||||
killmsg.arg1 = hnode->node_env;
|
||||
intf_fxns = hnode_mgr->intf_fxns;
|
||||
|
||||
if (hnode->utimeout > MAXTIMEOUT)
|
||||
|
@ -2902,8 +2902,8 @@ static int get_proc_props(struct node_mgr *hnode_mgr,
|
|||
host_res = pbridge_context->resources;
|
||||
if (!host_res)
|
||||
return -EPERM;
|
||||
hnode_mgr->ul_chnl_offset = host_res->dw_chnl_offset;
|
||||
hnode_mgr->ul_chnl_buf_size = host_res->dw_chnl_buf_size;
|
||||
hnode_mgr->ul_chnl_offset = host_res->chnl_offset;
|
||||
hnode_mgr->ul_chnl_buf_size = host_res->chnl_buf_size;
|
||||
hnode_mgr->ul_num_chnls = host_res->dw_num_chnls;
|
||||
|
||||
/*
|
||||
|
|
|
@ -639,7 +639,7 @@ int strm_reclaim(struct strm_object *stream_obj, u8 ** buf_ptr,
|
|||
if (buff_size)
|
||||
*buff_size = chnl_ioc_obj.buf_size;
|
||||
|
||||
*pdw_arg = chnl_ioc_obj.dw_arg;
|
||||
*pdw_arg = chnl_ioc_obj.arg;
|
||||
if (!CHNL_IS_IO_COMPLETE(chnl_ioc_obj)) {
|
||||
if (CHNL_IS_TIMED_OUT(chnl_ioc_obj)) {
|
||||
status = -ETIME;
|
||||
|
|
Loading…
Reference in a new issue