net/fec: add dual fec support for mx28
This patch is to add mx28 dual fec support. Here are some key notes for mx28 fec controller. - The mx28 fec controller naming ENET-MAC is a different IP from FEC used on other i.mx variants. But they are basically compatible on software interface, so it's possible to share the same driver. - ENET-MAC design on mx28 made an improper assumption that it runs on a big-endian system. As the result, driver has to swap every frame going to and coming from the controller. - The external phys can only be configured by fec0, which means fec1 can not work independently and both phys need to be configured by mii_bus attached on fec0. - ENET-MAC reset will get mac address registers reset too. - ENET-MAC MII/RMII mode and 10M/100M speed are configured differently FEC. - ETHER_EN bit must be set to get ENET-MAC interrupt work. Signed-off-by: Shawn Guo <shawn.guo@freescale.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Shawn Guo
David S. Miller
parent
bcc67771ed
commit
b5680e0b59
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@ -1944,18 +1944,19 @@ config 68360_ENET
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config FEC
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bool "FEC ethernet controller (of ColdFire and some i.MX CPUs)"
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depends on M523x || M527x || M5272 || M528x || M520x || M532x || \
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MACH_MX27 || ARCH_MX35 || ARCH_MX25 || ARCH_MX5
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MACH_MX27 || ARCH_MX35 || ARCH_MX25 || ARCH_MX5 || SOC_IMX28
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select PHYLIB
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help
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Say Y here if you want to use the built-in 10/100 Fast ethernet
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controller on some Motorola ColdFire and Freescale i.MX processors.
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config FEC2
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bool "Second FEC ethernet controller (on some ColdFire CPUs)"
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bool "Second FEC ethernet controller"
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depends on FEC
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help
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Say Y here if you want to use the second built-in 10/100 Fast
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ethernet controller on some Motorola ColdFire processors.
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ethernet controller on some Motorola ColdFire and Freescale
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i.MX processors.
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config FEC_MPC52xx
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tristate "MPC52xx FEC driver"
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@ -17,6 +17,8 @@
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*
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* Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be)
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* Copyright (c) 2004-2006 Macq Electronique SA.
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*
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* Copyright (C) 2010 Freescale Semiconductor, Inc.
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*/
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#include <linux/module.h>
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@ -45,20 +47,36 @@
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#include <asm/cacheflush.h>
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#ifndef CONFIG_ARCH_MXC
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#ifndef CONFIG_ARM
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#include <asm/coldfire.h>
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#include <asm/mcfsim.h>
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#endif
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#include "fec.h"
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#ifdef CONFIG_ARCH_MXC
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#include <mach/hardware.h>
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#if defined(CONFIG_ARCH_MXC) || defined(CONFIG_SOC_IMX28)
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#define FEC_ALIGNMENT 0xf
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#else
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#define FEC_ALIGNMENT 0x3
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#endif
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#define DRIVER_NAME "fec"
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/* Controller is ENET-MAC */
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#define FEC_QUIRK_ENET_MAC (1 << 0)
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/* Controller needs driver to swap frame */
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#define FEC_QUIRK_SWAP_FRAME (1 << 1)
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static struct platform_device_id fec_devtype[] = {
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{
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.name = DRIVER_NAME,
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.driver_data = 0,
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}, {
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.name = "imx28-fec",
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.driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_SWAP_FRAME,
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}
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};
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static unsigned char macaddr[ETH_ALEN];
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module_param_array(macaddr, byte, NULL, 0);
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MODULE_PARM_DESC(macaddr, "FEC Ethernet MAC address");
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@ -129,7 +147,8 @@ MODULE_PARM_DESC(macaddr, "FEC Ethernet MAC address");
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* account when setting it.
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*/
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#if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
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defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARCH_MXC)
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defined(CONFIG_M520x) || defined(CONFIG_M532x) || \
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defined(CONFIG_ARCH_MXC) || defined(CONFIG_SOC_IMX28)
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#define OPT_FRAME_SIZE (PKT_MAXBUF_SIZE << 16)
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#else
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#define OPT_FRAME_SIZE 0
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@ -208,10 +227,23 @@ static void fec_stop(struct net_device *dev);
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/* Transmitter timeout */
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#define TX_TIMEOUT (2 * HZ)
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static void *swap_buffer(void *bufaddr, int len)
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{
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int i;
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unsigned int *buf = bufaddr;
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for (i = 0; i < (len + 3) / 4; i++, buf++)
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*buf = cpu_to_be32(*buf);
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return bufaddr;
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}
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static netdev_tx_t
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fec_enet_start_xmit(struct sk_buff *skb, struct net_device *dev)
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{
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struct fec_enet_private *fep = netdev_priv(dev);
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const struct platform_device_id *id_entry =
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platform_get_device_id(fep->pdev);
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struct bufdesc *bdp;
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void *bufaddr;
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unsigned short status;
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@ -256,6 +288,14 @@ fec_enet_start_xmit(struct sk_buff *skb, struct net_device *dev)
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bufaddr = fep->tx_bounce[index];
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}
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/*
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* Some design made an incorrect assumption on endian mode of
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* the system that it's running on. As the result, driver has to
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* swap every frame going to and coming from the controller.
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*/
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if (id_entry->driver_data & FEC_QUIRK_SWAP_FRAME)
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swap_buffer(bufaddr, skb->len);
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/* Save skb pointer */
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fep->tx_skbuff[fep->skb_cur] = skb;
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@ -424,6 +464,8 @@ static void
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fec_enet_rx(struct net_device *dev)
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{
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struct fec_enet_private *fep = netdev_priv(dev);
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const struct platform_device_id *id_entry =
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platform_get_device_id(fep->pdev);
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struct bufdesc *bdp;
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unsigned short status;
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struct sk_buff *skb;
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@ -487,6 +529,9 @@ fec_enet_rx(struct net_device *dev)
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dma_unmap_single(NULL, bdp->cbd_bufaddr, bdp->cbd_datlen,
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DMA_FROM_DEVICE);
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if (id_entry->driver_data & FEC_QUIRK_SWAP_FRAME)
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swap_buffer(data, pkt_len);
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/* This does 16 byte alignment, exactly what we need.
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* The packet length includes FCS, but we don't want to
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* include that when passing upstream as it messes up
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@ -689,6 +734,7 @@ static int fec_enet_mii_probe(struct net_device *dev)
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char mdio_bus_id[MII_BUS_ID_SIZE];
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char phy_name[MII_BUS_ID_SIZE + 3];
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int phy_id;
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int dev_id = fep->pdev->id;
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fep->phy_dev = NULL;
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@ -700,6 +746,8 @@ static int fec_enet_mii_probe(struct net_device *dev)
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continue;
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if (fep->mii_bus->phy_map[phy_id]->phy_id == 0)
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continue;
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if (dev_id--)
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continue;
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strncpy(mdio_bus_id, fep->mii_bus->id, MII_BUS_ID_SIZE);
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break;
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}
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@ -737,10 +785,35 @@ static int fec_enet_mii_probe(struct net_device *dev)
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static int fec_enet_mii_init(struct platform_device *pdev)
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{
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static struct mii_bus *fec0_mii_bus;
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struct net_device *dev = platform_get_drvdata(pdev);
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struct fec_enet_private *fep = netdev_priv(dev);
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const struct platform_device_id *id_entry =
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platform_get_device_id(fep->pdev);
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int err = -ENXIO, i;
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/*
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* The dual fec interfaces are not equivalent with enet-mac.
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* Here are the differences:
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*
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* - fec0 supports MII & RMII modes while fec1 only supports RMII
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* - fec0 acts as the 1588 time master while fec1 is slave
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* - external phys can only be configured by fec0
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*
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* That is to say fec1 can not work independently. It only works
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* when fec0 is working. The reason behind this design is that the
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* second interface is added primarily for Switch mode.
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*
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* Because of the last point above, both phys are attached on fec0
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* mdio interface in board design, and need to be configured by
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* fec0 mii_bus.
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*/
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if ((id_entry->driver_data & FEC_QUIRK_ENET_MAC) && pdev->id) {
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/* fec1 uses fec0 mii_bus */
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fep->mii_bus = fec0_mii_bus;
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return 0;
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}
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fep->mii_timeout = 0;
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/*
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@ -777,6 +850,10 @@ static int fec_enet_mii_init(struct platform_device *pdev)
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if (mdiobus_register(fep->mii_bus))
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goto err_out_free_mdio_irq;
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/* save fec0 mii_bus */
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if (id_entry->driver_data & FEC_QUIRK_ENET_MAC)
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fec0_mii_bus = fep->mii_bus;
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return 0;
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err_out_free_mdio_irq:
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@ -1148,12 +1225,25 @@ static void
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fec_restart(struct net_device *dev, int duplex)
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{
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struct fec_enet_private *fep = netdev_priv(dev);
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const struct platform_device_id *id_entry =
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platform_get_device_id(fep->pdev);
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int i;
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u32 val, temp_mac[2];
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/* Whack a reset. We should wait for this. */
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writel(1, fep->hwp + FEC_ECNTRL);
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udelay(10);
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/*
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* enet-mac reset will reset mac address registers too,
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* so need to reconfigure it.
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*/
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if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
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memcpy(&temp_mac, dev->dev_addr, ETH_ALEN);
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writel(cpu_to_be32(temp_mac[0]), fep->hwp + FEC_ADDR_LOW);
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writel(cpu_to_be32(temp_mac[1]), fep->hwp + FEC_ADDR_HIGH);
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}
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/* Clear any outstanding interrupt. */
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writel(0xffc00000, fep->hwp + FEC_IEVENT);
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@ -1200,20 +1290,45 @@ fec_restart(struct net_device *dev, int duplex)
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/* Set MII speed */
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writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
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/*
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* The phy interface and speed need to get configured
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* differently on enet-mac.
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*/
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if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
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val = readl(fep->hwp + FEC_R_CNTRL);
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/* MII or RMII */
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if (fep->phy_interface == PHY_INTERFACE_MODE_RMII)
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val |= (1 << 8);
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else
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val &= ~(1 << 8);
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/* 10M or 100M */
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if (fep->phy_dev && fep->phy_dev->speed == SPEED_100)
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val &= ~(1 << 9);
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else
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val |= (1 << 9);
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writel(val, fep->hwp + FEC_R_CNTRL);
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} else {
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#ifdef FEC_MIIGSK_ENR
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if (fep->phy_interface == PHY_INTERFACE_MODE_RMII) {
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/* disable the gasket and wait */
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writel(0, fep->hwp + FEC_MIIGSK_ENR);
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while (readl(fep->hwp + FEC_MIIGSK_ENR) & 4)
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udelay(1);
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if (fep->phy_interface == PHY_INTERFACE_MODE_RMII) {
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/* disable the gasket and wait */
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writel(0, fep->hwp + FEC_MIIGSK_ENR);
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while (readl(fep->hwp + FEC_MIIGSK_ENR) & 4)
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udelay(1);
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/* configure the gasket: RMII, 50 MHz, no loopback, no echo */
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writel(1, fep->hwp + FEC_MIIGSK_CFGR);
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/*
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* configure the gasket:
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* RMII, 50 MHz, no loopback, no echo
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*/
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writel(1, fep->hwp + FEC_MIIGSK_CFGR);
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/* re-enable the gasket */
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writel(2, fep->hwp + FEC_MIIGSK_ENR);
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}
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/* re-enable the gasket */
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writel(2, fep->hwp + FEC_MIIGSK_ENR);
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}
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#endif
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}
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/* And last, enable the transmit and receive processing */
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writel(2, fep->hwp + FEC_ECNTRL);
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@ -1410,12 +1525,13 @@ static const struct dev_pm_ops fec_pm_ops = {
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static struct platform_driver fec_driver = {
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.driver = {
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.name = "fec",
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.name = DRIVER_NAME,
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.owner = THIS_MODULE,
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#ifdef CONFIG_PM
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.pm = &fec_pm_ops,
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#endif
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},
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.id_table = fec_devtype,
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.probe = fec_probe,
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.remove = __devexit_p(fec_drv_remove),
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};
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@ -14,7 +14,8 @@
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/****************************************************************************/
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#if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
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defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARCH_MXC)
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defined(CONFIG_M520x) || defined(CONFIG_M532x) || \
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defined(CONFIG_ARCH_MXC) || defined(CONFIG_SOC_IMX28)
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/*
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* Just figures, Motorola would have to change the offsets for
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* registers in the same peripheral device on different models
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@ -78,7 +79,7 @@
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/*
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* Define the buffer descriptor structure.
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*/
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#ifdef CONFIG_ARCH_MXC
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#if defined(CONFIG_ARCH_MXC) || defined(CONFIG_SOC_IMX28)
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struct bufdesc {
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unsigned short cbd_datlen; /* Data length */
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unsigned short cbd_sc; /* Control and status info */
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