[ARM] 4584/2: ARMv7: Add Advanced SIMD (NEON) extension support
This patch enables the use of the Advanced SIMD (NEON) extension on ARMv7. The NEON technology is a 64/128-bit hybrid SIMD architecture for accelerating the performance of multimedia and signal processing applications. The extension shares the registers with the VFP unit and enabling/disabling and saving/restoring follow the same rules. In addition, there are instructions that do not have the appropriate CP number encoded, the checks being made in the call_fpe function. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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@ -966,6 +966,13 @@ config VFPv3
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depends on VFP
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default y if CPU_V7
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config NEON
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bool "Advanced SIMD (NEON) Extension support"
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depends on VFPv3 && CPU_V7
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help
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Say Y to include support code for NEON, the ARMv7 Advanced SIMD
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Extension.
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endmenu
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menu "Userspace binary formats"
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@ -480,6 +480,13 @@ __und_usr:
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* co-processor instructions. However, we have to watch out
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* for the ARM6/ARM7 SWI bug.
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*
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* NEON is a special case that has to be handled here. Not all
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* NEON instructions are co-processor instructions, so we have
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* to make a special case of checking for them. Plus, there's
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* five groups of them, so we have a table of mask/opcode pairs
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* to check against, and if any match then we branch off into the
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* NEON handler code.
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*
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* Emulators may wish to make use of the following registers:
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* r0 = instruction opcode.
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* r2 = PC+4
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@ -488,6 +495,23 @@ __und_usr:
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* lr = unrecognised instruction return address
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*/
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call_fpe:
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#ifdef CONFIG_NEON
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adr r6, .LCneon_opcodes
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2:
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ldr r7, [r6], #4 @ mask value
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cmp r7, #0 @ end mask?
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beq 1f
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and r8, r0, r7
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ldr r7, [r6], #4 @ opcode bits matching in mask
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cmp r8, r7 @ NEON instruction?
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bne 2b
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get_thread_info r10
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mov r7, #1
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strb r7, [r10, #TI_USED_CP + 10] @ mark CP#10 as used
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strb r7, [r10, #TI_USED_CP + 11] @ mark CP#11 as used
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b do_vfp @ let VFP handler handle this
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1:
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#endif
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tst r0, #0x08000000 @ only CDP/CPRT/LDC/STC have bit 27
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#if defined(CONFIG_CPU_ARM610) || defined(CONFIG_CPU_ARM710)
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and r8, r0, #0x0f000000 @ mask out op-code bits
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@ -537,6 +561,20 @@ call_fpe:
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mov pc, lr @ CP#14 (Debug)
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mov pc, lr @ CP#15 (Control)
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#ifdef CONFIG_NEON
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.align 6
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.LCneon_opcodes:
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.word 0xfe000000 @ mask
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.word 0xf2000000 @ opcode
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.word 0xff100000 @ mask
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.word 0xf4000000 @ opcode
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.word 0x00000000 @ mask
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.word 0x00000000 @ opcode
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#endif
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do_fpe:
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enable_irq
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ldr r4, .LCfp
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