tg3: Add coalesce parameters for msix vectors
This patch adds code to tune the coalescing parameters for the other msix vectors. Signed-off-by: Matt Carlson <mcarlson@broadcom.com> Reviewed-by: Benjamin Li <benli@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -6876,24 +6876,63 @@ static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
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static void __tg3_set_rx_mode(struct net_device *);
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static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
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{
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tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
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tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
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tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
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tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
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if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
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tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
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tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
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int i;
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if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSIX)) {
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tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
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tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
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tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
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tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
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tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
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tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
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} else {
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tw32(HOSTCC_TXCOL_TICKS, 0);
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tw32(HOSTCC_TXMAX_FRAMES, 0);
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tw32(HOSTCC_TXCOAL_MAXF_INT, 0);
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tw32(HOSTCC_RXCOL_TICKS, 0);
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tw32(HOSTCC_RXMAX_FRAMES, 0);
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tw32(HOSTCC_RXCOAL_MAXF_INT, 0);
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}
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tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
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tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
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if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
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u32 val = ec->stats_block_coalesce_usecs;
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tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
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tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
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if (!netif_carrier_ok(tp->dev))
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val = 0;
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tw32(HOSTCC_STAT_COAL_TICKS, val);
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}
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for (i = 0; i < tp->irq_cnt - 1; i++) {
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u32 reg;
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reg = HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18;
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tw32(reg, ec->rx_coalesce_usecs);
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reg = HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18;
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tw32(reg, ec->tx_coalesce_usecs);
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reg = HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18;
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tw32(reg, ec->rx_max_coalesced_frames);
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reg = HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18;
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tw32(reg, ec->tx_max_coalesced_frames);
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reg = HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18;
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tw32(reg, ec->rx_max_coalesced_frames_irq);
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reg = HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18;
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tw32(reg, ec->tx_max_coalesced_frames_irq);
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}
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for (; i < tp->irq_max - 1; i++) {
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tw32(HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18, 0);
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tw32(HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18, 0);
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tw32(HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18, 0);
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tw32(HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18, 0);
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tw32(HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
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tw32(HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
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}
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}
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/* tp->lock is held. */
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@ -1119,7 +1119,15 @@
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#define HOSTCC_SND_CON_IDX_14 0x00003cf8
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#define HOSTCC_SND_CON_IDX_15 0x00003cfc
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#define HOSTCC_STATBLCK_RING1 0x00003d00
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/* 0x3d04 --> 0x4000 unused */
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/* 0x3d00 --> 0x3d80 unused */
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#define HOSTCC_RXCOL_TICKS_VEC1 0x00003d80
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#define HOSTCC_TXCOL_TICKS_VEC1 0x00003d84
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#define HOSTCC_RXMAX_FRAMES_VEC1 0x00003d88
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#define HOSTCC_TXMAX_FRAMES_VEC1 0x00003d8c
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#define HOSTCC_RXCOAL_MAXF_INT_VEC1 0x00003d90
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#define HOSTCC_TXCOAL_MAXF_INT_VEC1 0x00003d94
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/* 0x3d98 --> 0x4000 unused */
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/* Memory arbiter control registers */
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#define MEMARB_MODE 0x00004000
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