drm/i915: Make own struct for execlist items
Engine's execlist related items have been increasing to a point where a separate struct is warranted. Carve execlist specific items to a dedicated struct to add clarity. v2: add kerneldoc and fix whitespace (Joonas, Chris) v3: csb_mmio changes, rebase v4: s/\b(el|execlist)\b/execlists/ (Joonas) Suggested-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com> Acked-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Reviewed-by: Michał Winiarski <michal.winiarski@intel.com> (v3) Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> (v3) Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20170922124307.10914-1-mika.kuoppala@intel.com
This commit is contained in:
parent
d27ffc1d00
commit
b620e87021
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@ -3323,7 +3323,7 @@ static int i915_engine_info(struct seq_file *m, void *unused)
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read = GEN8_CSB_READ_PTR(ptr);
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write = GEN8_CSB_WRITE_PTR(ptr);
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seq_printf(m, "\tExeclist CSB read %d [%d cached], write %d [%d from hws], interrupt posted? %s\n",
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read, engine->csb_head,
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read, engine->execlists.csb_head,
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write,
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intel_read_status_page(engine, intel_hws_csb_write_index(engine->i915)),
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yesno(test_bit(ENGINE_IRQ_EXECLIST,
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@ -3345,10 +3345,10 @@ static int i915_engine_info(struct seq_file *m, void *unused)
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}
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rcu_read_lock();
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for (idx = 0; idx < ARRAY_SIZE(engine->execlist_port); idx++) {
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for (idx = 0; idx < ARRAY_SIZE(engine->execlists.port); idx++) {
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unsigned int count;
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rq = port_unpack(&engine->execlist_port[idx],
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rq = port_unpack(&engine->execlists.port[idx],
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&count);
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if (rq) {
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seq_printf(m, "\t\tELSP[%d] count=%d, ",
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@ -3362,7 +3362,7 @@ static int i915_engine_info(struct seq_file *m, void *unused)
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rcu_read_unlock();
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spin_lock_irq(&engine->timeline->lock);
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for (rb = engine->execlist_first; rb; rb = rb_next(rb)){
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for (rb = engine->execlists.first; rb; rb = rb_next(rb)) {
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struct i915_priolist *p =
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rb_entry(rb, typeof(*p), node);
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@ -2815,8 +2815,8 @@ i915_gem_reset_prepare_engine(struct intel_engine_cs *engine)
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* Turning off the engine->irq_tasklet until the reset is over
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* prevents the race.
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*/
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tasklet_kill(&engine->irq_tasklet);
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tasklet_disable(&engine->irq_tasklet);
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tasklet_kill(&engine->execlists.irq_tasklet);
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tasklet_disable(&engine->execlists.irq_tasklet);
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if (engine->irq_seqno_barrier)
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engine->irq_seqno_barrier(engine);
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@ -2995,7 +2995,7 @@ void i915_gem_reset(struct drm_i915_private *dev_priv)
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void i915_gem_reset_finish_engine(struct intel_engine_cs *engine)
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{
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tasklet_enable(&engine->irq_tasklet);
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tasklet_enable(&engine->execlists.irq_tasklet);
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kthread_unpark(engine->breadcrumbs.signaler);
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}
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@ -1327,10 +1327,10 @@ static void engine_record_requests(struct intel_engine_cs *engine,
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static void error_record_engine_execlists(struct intel_engine_cs *engine,
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struct drm_i915_error_engine *ee)
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{
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const struct execlist_port *port = engine->execlist_port;
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const struct execlist_port *port = engine->execlists.port;
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unsigned int n;
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for (n = 0; n < ARRAY_SIZE(engine->execlist_port); n++) {
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for (n = 0; n < ARRAY_SIZE(engine->execlists.port); n++) {
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struct drm_i915_gem_request *rq = port_request(&port[n]);
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if (!rq)
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@ -494,11 +494,12 @@ static void i915_guc_submit(struct intel_engine_cs *engine)
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struct drm_i915_private *dev_priv = engine->i915;
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struct intel_guc *guc = &dev_priv->guc;
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struct i915_guc_client *client = guc->execbuf_client;
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struct execlist_port *port = engine->execlist_port;
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unsigned int engine_id = engine->id;
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struct intel_engine_execlists * const execlists = &engine->execlists;
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struct execlist_port *port = execlists->port;
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const unsigned int engine_id = engine->id;
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unsigned int n;
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for (n = 0; n < ARRAY_SIZE(engine->execlist_port); n++) {
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for (n = 0; n < ARRAY_SIZE(execlists->port); n++) {
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struct drm_i915_gem_request *rq;
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unsigned int count;
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@ -558,7 +559,8 @@ static void port_assign(struct execlist_port *port,
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static void i915_guc_dequeue(struct intel_engine_cs *engine)
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{
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struct execlist_port *port = engine->execlist_port;
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struct intel_engine_execlists * const execlists = &engine->execlists;
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struct execlist_port *port = execlists->port;
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struct drm_i915_gem_request *last = NULL;
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bool submit = false;
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struct rb_node *rb;
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@ -567,15 +569,15 @@ static void i915_guc_dequeue(struct intel_engine_cs *engine)
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port++;
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spin_lock_irq(&engine->timeline->lock);
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rb = engine->execlist_first;
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GEM_BUG_ON(rb_first(&engine->execlist_queue) != rb);
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rb = execlists->first;
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GEM_BUG_ON(rb_first(&execlists->queue) != rb);
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while (rb) {
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struct i915_priolist *p = rb_entry(rb, typeof(*p), node);
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struct drm_i915_gem_request *rq, *rn;
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list_for_each_entry_safe(rq, rn, &p->requests, priotree.link) {
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if (last && rq->ctx != last->ctx) {
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if (port != engine->execlist_port) {
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if (port != execlists->port) {
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__list_del_many(&p->requests,
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&rq->priotree.link);
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goto done;
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@ -596,13 +598,13 @@ static void i915_guc_dequeue(struct intel_engine_cs *engine)
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}
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rb = rb_next(rb);
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rb_erase(&p->node, &engine->execlist_queue);
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rb_erase(&p->node, &execlists->queue);
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INIT_LIST_HEAD(&p->requests);
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if (p->priority != I915_PRIORITY_NORMAL)
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kmem_cache_free(engine->i915->priorities, p);
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}
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done:
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engine->execlist_first = rb;
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execlists->first = rb;
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if (submit) {
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port_assign(port, last);
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i915_guc_submit(engine);
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@ -612,8 +614,8 @@ done:
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static void i915_guc_irq_handler(unsigned long data)
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{
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struct intel_engine_cs *engine = (struct intel_engine_cs *)data;
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struct execlist_port *port = engine->execlist_port;
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struct intel_engine_cs * const engine = (struct intel_engine_cs *)data;
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struct execlist_port *port = engine->execlists.port;
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struct drm_i915_gem_request *rq;
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rq = port_request(&port[0]);
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@ -1144,7 +1146,7 @@ int i915_guc_submission_enable(struct drm_i915_private *dev_priv)
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* and it is guaranteed that it will remove the work item from the
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* queue before our request is completed.
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*/
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BUILD_BUG_ON(ARRAY_SIZE(engine->execlist_port) *
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BUILD_BUG_ON(ARRAY_SIZE(engine->execlists.port) *
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sizeof(struct guc_wq_item) *
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I915_NUM_ENGINES > GUC_WQ_SIZE);
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@ -1175,14 +1177,15 @@ int i915_guc_submission_enable(struct drm_i915_private *dev_priv)
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guc_interrupts_capture(dev_priv);
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for_each_engine(engine, dev_priv, id) {
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struct intel_engine_execlists * const execlists = &engine->execlists;
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/* The tasklet was initialised by execlists, and may be in
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* a state of flux (across a reset) and so we just want to
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* take over the callback without changing any other state
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* in the tasklet.
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*/
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engine->irq_tasklet.func = i915_guc_irq_handler;
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execlists->irq_tasklet.func = i915_guc_irq_handler;
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clear_bit(ENGINE_IRQ_EXECLIST, &engine->irq_posted);
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tasklet_schedule(&engine->irq_tasklet);
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tasklet_schedule(&execlists->irq_tasklet);
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}
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return 0;
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@ -1346,10 +1346,11 @@ static void snb_gt_irq_handler(struct drm_i915_private *dev_priv,
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static void
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gen8_cs_irq_handler(struct intel_engine_cs *engine, u32 iir, int test_shift)
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{
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struct intel_engine_execlists * const execlists = &engine->execlists;
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bool tasklet = false;
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if (iir & (GT_CONTEXT_SWITCH_INTERRUPT << test_shift)) {
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if (port_count(&engine->execlist_port[0])) {
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if (port_count(&execlists->port[0])) {
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__set_bit(ENGINE_IRQ_EXECLIST, &engine->irq_posted);
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tasklet = true;
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}
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@ -1361,7 +1362,7 @@ gen8_cs_irq_handler(struct intel_engine_cs *engine, u32 iir, int test_shift)
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}
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if (tasklet)
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tasklet_hi_schedule(&engine->irq_tasklet);
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tasklet_hi_schedule(&execlists->irq_tasklet);
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}
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static irqreturn_t gen8_gt_irq_ack(struct drm_i915_private *dev_priv,
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@ -393,8 +393,8 @@ static void intel_engine_init_timeline(struct intel_engine_cs *engine)
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*/
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void intel_engine_setup_common(struct intel_engine_cs *engine)
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{
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engine->execlist_queue = RB_ROOT;
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engine->execlist_first = NULL;
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engine->execlists.queue = RB_ROOT;
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engine->execlists.first = NULL;
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intel_engine_init_timeline(engine);
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intel_engine_init_hangcheck(engine);
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@ -1475,11 +1475,11 @@ bool intel_engine_is_idle(struct intel_engine_cs *engine)
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return false;
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/* Both ports drained, no more ELSP submission? */
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if (port_request(&engine->execlist_port[0]))
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if (port_request(&engine->execlists.port[0]))
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return false;
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/* ELSP is empty, but there are ready requests? */
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if (READ_ONCE(engine->execlist_first))
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if (READ_ONCE(engine->execlists.first))
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return false;
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/* Ring stopped? */
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@ -1528,8 +1528,8 @@ void intel_engines_mark_idle(struct drm_i915_private *i915)
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for_each_engine(engine, i915, id) {
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intel_engine_disarm_breadcrumbs(engine);
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i915_gem_batch_pool_fini(&engine->batch_pool);
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tasklet_kill(&engine->irq_tasklet);
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engine->no_priolist = false;
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tasklet_kill(&engine->execlists.irq_tasklet);
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engine->execlists.no_priolist = false;
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}
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}
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@ -291,17 +291,18 @@ lookup_priolist(struct intel_engine_cs *engine,
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struct i915_priotree *pt,
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int prio)
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{
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struct intel_engine_execlists * const execlists = &engine->execlists;
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struct i915_priolist *p;
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struct rb_node **parent, *rb;
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bool first = true;
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if (unlikely(engine->no_priolist))
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if (unlikely(execlists->no_priolist))
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prio = I915_PRIORITY_NORMAL;
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find_priolist:
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/* most positive priority is scheduled first, equal priorities fifo */
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rb = NULL;
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parent = &engine->execlist_queue.rb_node;
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parent = &execlists->queue.rb_node;
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while (*parent) {
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rb = *parent;
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p = rb_entry(rb, typeof(*p), node);
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@ -316,7 +317,7 @@ find_priolist:
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}
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if (prio == I915_PRIORITY_NORMAL) {
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p = &engine->default_priolist;
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p = &execlists->default_priolist;
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} else {
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p = kmem_cache_alloc(engine->i915->priorities, GFP_ATOMIC);
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/* Convert an allocation failure to a priority bump */
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@ -331,7 +332,7 @@ find_priolist:
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* requests, so if userspace lied about their
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* dependencies that reordering may be visible.
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*/
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engine->no_priolist = true;
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execlists->no_priolist = true;
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goto find_priolist;
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}
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}
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@ -339,10 +340,10 @@ find_priolist:
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p->priority = prio;
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INIT_LIST_HEAD(&p->requests);
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rb_link_node(&p->node, rb, parent);
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rb_insert_color(&p->node, &engine->execlist_queue);
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rb_insert_color(&p->node, &execlists->queue);
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if (first)
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engine->execlist_first = &p->node;
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execlists->first = &p->node;
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return ptr_pack_bits(p, first, 1);
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}
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@ -393,12 +394,12 @@ static u64 execlists_update_context(struct drm_i915_gem_request *rq)
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static void execlists_submit_ports(struct intel_engine_cs *engine)
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{
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struct execlist_port *port = engine->execlist_port;
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struct execlist_port *port = engine->execlists.port;
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u32 __iomem *elsp =
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engine->i915->regs + i915_mmio_reg_offset(RING_ELSP(engine));
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unsigned int n;
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for (n = ARRAY_SIZE(engine->execlist_port); n--; ) {
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for (n = ARRAY_SIZE(engine->execlists.port); n--; ) {
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struct drm_i915_gem_request *rq;
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unsigned int count;
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u64 desc;
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@ -453,7 +454,7 @@ static void port_assign(struct execlist_port *port,
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static void execlists_dequeue(struct intel_engine_cs *engine)
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{
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struct drm_i915_gem_request *last;
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struct execlist_port *port = engine->execlist_port;
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struct execlist_port *port = engine->execlists.port;
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struct rb_node *rb;
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bool submit = false;
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@ -491,8 +492,8 @@ static void execlists_dequeue(struct intel_engine_cs *engine)
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*/
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spin_lock_irq(&engine->timeline->lock);
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rb = engine->execlist_first;
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GEM_BUG_ON(rb_first(&engine->execlist_queue) != rb);
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rb = engine->execlists.first;
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GEM_BUG_ON(rb_first(&engine->execlists.queue) != rb);
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while (rb) {
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struct i915_priolist *p = rb_entry(rb, typeof(*p), node);
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struct drm_i915_gem_request *rq, *rn;
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@ -515,7 +516,7 @@ static void execlists_dequeue(struct intel_engine_cs *engine)
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* combine this request with the last, then we
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* are done.
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*/
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if (port != engine->execlist_port) {
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if (port != engine->execlists.port) {
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__list_del_many(&p->requests,
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&rq->priotree.link);
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goto done;
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@ -552,13 +553,13 @@ static void execlists_dequeue(struct intel_engine_cs *engine)
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}
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rb = rb_next(rb);
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rb_erase(&p->node, &engine->execlist_queue);
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rb_erase(&p->node, &engine->execlists.queue);
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INIT_LIST_HEAD(&p->requests);
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if (p->priority != I915_PRIORITY_NORMAL)
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kmem_cache_free(engine->i915->priorities, p);
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}
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done:
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engine->execlist_first = rb;
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engine->execlists.first = rb;
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if (submit)
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port_assign(port, last);
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spin_unlock_irq(&engine->timeline->lock);
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@ -569,7 +570,8 @@ done:
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static void execlists_cancel_requests(struct intel_engine_cs *engine)
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{
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struct execlist_port *port = engine->execlist_port;
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struct intel_engine_execlists * const execlists = &engine->execlists;
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struct execlist_port *port = execlists->port;
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struct drm_i915_gem_request *rq, *rn;
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struct rb_node *rb;
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unsigned long flags;
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@ -578,9 +580,9 @@ static void execlists_cancel_requests(struct intel_engine_cs *engine)
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spin_lock_irqsave(&engine->timeline->lock, flags);
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/* Cancel the requests on the HW and clear the ELSP tracker. */
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for (n = 0; n < ARRAY_SIZE(engine->execlist_port); n++)
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for (n = 0; n < ARRAY_SIZE(execlists->port); n++)
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i915_gem_request_put(port_request(&port[n]));
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memset(engine->execlist_port, 0, sizeof(engine->execlist_port));
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memset(execlists->port, 0, sizeof(execlists->port));
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/* Mark all executing requests as skipped. */
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list_for_each_entry(rq, &engine->timeline->requests, link) {
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@ -590,7 +592,7 @@ static void execlists_cancel_requests(struct intel_engine_cs *engine)
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}
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/* Flush the queued requests to the timeline list (for retiring). */
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rb = engine->execlist_first;
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rb = execlists->first;
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while (rb) {
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struct i915_priolist *p = rb_entry(rb, typeof(*p), node);
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@ -603,7 +605,7 @@ static void execlists_cancel_requests(struct intel_engine_cs *engine)
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}
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rb = rb_next(rb);
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rb_erase(&p->node, &engine->execlist_queue);
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rb_erase(&p->node, &execlists->queue);
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INIT_LIST_HEAD(&p->requests);
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if (p->priority != I915_PRIORITY_NORMAL)
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kmem_cache_free(engine->i915->priorities, p);
|
||||
|
@ -611,8 +613,8 @@ static void execlists_cancel_requests(struct intel_engine_cs *engine)
|
|||
|
||||
/* Remaining _unready_ requests will be nop'ed when submitted */
|
||||
|
||||
engine->execlist_queue = RB_ROOT;
|
||||
engine->execlist_first = NULL;
|
||||
execlists->queue = RB_ROOT;
|
||||
execlists->first = NULL;
|
||||
GEM_BUG_ON(port_isset(&port[0]));
|
||||
|
||||
/*
|
||||
|
@ -628,7 +630,7 @@ static void execlists_cancel_requests(struct intel_engine_cs *engine)
|
|||
|
||||
static bool execlists_elsp_ready(const struct intel_engine_cs *engine)
|
||||
{
|
||||
const struct execlist_port *port = engine->execlist_port;
|
||||
const struct execlist_port *port = engine->execlists.port;
|
||||
|
||||
return port_count(&port[0]) + port_count(&port[1]) < 2;
|
||||
}
|
||||
|
@ -639,8 +641,9 @@ static bool execlists_elsp_ready(const struct intel_engine_cs *engine)
|
|||
*/
|
||||
static void intel_lrc_irq_handler(unsigned long data)
|
||||
{
|
||||
struct intel_engine_cs *engine = (struct intel_engine_cs *)data;
|
||||
struct execlist_port *port = engine->execlist_port;
|
||||
struct intel_engine_cs * const engine = (struct intel_engine_cs *)data;
|
||||
struct intel_engine_execlists * const execlists = &engine->execlists;
|
||||
struct execlist_port *port = execlists->port;
|
||||
struct drm_i915_private *dev_priv = engine->i915;
|
||||
|
||||
/* We can skip acquiring intel_runtime_pm_get() here as it was taken
|
||||
|
@ -652,7 +655,7 @@ static void intel_lrc_irq_handler(unsigned long data)
|
|||
*/
|
||||
GEM_BUG_ON(!dev_priv->gt.awake);
|
||||
|
||||
intel_uncore_forcewake_get(dev_priv, engine->fw_domains);
|
||||
intel_uncore_forcewake_get(dev_priv, execlists->fw_domains);
|
||||
|
||||
/* Prefer doing test_and_clear_bit() as a two stage operation to avoid
|
||||
* imposing the cost of a locked atomic transaction when submitting a
|
||||
|
@ -665,10 +668,10 @@ static void intel_lrc_irq_handler(unsigned long data)
|
|||
unsigned int head, tail;
|
||||
|
||||
/* However GVT emulation depends upon intercepting CSB mmio */
|
||||
if (unlikely(engine->csb_use_mmio)) {
|
||||
if (unlikely(execlists->csb_use_mmio)) {
|
||||
buf = (u32 * __force)
|
||||
(dev_priv->regs + i915_mmio_reg_offset(RING_CONTEXT_STATUS_BUF_LO(engine, 0)));
|
||||
engine->csb_head = -1; /* force mmio read of CSB ptrs */
|
||||
execlists->csb_head = -1; /* force mmio read of CSB ptrs */
|
||||
}
|
||||
|
||||
/* The write will be ordered by the uncached read (itself
|
||||
|
@ -682,19 +685,20 @@ static void intel_lrc_irq_handler(unsigned long data)
|
|||
* is set and we do a new loop.
|
||||
*/
|
||||
__clear_bit(ENGINE_IRQ_EXECLIST, &engine->irq_posted);
|
||||
if (unlikely(engine->csb_head == -1)) { /* following a reset */
|
||||
if (unlikely(execlists->csb_head == -1)) { /* following a reset */
|
||||
head = readl(dev_priv->regs + i915_mmio_reg_offset(RING_CONTEXT_STATUS_PTR(engine)));
|
||||
tail = GEN8_CSB_WRITE_PTR(head);
|
||||
head = GEN8_CSB_READ_PTR(head);
|
||||
engine->csb_head = head;
|
||||
execlists->csb_head = head;
|
||||
} else {
|
||||
const int write_idx =
|
||||
intel_hws_csb_write_index(dev_priv) -
|
||||
I915_HWS_CSB_BUF0_INDEX;
|
||||
|
||||
head = engine->csb_head;
|
||||
head = execlists->csb_head;
|
||||
tail = READ_ONCE(buf[write_idx]);
|
||||
}
|
||||
|
||||
while (head != tail) {
|
||||
struct drm_i915_gem_request *rq;
|
||||
unsigned int status;
|
||||
|
@ -748,8 +752,8 @@ static void intel_lrc_irq_handler(unsigned long data)
|
|||
!(status & GEN8_CTX_STATUS_ACTIVE_IDLE));
|
||||
}
|
||||
|
||||
if (head != engine->csb_head) {
|
||||
engine->csb_head = head;
|
||||
if (head != execlists->csb_head) {
|
||||
execlists->csb_head = head;
|
||||
writel(_MASKED_FIELD(GEN8_CSB_READ_PTR_MASK, head << 8),
|
||||
dev_priv->regs + i915_mmio_reg_offset(RING_CONTEXT_STATUS_PTR(engine)));
|
||||
}
|
||||
|
@ -758,7 +762,7 @@ static void intel_lrc_irq_handler(unsigned long data)
|
|||
if (execlists_elsp_ready(engine))
|
||||
execlists_dequeue(engine);
|
||||
|
||||
intel_uncore_forcewake_put(dev_priv, engine->fw_domains);
|
||||
intel_uncore_forcewake_put(dev_priv, execlists->fw_domains);
|
||||
}
|
||||
|
||||
static void insert_request(struct intel_engine_cs *engine,
|
||||
|
@ -769,7 +773,7 @@ static void insert_request(struct intel_engine_cs *engine,
|
|||
|
||||
list_add_tail(&pt->link, &ptr_mask_bits(p, 1)->requests);
|
||||
if (ptr_unmask_bits(p, 1) && execlists_elsp_ready(engine))
|
||||
tasklet_hi_schedule(&engine->irq_tasklet);
|
||||
tasklet_hi_schedule(&engine->execlists.irq_tasklet);
|
||||
}
|
||||
|
||||
static void execlists_submit_request(struct drm_i915_gem_request *request)
|
||||
|
@ -782,7 +786,7 @@ static void execlists_submit_request(struct drm_i915_gem_request *request)
|
|||
|
||||
insert_request(engine, &request->priotree, request->priotree.priority);
|
||||
|
||||
GEM_BUG_ON(!engine->execlist_first);
|
||||
GEM_BUG_ON(!engine->execlists.first);
|
||||
GEM_BUG_ON(list_empty(&request->priotree.link));
|
||||
|
||||
spin_unlock_irqrestore(&engine->timeline->lock, flags);
|
||||
|
@ -1289,6 +1293,7 @@ static u8 gtiir[] = {
|
|||
static int gen8_init_common_ring(struct intel_engine_cs *engine)
|
||||
{
|
||||
struct drm_i915_private *dev_priv = engine->i915;
|
||||
struct intel_engine_execlists * const execlists = &engine->execlists;
|
||||
int ret;
|
||||
|
||||
ret = intel_mocs_init_engine(engine);
|
||||
|
@ -1321,11 +1326,11 @@ static int gen8_init_common_ring(struct intel_engine_cs *engine)
|
|||
I915_WRITE(GEN8_GT_IIR(gtiir[engine->id]),
|
||||
GT_CONTEXT_SWITCH_INTERRUPT << engine->irq_shift);
|
||||
clear_bit(ENGINE_IRQ_EXECLIST, &engine->irq_posted);
|
||||
engine->csb_head = -1;
|
||||
execlists->csb_head = -1;
|
||||
|
||||
/* After a GPU reset, we may have requests to replay */
|
||||
if (!i915_modparams.enable_guc_submission && engine->execlist_first)
|
||||
tasklet_schedule(&engine->irq_tasklet);
|
||||
if (!i915_modparams.enable_guc_submission && execlists->first)
|
||||
tasklet_schedule(&execlists->irq_tasklet);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
@ -1366,7 +1371,8 @@ static int gen9_init_render_ring(struct intel_engine_cs *engine)
|
|||
static void reset_common_ring(struct intel_engine_cs *engine,
|
||||
struct drm_i915_gem_request *request)
|
||||
{
|
||||
struct execlist_port *port = engine->execlist_port;
|
||||
struct intel_engine_execlists * const execlists = &engine->execlists;
|
||||
struct execlist_port *port = execlists->port;
|
||||
struct drm_i915_gem_request *rq, *rn;
|
||||
struct intel_context *ce;
|
||||
unsigned long flags;
|
||||
|
@ -1383,9 +1389,9 @@ static void reset_common_ring(struct intel_engine_cs *engine,
|
|||
* guessing the missed context-switch events by looking at what
|
||||
* requests were completed.
|
||||
*/
|
||||
for (n = 0; n < ARRAY_SIZE(engine->execlist_port); n++)
|
||||
for (n = 0; n < ARRAY_SIZE(execlists->port); n++)
|
||||
i915_gem_request_put(port_request(&port[n]));
|
||||
memset(engine->execlist_port, 0, sizeof(engine->execlist_port));
|
||||
memset(execlists->port, 0, sizeof(execlists->port));
|
||||
|
||||
/* Push back any incomplete requests for replay after the reset. */
|
||||
list_for_each_entry_safe_reverse(rq, rn,
|
||||
|
@ -1719,8 +1725,8 @@ void intel_logical_ring_cleanup(struct intel_engine_cs *engine)
|
|||
* Tasklet cannot be active at this point due intel_mark_active/idle
|
||||
* so this is just for documentation.
|
||||
*/
|
||||
if (WARN_ON(test_bit(TASKLET_STATE_SCHED, &engine->irq_tasklet.state)))
|
||||
tasklet_kill(&engine->irq_tasklet);
|
||||
if (WARN_ON(test_bit(TASKLET_STATE_SCHED, &engine->execlists.irq_tasklet.state)))
|
||||
tasklet_kill(&engine->execlists.irq_tasklet);
|
||||
|
||||
dev_priv = engine->i915;
|
||||
|
||||
|
@ -1744,7 +1750,7 @@ static void execlists_set_default_submission(struct intel_engine_cs *engine)
|
|||
engine->submit_request = execlists_submit_request;
|
||||
engine->cancel_requests = execlists_cancel_requests;
|
||||
engine->schedule = execlists_schedule;
|
||||
engine->irq_tasklet.func = intel_lrc_irq_handler;
|
||||
engine->execlists.irq_tasklet.func = intel_lrc_irq_handler;
|
||||
}
|
||||
|
||||
static void
|
||||
|
@ -1806,7 +1812,7 @@ logical_ring_setup(struct intel_engine_cs *engine)
|
|||
/* Intentionally left blank. */
|
||||
engine->buffer = NULL;
|
||||
|
||||
engine->csb_use_mmio = irq_handler_force_mmio(dev_priv);
|
||||
engine->execlists.csb_use_mmio = irq_handler_force_mmio(dev_priv);
|
||||
|
||||
fw_domains = intel_uncore_forcewake_for_reg(dev_priv,
|
||||
RING_ELSP(engine),
|
||||
|
@ -1820,9 +1826,9 @@ logical_ring_setup(struct intel_engine_cs *engine)
|
|||
RING_CONTEXT_STATUS_BUF_BASE(engine),
|
||||
FW_REG_READ);
|
||||
|
||||
engine->fw_domains = fw_domains;
|
||||
engine->execlists.fw_domains = fw_domains;
|
||||
|
||||
tasklet_init(&engine->irq_tasklet,
|
||||
tasklet_init(&engine->execlists.irq_tasklet,
|
||||
intel_lrc_irq_handler, (unsigned long)engine);
|
||||
|
||||
logical_ring_default_vfuncs(engine);
|
||||
|
|
|
@ -184,6 +184,84 @@ struct i915_priolist {
|
|||
int priority;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct intel_engine_execlists - execlist submission queue and port state
|
||||
*
|
||||
* The struct intel_engine_execlists represents the combined logical state of
|
||||
* driver and the hardware state for execlist mode of submission.
|
||||
*/
|
||||
struct intel_engine_execlists {
|
||||
/**
|
||||
* @irq_tasklet: softirq tasklet for bottom handler
|
||||
*/
|
||||
struct tasklet_struct irq_tasklet;
|
||||
|
||||
/**
|
||||
* @default_priolist: priority list for I915_PRIORITY_NORMAL
|
||||
*/
|
||||
struct i915_priolist default_priolist;
|
||||
|
||||
/**
|
||||
* @no_priolist: priority lists disabled
|
||||
*/
|
||||
bool no_priolist;
|
||||
|
||||
/**
|
||||
* @port: execlist port states
|
||||
*
|
||||
* For each hardware ELSP (ExecList Submission Port) we keep
|
||||
* track of the last request and the number of times we submitted
|
||||
* that port to hw. We then count the number of times the hw reports
|
||||
* a context completion or preemption. As only one context can
|
||||
* be active on hw, we limit resubmission of context to port[0]. This
|
||||
* is called Lite Restore, of the context.
|
||||
*/
|
||||
struct execlist_port {
|
||||
/**
|
||||
* @request_count: combined request and submission count
|
||||
*/
|
||||
struct drm_i915_gem_request *request_count;
|
||||
#define EXECLIST_COUNT_BITS 2
|
||||
#define port_request(p) ptr_mask_bits((p)->request_count, EXECLIST_COUNT_BITS)
|
||||
#define port_count(p) ptr_unmask_bits((p)->request_count, EXECLIST_COUNT_BITS)
|
||||
#define port_pack(rq, count) ptr_pack_bits(rq, count, EXECLIST_COUNT_BITS)
|
||||
#define port_unpack(p, count) ptr_unpack_bits((p)->request_count, count, EXECLIST_COUNT_BITS)
|
||||
#define port_set(p, packed) ((p)->request_count = (packed))
|
||||
#define port_isset(p) ((p)->request_count)
|
||||
#define port_index(p, e) ((p) - (e)->execlists.port)
|
||||
|
||||
/**
|
||||
* @context_id: context ID for port
|
||||
*/
|
||||
GEM_DEBUG_DECL(u32 context_id);
|
||||
} port[2];
|
||||
|
||||
/**
|
||||
* @queue: queue of requests, in priority lists
|
||||
*/
|
||||
struct rb_root queue;
|
||||
|
||||
/**
|
||||
* @first: leftmost level in priority @queue
|
||||
*/
|
||||
struct rb_node *first;
|
||||
|
||||
/**
|
||||
* @fw_domains: forcewake domains for irq tasklet
|
||||
*/
|
||||
unsigned int fw_domains;
|
||||
|
||||
/**
|
||||
* @csb_head: context status buffer head
|
||||
*/
|
||||
unsigned int csb_head;
|
||||
|
||||
/**
|
||||
* @csb_use_mmio: access csb through mmio, instead of hwsp
|
||||
*/
|
||||
bool csb_use_mmio;
|
||||
};
|
||||
|
||||
#define INTEL_ENGINE_CS_MAX_NAME 8
|
||||
|
||||
struct intel_engine_cs {
|
||||
|
@ -380,27 +458,7 @@ struct intel_engine_cs {
|
|||
u32 *(*signal)(struct drm_i915_gem_request *req, u32 *cs);
|
||||
} semaphore;
|
||||
|
||||
/* Execlists */
|
||||
struct tasklet_struct irq_tasklet;
|
||||
struct i915_priolist default_priolist;
|
||||
bool no_priolist;
|
||||
struct execlist_port {
|
||||
struct drm_i915_gem_request *request_count;
|
||||
#define EXECLIST_COUNT_BITS 2
|
||||
#define port_request(p) ptr_mask_bits((p)->request_count, EXECLIST_COUNT_BITS)
|
||||
#define port_count(p) ptr_unmask_bits((p)->request_count, EXECLIST_COUNT_BITS)
|
||||
#define port_pack(rq, count) ptr_pack_bits(rq, count, EXECLIST_COUNT_BITS)
|
||||
#define port_unpack(p, count) ptr_unpack_bits((p)->request_count, count, EXECLIST_COUNT_BITS)
|
||||
#define port_set(p, packed) ((p)->request_count = (packed))
|
||||
#define port_isset(p) ((p)->request_count)
|
||||
#define port_index(p, e) ((p) - (e)->execlist_port)
|
||||
GEM_DEBUG_DECL(u32 context_id);
|
||||
} execlist_port[2];
|
||||
struct rb_root execlist_queue;
|
||||
struct rb_node *execlist_first;
|
||||
unsigned int fw_domains;
|
||||
unsigned int csb_head;
|
||||
bool csb_use_mmio;
|
||||
struct intel_engine_execlists execlists;
|
||||
|
||||
/* Contexts are pinned whilst they are active on the GPU. The last
|
||||
* context executed remains active whilst the GPU is idle - the
|
||||
|
|
Loading…
Reference in a new issue