Merge branch 'omap-all' into devel
Conflicts: arch/arm/mach-omap2/gpmc.c arch/arm/mach-omap2/irq.c
This commit is contained in:
commit
b6825d2df5
|
@ -118,6 +118,7 @@ endif
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machine-$(CONFIG_ARCH_IXP23XX) := ixp23xx
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machine-$(CONFIG_ARCH_OMAP1) := omap1
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machine-$(CONFIG_ARCH_OMAP2) := omap2
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machine-$(CONFIG_ARCH_OMAP3) := omap2
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plat-$(CONFIG_ARCH_OMAP) := omap
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machine-$(CONFIG_ARCH_S3C2410) := s3c2410 s3c2400 s3c2412 s3c2440 s3c2442 s3c2443
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plat-$(CONFIG_PLAT_S3C24XX) := s3c24xx
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|
|
1321
arch/arm/configs/omap3_beagle_defconfig
Normal file
1321
arch/arm/configs/omap3_beagle_defconfig
Normal file
File diff suppressed because it is too large
Load diff
1044
arch/arm/configs/omap_ldp_defconfig
Normal file
1044
arch/arm/configs/omap_ldp_defconfig
Normal file
File diff suppressed because it is too large
Load diff
1885
arch/arm/configs/overo_defconfig
Normal file
1885
arch/arm/configs/overo_defconfig
Normal file
File diff suppressed because it is too large
Load diff
|
@ -201,7 +201,7 @@ static int calc_dsor_exp(struct clk *clk, unsigned long rate)
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return -EINVAL;
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parent = clk->parent;
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if (unlikely(parent == 0))
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if (unlikely(parent == NULL))
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return -EIO;
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realrate = parent->rate;
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@ -499,7 +499,7 @@ static int omap1_clk_enable_generic(struct clk *clk)
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if (clk->flags & ALWAYS_ENABLED)
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return 0;
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if (unlikely(clk->enable_reg == 0)) {
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if (unlikely(clk->enable_reg == NULL)) {
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printk(KERN_ERR "clock.c: Enable for %s without enable code\n",
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clk->name);
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return -EINVAL;
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@ -535,7 +535,7 @@ static void omap1_clk_disable_generic(struct clk *clk)
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__u16 regval16;
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__u32 regval32;
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if (clk->enable_reg == 0)
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if (clk->enable_reg == NULL)
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return;
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if (clk->flags & ENABLE_REG_32BIT) {
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@ -577,7 +577,7 @@ static long omap1_clk_round_rate(struct clk *clk, unsigned long rate)
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return clk->parent->rate / (1 << dsor_exp);
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}
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if(clk->round_rate != 0)
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if (clk->round_rate != NULL)
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return clk->round_rate(clk, rate);
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return clk->rate;
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@ -625,7 +625,7 @@ static void __init omap1_clk_disable_unused(struct clk *clk)
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/* Clocks in the DSP domain need api_ck. Just assume bootloader
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* has not enabled any DSP clocks */
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if ((u32)clk->enable_reg == DSP_IDLECT2) {
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if (clk->enable_reg == DSP_IDLECT2) {
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printk(KERN_INFO "Skipping reset check for DSP domain "
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"clock \"%s\"\n", clk->name);
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return;
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|
|
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@ -324,7 +324,7 @@ static struct clk dspper_ck = {
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.parent = &ck_dpll1,
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.flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
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RATE_CKCTL | VIRTUAL_IO_ADDRESS,
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.enable_reg = (void __iomem *)DSP_IDLECT2,
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.enable_reg = DSP_IDLECT2,
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.enable_bit = EN_PERCK,
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.rate_offset = CKCTL_PERDIV_OFFSET,
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.recalc = &omap1_ckctl_recalc_dsp_domain,
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@ -338,7 +338,7 @@ static struct clk dspxor_ck = {
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.parent = &ck_ref,
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.flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
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VIRTUAL_IO_ADDRESS,
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.enable_reg = (void __iomem *)DSP_IDLECT2,
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.enable_reg = DSP_IDLECT2,
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.enable_bit = EN_XORPCK,
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.recalc = &followparent_recalc,
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.enable = &omap1_clk_enable_dsp_domain,
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|
@ -350,7 +350,7 @@ static struct clk dsptim_ck = {
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.parent = &ck_ref,
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.flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
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VIRTUAL_IO_ADDRESS,
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.enable_reg = (void __iomem *)DSP_IDLECT2,
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.enable_reg = DSP_IDLECT2,
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.enable_bit = EN_DSPTIMCK,
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.recalc = &followparent_recalc,
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.enable = &omap1_clk_enable_dsp_domain,
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|
|
|
@ -101,7 +101,7 @@ static inline void omap_init_mbox(void) { }
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#if defined(CONFIG_OMAP_STI)
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#define OMAP1_STI_BASE IO_ADDRESS(0xfffea000)
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#define OMAP1_STI_BASE 0xfffea000
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#define OMAP1_STI_CHANNEL_BASE (OMAP1_STI_BASE + 0x400)
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static struct resource sti_resources[] = {
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|
|
|
@ -103,30 +103,6 @@ static inline void omap_mcbsp_clk_init(struct mcbsp_internal_clk *mclk)
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{ }
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#endif
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static int omap1_mcbsp_check(unsigned int id)
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{
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/* REVISIT: Check correctly for number of registered McBSPs */
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if (cpu_is_omap730()) {
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if (id > OMAP_MAX_MCBSP_COUNT - 2) {
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printk(KERN_ERR "OMAP-McBSP: McBSP%d doesn't exist\n",
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id + 1);
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return -ENODEV;
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}
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return 0;
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}
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if (cpu_is_omap15xx() || cpu_is_omap16xx()) {
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if (id > OMAP_MAX_MCBSP_COUNT - 1) {
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printk(KERN_ERR "OMAP-McBSP: McBSP%d doesn't exist\n",
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id + 1);
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return -ENODEV;
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}
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return 0;
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}
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return -ENODEV;
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}
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static void omap1_mcbsp_request(unsigned int id)
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{
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/*
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|
@ -151,7 +127,6 @@ static void omap1_mcbsp_free(unsigned int id)
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}
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static struct omap_mcbsp_ops omap1_mcbsp_ops = {
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.check = omap1_mcbsp_check,
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.request = omap1_mcbsp_request,
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.free = omap1_mcbsp_free,
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};
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@ -160,7 +135,6 @@ static struct omap_mcbsp_ops omap1_mcbsp_ops = {
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static struct omap_mcbsp_platform_data omap730_mcbsp_pdata[] = {
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{
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.phys_base = OMAP730_MCBSP1_BASE,
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.virt_base = io_p2v(OMAP730_MCBSP1_BASE),
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.dma_rx_sync = OMAP_DMA_MCBSP1_RX,
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.dma_tx_sync = OMAP_DMA_MCBSP1_TX,
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.rx_irq = INT_730_McBSP1RX,
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@ -169,7 +143,6 @@ static struct omap_mcbsp_platform_data omap730_mcbsp_pdata[] = {
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},
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{
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.phys_base = OMAP730_MCBSP2_BASE,
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.virt_base = io_p2v(OMAP730_MCBSP2_BASE),
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.dma_rx_sync = OMAP_DMA_MCBSP3_RX,
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.dma_tx_sync = OMAP_DMA_MCBSP3_TX,
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.rx_irq = INT_730_McBSP2RX,
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@ -187,7 +160,6 @@ static struct omap_mcbsp_platform_data omap730_mcbsp_pdata[] = {
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static struct omap_mcbsp_platform_data omap15xx_mcbsp_pdata[] = {
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{
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.phys_base = OMAP1510_MCBSP1_BASE,
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.virt_base = OMAP1510_MCBSP1_BASE,
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.dma_rx_sync = OMAP_DMA_MCBSP1_RX,
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.dma_tx_sync = OMAP_DMA_MCBSP1_TX,
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.rx_irq = INT_McBSP1RX,
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@ -197,7 +169,6 @@ static struct omap_mcbsp_platform_data omap15xx_mcbsp_pdata[] = {
|
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},
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{
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.phys_base = OMAP1510_MCBSP2_BASE,
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.virt_base = io_p2v(OMAP1510_MCBSP2_BASE),
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.dma_rx_sync = OMAP_DMA_MCBSP2_RX,
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.dma_tx_sync = OMAP_DMA_MCBSP2_TX,
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.rx_irq = INT_1510_SPI_RX,
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@ -206,7 +177,6 @@ static struct omap_mcbsp_platform_data omap15xx_mcbsp_pdata[] = {
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},
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{
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.phys_base = OMAP1510_MCBSP3_BASE,
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.virt_base = OMAP1510_MCBSP3_BASE,
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.dma_rx_sync = OMAP_DMA_MCBSP3_RX,
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.dma_tx_sync = OMAP_DMA_MCBSP3_TX,
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.rx_irq = INT_McBSP3RX,
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@ -225,7 +195,6 @@ static struct omap_mcbsp_platform_data omap15xx_mcbsp_pdata[] = {
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static struct omap_mcbsp_platform_data omap16xx_mcbsp_pdata[] = {
|
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{
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.phys_base = OMAP1610_MCBSP1_BASE,
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.virt_base = OMAP1610_MCBSP1_BASE,
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.dma_rx_sync = OMAP_DMA_MCBSP1_RX,
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.dma_tx_sync = OMAP_DMA_MCBSP1_TX,
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.rx_irq = INT_McBSP1RX,
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@ -235,7 +204,6 @@ static struct omap_mcbsp_platform_data omap16xx_mcbsp_pdata[] = {
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},
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{
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.phys_base = OMAP1610_MCBSP2_BASE,
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.virt_base = io_p2v(OMAP1610_MCBSP2_BASE),
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.dma_rx_sync = OMAP_DMA_MCBSP2_RX,
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.dma_tx_sync = OMAP_DMA_MCBSP2_TX,
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.rx_irq = INT_1610_McBSP2_RX,
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@ -244,7 +212,6 @@ static struct omap_mcbsp_platform_data omap16xx_mcbsp_pdata[] = {
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},
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{
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.phys_base = OMAP1610_MCBSP3_BASE,
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.virt_base = OMAP1610_MCBSP3_BASE,
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.dma_rx_sync = OMAP_DMA_MCBSP3_RX,
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.dma_tx_sync = OMAP_DMA_MCBSP3_TX,
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.rx_irq = INT_McBSP3RX,
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@ -270,6 +237,18 @@ int __init omap1_mcbsp_init(void)
|
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}
|
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}
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if (cpu_is_omap730())
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omap_mcbsp_count = OMAP730_MCBSP_PDATA_SZ;
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if (cpu_is_omap15xx())
|
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omap_mcbsp_count = OMAP15XX_MCBSP_PDATA_SZ;
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if (cpu_is_omap16xx())
|
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omap_mcbsp_count = OMAP16XX_MCBSP_PDATA_SZ;
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|
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mcbsp_ptr = kzalloc(omap_mcbsp_count * sizeof(struct omap_mcbsp *),
|
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GFP_KERNEL);
|
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if (!mcbsp_ptr)
|
||||
return -ENOMEM;
|
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|
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if (cpu_is_omap730())
|
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omap_mcbsp_register_board_cfg(omap730_mcbsp_pdata,
|
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OMAP730_MCBSP_PDATA_SZ);
|
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|
|
|
@ -67,8 +67,8 @@ static void __init omap_serial_reset(struct plat_serial8250_port *p)
|
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|
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static struct plat_serial8250_port serial_platform_data[] = {
|
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{
|
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.membase = (char*)IO_ADDRESS(OMAP_UART1_BASE),
|
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.mapbase = (unsigned long)OMAP_UART1_BASE,
|
||||
.membase = IO_ADDRESS(OMAP_UART1_BASE),
|
||||
.mapbase = OMAP_UART1_BASE,
|
||||
.irq = INT_UART1,
|
||||
.flags = UPF_BOOT_AUTOCONF,
|
||||
.iotype = UPIO_MEM,
|
||||
|
@ -76,8 +76,8 @@ static struct plat_serial8250_port serial_platform_data[] = {
|
|||
.uartclk = OMAP16XX_BASE_BAUD * 16,
|
||||
},
|
||||
{
|
||||
.membase = (char*)IO_ADDRESS(OMAP_UART2_BASE),
|
||||
.mapbase = (unsigned long)OMAP_UART2_BASE,
|
||||
.membase = IO_ADDRESS(OMAP_UART2_BASE),
|
||||
.mapbase = OMAP_UART2_BASE,
|
||||
.irq = INT_UART2,
|
||||
.flags = UPF_BOOT_AUTOCONF,
|
||||
.iotype = UPIO_MEM,
|
||||
|
@ -85,8 +85,8 @@ static struct plat_serial8250_port serial_platform_data[] = {
|
|||
.uartclk = OMAP16XX_BASE_BAUD * 16,
|
||||
},
|
||||
{
|
||||
.membase = (char*)IO_ADDRESS(OMAP_UART3_BASE),
|
||||
.mapbase = (unsigned long)OMAP_UART3_BASE,
|
||||
.membase = IO_ADDRESS(OMAP_UART3_BASE),
|
||||
.mapbase = OMAP_UART3_BASE,
|
||||
.irq = INT_UART3,
|
||||
.flags = UPF_BOOT_AUTOCONF,
|
||||
.iotype = UPIO_MEM,
|
||||
|
|
|
@ -15,8 +15,17 @@ config ARCH_OMAP2430
|
|||
bool "OMAP2430 support"
|
||||
depends on ARCH_OMAP24XX
|
||||
|
||||
config ARCH_OMAP34XX
|
||||
bool "OMAP34xx Based System"
|
||||
depends on ARCH_OMAP3
|
||||
|
||||
config ARCH_OMAP3430
|
||||
bool "OMAP3430 support"
|
||||
depends on ARCH_OMAP3 && ARCH_OMAP34XX
|
||||
select ARCH_OMAP_OTG
|
||||
|
||||
comment "OMAP Board Type"
|
||||
depends on ARCH_OMAP2
|
||||
depends on ARCH_OMAP2 || ARCH_OMAP3
|
||||
|
||||
config MACH_OMAP_GENERIC
|
||||
bool "Generic OMAP board"
|
||||
|
@ -35,3 +44,14 @@ config MACH_OMAP_2430SDP
|
|||
bool "OMAP 2430 SDP board"
|
||||
depends on ARCH_OMAP2 && ARCH_OMAP24XX
|
||||
|
||||
config MACH_OMAP3_BEAGLE
|
||||
bool "OMAP3 BEAGLE board"
|
||||
depends on ARCH_OMAP3 && ARCH_OMAP34XX
|
||||
|
||||
config MACH_OMAP_LDP
|
||||
bool "OMAP3 LDP board"
|
||||
depends on ARCH_OMAP3 && ARCH_OMAP34XX
|
||||
|
||||
config MACH_OVERO
|
||||
bool "Gumstix Overo board"
|
||||
depends on ARCH_OMAP3 && ARCH_OMAP34XX
|
||||
|
|
|
@ -4,16 +4,21 @@
|
|||
|
||||
# Common support
|
||||
obj-y := irq.o id.o io.o memory.o control.o prcm.o clock.o mux.o \
|
||||
devices.o serial.o gpmc.o timer-gp.o
|
||||
devices.o serial.o gpmc.o timer-gp.o powerdomain.o \
|
||||
clockdomain.o
|
||||
|
||||
obj-$(CONFIG_OMAP_MCBSP) += mcbsp.o
|
||||
|
||||
# Functions loaded to SRAM
|
||||
obj-$(CONFIG_ARCH_OMAP2420) += sram242x.o
|
||||
obj-$(CONFIG_ARCH_OMAP2430) += sram243x.o
|
||||
obj-$(CONFIG_ARCH_OMAP3) += sram34xx.o
|
||||
|
||||
# Power Management
|
||||
obj-$(CONFIG_PM) += pm.o sleep.o
|
||||
ifeq ($(CONFIG_PM),y)
|
||||
obj-y += pm.o
|
||||
obj-$(CONFIG_ARCH_OMAP24XX) += sleep24xx.o
|
||||
endif
|
||||
|
||||
# Clock framework
|
||||
obj-$(CONFIG_ARCH_OMAP2) += clock24xx.o
|
||||
|
@ -24,4 +29,7 @@ obj-$(CONFIG_MACH_OMAP_GENERIC) += board-generic.o
|
|||
obj-$(CONFIG_MACH_OMAP_H4) += board-h4.o
|
||||
obj-$(CONFIG_MACH_OMAP_2430SDP) += board-2430sdp.o
|
||||
obj-$(CONFIG_MACH_OMAP_APOLLON) += board-apollon.o
|
||||
obj-$(CONFIG_MACH_OMAP3_BEAGLE) += board-omap3beagle.o
|
||||
obj-$(CONFIG_MACH_OMAP_LDP) += board-ldp.o
|
||||
obj-$(CONFIG_MACH_OVERO) += board-overo.o
|
||||
|
||||
|
|
86
arch/arm/mach-omap2/board-ldp.c
Normal file
86
arch/arm/mach-omap2/board-ldp.c
Normal file
|
@ -0,0 +1,86 @@
|
|||
/*
|
||||
* linux/arch/arm/mach-omap2/board-ldp.c
|
||||
*
|
||||
* Copyright (C) 2008 Texas Instruments Inc.
|
||||
* Nishant Kamat <nskamat@ti.com>
|
||||
*
|
||||
* Modified from mach-omap2/board-3430sdp.c
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/input.h>
|
||||
#include <linux/workqueue.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/clk.h>
|
||||
#include <linux/spi/spi.h>
|
||||
#include <linux/spi/ads7846.h>
|
||||
|
||||
#include <mach/hardware.h>
|
||||
#include <asm/mach-types.h>
|
||||
#include <asm/mach/arch.h>
|
||||
#include <asm/mach/map.h>
|
||||
|
||||
#include <mach/board-ldp.h>
|
||||
#include <mach/mcspi.h>
|
||||
#include <mach/gpio.h>
|
||||
#include <mach/board.h>
|
||||
#include <mach/common.h>
|
||||
#include <mach/gpmc.h>
|
||||
|
||||
#include <asm/io.h>
|
||||
#include <asm/delay.h>
|
||||
#include <mach/control.h>
|
||||
|
||||
static void __init omap_ldp_init_irq(void)
|
||||
{
|
||||
omap2_init_common_hw();
|
||||
omap_init_irq();
|
||||
omap_gpio_init();
|
||||
}
|
||||
|
||||
static struct omap_uart_config ldp_uart_config __initdata = {
|
||||
.enabled_uarts = ((1 << 0) | (1 << 1) | (1 << 2)),
|
||||
};
|
||||
|
||||
static struct omap_board_config_kernel ldp_config[] __initdata = {
|
||||
{ OMAP_TAG_UART, &ldp_uart_config },
|
||||
};
|
||||
|
||||
static int __init omap_i2c_init(void)
|
||||
{
|
||||
omap_register_i2c_bus(1, 2600, NULL, 0);
|
||||
omap_register_i2c_bus(2, 400, NULL, 0);
|
||||
omap_register_i2c_bus(3, 400, NULL, 0);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void __init omap_ldp_init(void)
|
||||
{
|
||||
omap_i2c_init();
|
||||
omap_board_config = ldp_config;
|
||||
omap_board_config_size = ARRAY_SIZE(ldp_config);
|
||||
omap_serial_init();
|
||||
}
|
||||
|
||||
static void __init omap_ldp_map_io(void)
|
||||
{
|
||||
omap2_set_globals_343x();
|
||||
omap2_map_common_io();
|
||||
}
|
||||
|
||||
MACHINE_START(OMAP_LDP, "OMAP LDP board")
|
||||
.phys_io = 0x48000000,
|
||||
.io_pg_offst = ((0xd8000000) >> 18) & 0xfffc,
|
||||
.boot_params = 0x80000100,
|
||||
.map_io = omap_ldp_map_io,
|
||||
.init_irq = omap_ldp_init_irq,
|
||||
.init_machine = omap_ldp_init,
|
||||
.timer = &omap_timer,
|
||||
MACHINE_END
|
244
arch/arm/mach-omap2/board-omap3beagle.c
Normal file
244
arch/arm/mach-omap2/board-omap3beagle.c
Normal file
|
@ -0,0 +1,244 @@
|
|||
/*
|
||||
* linux/arch/arm/mach-omap2/board-omap3beagle.c
|
||||
*
|
||||
* Copyright (C) 2008 Texas Instruments
|
||||
*
|
||||
* Modified from mach-omap2/board-3430sdp.c
|
||||
*
|
||||
* Initial code: Syed Mohammed Khasim
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/clk.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/leds.h>
|
||||
#include <linux/gpio.h>
|
||||
#include <linux/input.h>
|
||||
#include <linux/gpio_keys.h>
|
||||
|
||||
#include <linux/mtd/mtd.h>
|
||||
#include <linux/mtd/partitions.h>
|
||||
#include <linux/mtd/nand.h>
|
||||
|
||||
#include <mach/hardware.h>
|
||||
#include <asm/mach-types.h>
|
||||
#include <asm/mach/arch.h>
|
||||
#include <asm/mach/map.h>
|
||||
#include <asm/mach/flash.h>
|
||||
|
||||
#include <mach/board.h>
|
||||
#include <mach/common.h>
|
||||
#include <mach/gpmc.h>
|
||||
#include <mach/nand.h>
|
||||
|
||||
|
||||
#define GPMC_CS0_BASE 0x60
|
||||
#define GPMC_CS_SIZE 0x30
|
||||
|
||||
#define NAND_BLOCK_SIZE SZ_128K
|
||||
|
||||
static struct mtd_partition omap3beagle_nand_partitions[] = {
|
||||
/* All the partition sizes are listed in terms of NAND block size */
|
||||
{
|
||||
.name = "X-Loader",
|
||||
.offset = 0,
|
||||
.size = 4 * NAND_BLOCK_SIZE,
|
||||
.mask_flags = MTD_WRITEABLE, /* force read-only */
|
||||
},
|
||||
{
|
||||
.name = "U-Boot",
|
||||
.offset = MTDPART_OFS_APPEND, /* Offset = 0x80000 */
|
||||
.size = 15 * NAND_BLOCK_SIZE,
|
||||
.mask_flags = MTD_WRITEABLE, /* force read-only */
|
||||
},
|
||||
{
|
||||
.name = "U-Boot Env",
|
||||
.offset = MTDPART_OFS_APPEND, /* Offset = 0x260000 */
|
||||
.size = 1 * NAND_BLOCK_SIZE,
|
||||
},
|
||||
{
|
||||
.name = "Kernel",
|
||||
.offset = MTDPART_OFS_APPEND, /* Offset = 0x280000 */
|
||||
.size = 32 * NAND_BLOCK_SIZE,
|
||||
},
|
||||
{
|
||||
.name = "File System",
|
||||
.offset = MTDPART_OFS_APPEND, /* Offset = 0x680000 */
|
||||
.size = MTDPART_SIZ_FULL,
|
||||
},
|
||||
};
|
||||
|
||||
static struct omap_nand_platform_data omap3beagle_nand_data = {
|
||||
.options = NAND_BUSWIDTH_16,
|
||||
.parts = omap3beagle_nand_partitions,
|
||||
.nr_parts = ARRAY_SIZE(omap3beagle_nand_partitions),
|
||||
.dma_channel = -1, /* disable DMA in OMAP NAND driver */
|
||||
.nand_setup = NULL,
|
||||
.dev_ready = NULL,
|
||||
};
|
||||
|
||||
static struct resource omap3beagle_nand_resource = {
|
||||
.flags = IORESOURCE_MEM,
|
||||
};
|
||||
|
||||
static struct platform_device omap3beagle_nand_device = {
|
||||
.name = "omap2-nand",
|
||||
.id = -1,
|
||||
.dev = {
|
||||
.platform_data = &omap3beagle_nand_data,
|
||||
},
|
||||
.num_resources = 1,
|
||||
.resource = &omap3beagle_nand_resource,
|
||||
};
|
||||
|
||||
static struct omap_uart_config omap3_beagle_uart_config __initdata = {
|
||||
.enabled_uarts = ((1 << 0) | (1 << 1) | (1 << 2)),
|
||||
};
|
||||
|
||||
static void __init omap3_beagle_init_irq(void)
|
||||
{
|
||||
omap2_init_common_hw();
|
||||
omap_init_irq();
|
||||
omap_gpio_init();
|
||||
}
|
||||
|
||||
static struct platform_device omap3_beagle_lcd_device = {
|
||||
.name = "omap3beagle_lcd",
|
||||
.id = -1,
|
||||
};
|
||||
|
||||
static struct omap_lcd_config omap3_beagle_lcd_config __initdata = {
|
||||
.ctrl_name = "internal",
|
||||
};
|
||||
|
||||
static struct gpio_led gpio_leds[] = {
|
||||
{
|
||||
.name = "beagleboard::usr0",
|
||||
.default_trigger = "heartbeat",
|
||||
.gpio = 150,
|
||||
},
|
||||
{
|
||||
.name = "beagleboard::usr1",
|
||||
.default_trigger = "mmc0",
|
||||
.gpio = 149,
|
||||
},
|
||||
};
|
||||
|
||||
static struct gpio_led_platform_data gpio_led_info = {
|
||||
.leds = gpio_leds,
|
||||
.num_leds = ARRAY_SIZE(gpio_leds),
|
||||
};
|
||||
|
||||
static struct platform_device leds_gpio = {
|
||||
.name = "leds-gpio",
|
||||
.id = -1,
|
||||
.dev = {
|
||||
.platform_data = &gpio_led_info,
|
||||
},
|
||||
};
|
||||
|
||||
static struct gpio_keys_button gpio_buttons[] = {
|
||||
{
|
||||
.code = BTN_EXTRA,
|
||||
.gpio = 7,
|
||||
.desc = "user",
|
||||
.wakeup = 1,
|
||||
},
|
||||
};
|
||||
|
||||
static struct gpio_keys_platform_data gpio_key_info = {
|
||||
.buttons = gpio_buttons,
|
||||
.nbuttons = ARRAY_SIZE(gpio_buttons),
|
||||
};
|
||||
|
||||
static struct platform_device keys_gpio = {
|
||||
.name = "gpio-keys",
|
||||
.id = -1,
|
||||
.dev = {
|
||||
.platform_data = &gpio_key_info,
|
||||
},
|
||||
};
|
||||
|
||||
static struct omap_board_config_kernel omap3_beagle_config[] __initdata = {
|
||||
{ OMAP_TAG_UART, &omap3_beagle_uart_config },
|
||||
{ OMAP_TAG_LCD, &omap3_beagle_lcd_config },
|
||||
};
|
||||
|
||||
static struct platform_device *omap3_beagle_devices[] __initdata = {
|
||||
&omap3_beagle_lcd_device,
|
||||
&leds_gpio,
|
||||
&keys_gpio,
|
||||
};
|
||||
|
||||
static void __init omap3beagle_flash_init(void)
|
||||
{
|
||||
u8 cs = 0;
|
||||
u8 nandcs = GPMC_CS_NUM + 1;
|
||||
|
||||
u32 gpmc_base_add = OMAP34XX_GPMC_VIRT;
|
||||
|
||||
/* find out the chip-select on which NAND exists */
|
||||
while (cs < GPMC_CS_NUM) {
|
||||
u32 ret = 0;
|
||||
ret = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
|
||||
|
||||
if ((ret & 0xC00) == 0x800) {
|
||||
printk(KERN_INFO "Found NAND on CS%d\n", cs);
|
||||
if (nandcs > GPMC_CS_NUM)
|
||||
nandcs = cs;
|
||||
}
|
||||
cs++;
|
||||
}
|
||||
|
||||
if (nandcs > GPMC_CS_NUM) {
|
||||
printk(KERN_INFO "NAND: Unable to find configuration "
|
||||
"in GPMC\n ");
|
||||
return;
|
||||
}
|
||||
|
||||
if (nandcs < GPMC_CS_NUM) {
|
||||
omap3beagle_nand_data.cs = nandcs;
|
||||
omap3beagle_nand_data.gpmc_cs_baseaddr = (void *)
|
||||
(gpmc_base_add + GPMC_CS0_BASE + nandcs * GPMC_CS_SIZE);
|
||||
omap3beagle_nand_data.gpmc_baseaddr = (void *) (gpmc_base_add);
|
||||
|
||||
printk(KERN_INFO "Registering NAND on CS%d\n", nandcs);
|
||||
if (platform_device_register(&omap3beagle_nand_device) < 0)
|
||||
printk(KERN_ERR "Unable to register NAND device\n");
|
||||
}
|
||||
}
|
||||
|
||||
static void __init omap3_beagle_init(void)
|
||||
{
|
||||
platform_add_devices(omap3_beagle_devices,
|
||||
ARRAY_SIZE(omap3_beagle_devices));
|
||||
omap_board_config = omap3_beagle_config;
|
||||
omap_board_config_size = ARRAY_SIZE(omap3_beagle_config);
|
||||
omap_serial_init();
|
||||
omap3beagle_flash_init();
|
||||
}
|
||||
|
||||
static void __init omap3_beagle_map_io(void)
|
||||
{
|
||||
omap2_set_globals_343x();
|
||||
omap2_map_common_io();
|
||||
}
|
||||
|
||||
MACHINE_START(OMAP3_BEAGLE, "OMAP3 Beagle Board")
|
||||
/* Maintainer: Syed Mohammed Khasim - http://beagleboard.org */
|
||||
.phys_io = 0x48000000,
|
||||
.io_pg_offst = ((0xd8000000) >> 18) & 0xfffc,
|
||||
.boot_params = 0x80000100,
|
||||
.map_io = omap3_beagle_map_io,
|
||||
.init_irq = omap3_beagle_init_irq,
|
||||
.init_machine = omap3_beagle_init,
|
||||
.timer = &omap_timer,
|
||||
MACHINE_END
|
242
arch/arm/mach-omap2/board-overo.c
Normal file
242
arch/arm/mach-omap2/board-overo.c
Normal file
|
@ -0,0 +1,242 @@
|
|||
/*
|
||||
* board-overo.c (Gumstix Overo)
|
||||
*
|
||||
* Initial code: Steve Sakoman <steve@sakoman.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* version 2 as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but
|
||||
* WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
* General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
|
||||
* 02110-1301 USA
|
||||
*
|
||||
*/
|
||||
|
||||
#include <linux/clk.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/platform_device.h>
|
||||
|
||||
#include <linux/mtd/mtd.h>
|
||||
#include <linux/mtd/nand.h>
|
||||
#include <linux/mtd/partitions.h>
|
||||
|
||||
#include <asm/mach-types.h>
|
||||
#include <asm/mach/arch.h>
|
||||
#include <asm/mach/flash.h>
|
||||
#include <asm/mach/map.h>
|
||||
|
||||
#include <mach/board-overo.h>
|
||||
#include <mach/board.h>
|
||||
#include <mach/common.h>
|
||||
#include <mach/gpio.h>
|
||||
#include <mach/gpmc.h>
|
||||
#include <mach/hardware.h>
|
||||
#include <mach/nand.h>
|
||||
|
||||
#define NAND_BLOCK_SIZE SZ_128K
|
||||
#define GPMC_CS0_BASE 0x60
|
||||
#define GPMC_CS_SIZE 0x30
|
||||
|
||||
static struct mtd_partition overo_nand_partitions[] = {
|
||||
{
|
||||
.name = "xloader",
|
||||
.offset = 0, /* Offset = 0x00000 */
|
||||
.size = 4 * NAND_BLOCK_SIZE,
|
||||
.mask_flags = MTD_WRITEABLE
|
||||
},
|
||||
{
|
||||
.name = "uboot",
|
||||
.offset = MTDPART_OFS_APPEND, /* Offset = 0x80000 */
|
||||
.size = 14 * NAND_BLOCK_SIZE,
|
||||
},
|
||||
{
|
||||
.name = "uboot environment",
|
||||
.offset = MTDPART_OFS_APPEND, /* Offset = 0x240000 */
|
||||
.size = 2 * NAND_BLOCK_SIZE,
|
||||
},
|
||||
{
|
||||
.name = "linux",
|
||||
.offset = MTDPART_OFS_APPEND, /* Offset = 0x280000 */
|
||||
.size = 32 * NAND_BLOCK_SIZE,
|
||||
},
|
||||
{
|
||||
.name = "rootfs",
|
||||
.offset = MTDPART_OFS_APPEND, /* Offset = 0x680000 */
|
||||
.size = MTDPART_SIZ_FULL,
|
||||
},
|
||||
};
|
||||
|
||||
static struct omap_nand_platform_data overo_nand_data = {
|
||||
.parts = overo_nand_partitions,
|
||||
.nr_parts = ARRAY_SIZE(overo_nand_partitions),
|
||||
.dma_channel = -1, /* disable DMA in OMAP NAND driver */
|
||||
};
|
||||
|
||||
static struct resource overo_nand_resource = {
|
||||
.flags = IORESOURCE_MEM,
|
||||
};
|
||||
|
||||
static struct platform_device overo_nand_device = {
|
||||
.name = "omap2-nand",
|
||||
.id = -1,
|
||||
.dev = {
|
||||
.platform_data = &overo_nand_data,
|
||||
},
|
||||
.num_resources = 1,
|
||||
.resource = &overo_nand_resource,
|
||||
};
|
||||
|
||||
|
||||
static void __init overo_flash_init(void)
|
||||
{
|
||||
u8 cs = 0;
|
||||
u8 nandcs = GPMC_CS_NUM + 1;
|
||||
|
||||
u32 gpmc_base_add = OMAP34XX_GPMC_VIRT;
|
||||
|
||||
/* find out the chip-select on which NAND exists */
|
||||
while (cs < GPMC_CS_NUM) {
|
||||
u32 ret = 0;
|
||||
ret = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
|
||||
|
||||
if ((ret & 0xC00) == 0x800) {
|
||||
printk(KERN_INFO "Found NAND on CS%d\n", cs);
|
||||
if (nandcs > GPMC_CS_NUM)
|
||||
nandcs = cs;
|
||||
}
|
||||
cs++;
|
||||
}
|
||||
|
||||
if (nandcs > GPMC_CS_NUM) {
|
||||
printk(KERN_INFO "NAND: Unable to find configuration "
|
||||
"in GPMC\n ");
|
||||
return;
|
||||
}
|
||||
|
||||
if (nandcs < GPMC_CS_NUM) {
|
||||
overo_nand_data.cs = nandcs;
|
||||
overo_nand_data.gpmc_cs_baseaddr = (void *)
|
||||
(gpmc_base_add + GPMC_CS0_BASE + nandcs * GPMC_CS_SIZE);
|
||||
overo_nand_data.gpmc_baseaddr = (void *) (gpmc_base_add);
|
||||
|
||||
printk(KERN_INFO "Registering NAND on CS%d\n", nandcs);
|
||||
if (platform_device_register(&overo_nand_device) < 0)
|
||||
printk(KERN_ERR "Unable to register NAND device\n");
|
||||
}
|
||||
}
|
||||
static struct omap_uart_config overo_uart_config __initdata = {
|
||||
.enabled_uarts = ((1 << 0) | (1 << 1) | (1 << 2)),
|
||||
};
|
||||
|
||||
static int __init overo_i2c_init(void)
|
||||
{
|
||||
/* i2c2 pins are used for gpio */
|
||||
omap_register_i2c_bus(3, 400, NULL, 0);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void __init overo_init_irq(void)
|
||||
{
|
||||
omap2_init_common_hw();
|
||||
omap_init_irq();
|
||||
omap_gpio_init();
|
||||
}
|
||||
|
||||
static struct platform_device overo_lcd_device = {
|
||||
.name = "overo_lcd",
|
||||
.id = -1,
|
||||
};
|
||||
|
||||
static struct omap_lcd_config overo_lcd_config __initdata = {
|
||||
.ctrl_name = "internal",
|
||||
};
|
||||
|
||||
static struct omap_board_config_kernel overo_config[] __initdata = {
|
||||
{ OMAP_TAG_UART, &overo_uart_config },
|
||||
{ OMAP_TAG_LCD, &overo_lcd_config },
|
||||
};
|
||||
|
||||
static struct platform_device *overo_devices[] __initdata = {
|
||||
&overo_lcd_device,
|
||||
};
|
||||
|
||||
static void __init overo_init(void)
|
||||
{
|
||||
overo_i2c_init();
|
||||
platform_add_devices(overo_devices, ARRAY_SIZE(overo_devices));
|
||||
omap_board_config = overo_config;
|
||||
omap_board_config_size = ARRAY_SIZE(overo_config);
|
||||
omap_serial_init();
|
||||
overo_flash_init();
|
||||
|
||||
if ((gpio_request(OVERO_GPIO_W2W_NRESET,
|
||||
"OVERO_GPIO_W2W_NRESET") == 0) &&
|
||||
(gpio_direction_output(OVERO_GPIO_W2W_NRESET, 1) == 0)) {
|
||||
gpio_export(OVERO_GPIO_W2W_NRESET, 0);
|
||||
gpio_set_value(OVERO_GPIO_W2W_NRESET, 0);
|
||||
udelay(10);
|
||||
gpio_set_value(OVERO_GPIO_W2W_NRESET, 1);
|
||||
} else {
|
||||
printk(KERN_ERR "could not obtain gpio for "
|
||||
"OVERO_GPIO_W2W_NRESET\n");
|
||||
}
|
||||
|
||||
if ((gpio_request(OVERO_GPIO_BT_XGATE, "OVERO_GPIO_BT_XGATE") == 0) &&
|
||||
(gpio_direction_output(OVERO_GPIO_BT_XGATE, 0) == 0))
|
||||
gpio_export(OVERO_GPIO_BT_XGATE, 0);
|
||||
else
|
||||
printk(KERN_ERR "could not obtain gpio for OVERO_GPIO_BT_XGATE\n");
|
||||
|
||||
if ((gpio_request(OVERO_GPIO_BT_NRESET, "OVERO_GPIO_BT_NRESET") == 0) &&
|
||||
(gpio_direction_output(OVERO_GPIO_BT_NRESET, 1) == 0)) {
|
||||
gpio_export(OVERO_GPIO_BT_NRESET, 0);
|
||||
gpio_set_value(OVERO_GPIO_BT_NRESET, 0);
|
||||
mdelay(6);
|
||||
gpio_set_value(OVERO_GPIO_BT_NRESET, 1);
|
||||
} else {
|
||||
printk(KERN_ERR "could not obtain gpio for "
|
||||
"OVERO_GPIO_BT_NRESET\n");
|
||||
}
|
||||
|
||||
if ((gpio_request(OVERO_GPIO_USBH_CPEN, "OVERO_GPIO_USBH_CPEN") == 0) &&
|
||||
(gpio_direction_output(OVERO_GPIO_USBH_CPEN, 1) == 0))
|
||||
gpio_export(OVERO_GPIO_USBH_CPEN, 0);
|
||||
else
|
||||
printk(KERN_ERR "could not obtain gpio for "
|
||||
"OVERO_GPIO_USBH_CPEN\n");
|
||||
|
||||
if ((gpio_request(OVERO_GPIO_USBH_NRESET,
|
||||
"OVERO_GPIO_USBH_NRESET") == 0) &&
|
||||
(gpio_direction_output(OVERO_GPIO_USBH_NRESET, 1) == 0))
|
||||
gpio_export(OVERO_GPIO_USBH_NRESET, 0);
|
||||
else
|
||||
printk(KERN_ERR "could not obtain gpio for "
|
||||
"OVERO_GPIO_USBH_NRESET\n");
|
||||
}
|
||||
|
||||
static void __init overo_map_io(void)
|
||||
{
|
||||
omap2_set_globals_343x();
|
||||
omap2_map_common_io();
|
||||
}
|
||||
|
||||
MACHINE_START(OVERO, "Gumstix Overo")
|
||||
.phys_io = 0x48000000,
|
||||
.io_pg_offst = ((0xd8000000) >> 18) & 0xfffc,
|
||||
.boot_params = 0x80000100,
|
||||
.map_io = overo_map_io,
|
||||
.init_irq = overo_init_irq,
|
||||
.init_machine = overo_init,
|
||||
.timer = &omap_timer,
|
||||
MACHINE_END
|
|
@ -25,6 +25,7 @@
|
|||
#include <linux/bitops.h>
|
||||
|
||||
#include <mach/clock.h>
|
||||
#include <mach/clockdomain.h>
|
||||
#include <mach/sram.h>
|
||||
#include <mach/cpu.h>
|
||||
#include <asm/div64.h>
|
||||
|
@ -61,9 +62,35 @@
|
|||
u8 cpu_mask;
|
||||
|
||||
/*-------------------------------------------------------------------------
|
||||
* Omap2 specific clock functions
|
||||
* OMAP2/3 specific clock functions
|
||||
*-------------------------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* omap2_init_clk_clkdm - look up a clockdomain name, store pointer in clk
|
||||
* @clk: OMAP clock struct ptr to use
|
||||
*
|
||||
* Convert a clockdomain name stored in a struct clk 'clk' into a
|
||||
* clockdomain pointer, and save it into the struct clk. Intended to be
|
||||
* called during clk_register(). No return value.
|
||||
*/
|
||||
void omap2_init_clk_clkdm(struct clk *clk)
|
||||
{
|
||||
struct clockdomain *clkdm;
|
||||
|
||||
if (!clk->clkdm_name)
|
||||
return;
|
||||
|
||||
clkdm = clkdm_lookup(clk->clkdm_name);
|
||||
if (clkdm) {
|
||||
pr_debug("clock: associated clk %s to clkdm %s\n",
|
||||
clk->name, clk->clkdm_name);
|
||||
clk->clkdm = clkdm;
|
||||
} else {
|
||||
pr_debug("clock: could not associate clk %s to "
|
||||
"clkdm %s\n", clk->name, clk->clkdm_name);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* omap2_init_clksel_parent - set a clksel clk's parent field from the hardware
|
||||
* @clk: OMAP clock struct ptr to use
|
||||
|
@ -250,7 +277,7 @@ int _omap2_clk_enable(struct clk *clk)
|
|||
if (clk->enable)
|
||||
return clk->enable(clk);
|
||||
|
||||
if (unlikely(clk->enable_reg == 0)) {
|
||||
if (unlikely(clk->enable_reg == NULL)) {
|
||||
printk(KERN_ERR "clock.c: Enable for %s without enable code\n",
|
||||
clk->name);
|
||||
return 0; /* REVISIT: -EINVAL */
|
||||
|
@ -282,7 +309,7 @@ void _omap2_clk_disable(struct clk *clk)
|
|||
return;
|
||||
}
|
||||
|
||||
if (clk->enable_reg == 0) {
|
||||
if (clk->enable_reg == NULL) {
|
||||
/*
|
||||
* 'Independent' here refers to a clock which is not
|
||||
* controlled by its parent.
|
||||
|
@ -307,6 +334,9 @@ void omap2_clk_disable(struct clk *clk)
|
|||
_omap2_clk_disable(clk);
|
||||
if (likely((u32)clk->parent))
|
||||
omap2_clk_disable(clk->parent);
|
||||
if (clk->clkdm)
|
||||
omap2_clkdm_clk_disable(clk->clkdm, clk);
|
||||
|
||||
}
|
||||
}
|
||||
|
||||
|
@ -323,11 +353,19 @@ int omap2_clk_enable(struct clk *clk)
|
|||
return ret;
|
||||
}
|
||||
|
||||
if (clk->clkdm)
|
||||
omap2_clkdm_clk_enable(clk->clkdm, clk);
|
||||
|
||||
ret = _omap2_clk_enable(clk);
|
||||
|
||||
if (unlikely(ret != 0) && clk->parent) {
|
||||
omap2_clk_disable(clk->parent);
|
||||
clk->usecount--;
|
||||
if (unlikely(ret != 0)) {
|
||||
if (clk->clkdm)
|
||||
omap2_clkdm_clk_disable(clk->clkdm, clk);
|
||||
|
||||
if (clk->parent) {
|
||||
omap2_clk_disable(clk->parent);
|
||||
clk->usecount--;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
@ -476,7 +514,7 @@ long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate)
|
|||
/* Given a clock and a rate apply a clock specific rounding function */
|
||||
long omap2_clk_round_rate(struct clk *clk, unsigned long rate)
|
||||
{
|
||||
if (clk->round_rate != 0)
|
||||
if (clk->round_rate != NULL)
|
||||
return clk->round_rate(clk, rate);
|
||||
|
||||
if (clk->flags & RATE_FIXED)
|
||||
|
@ -565,7 +603,7 @@ u32 omap2_divisor_to_clksel(struct clk *clk, u32 div)
|
|||
*/
|
||||
void __iomem *omap2_get_clksel(struct clk *clk, u32 *field_mask)
|
||||
{
|
||||
if (unlikely((clk->clksel_reg == 0) || (clk->clksel_mask == 0)))
|
||||
if (unlikely((clk->clksel_reg == NULL) || (clk->clksel_mask == NULL)))
|
||||
return NULL;
|
||||
|
||||
*field_mask = clk->clksel_mask;
|
||||
|
@ -585,7 +623,7 @@ u32 omap2_clksel_get_divisor(struct clk *clk)
|
|||
void __iomem *div_addr;
|
||||
|
||||
div_addr = omap2_get_clksel(clk, &field_mask);
|
||||
if (div_addr == 0)
|
||||
if (div_addr == NULL)
|
||||
return 0;
|
||||
|
||||
field_val = __raw_readl(div_addr) & field_mask;
|
||||
|
@ -604,7 +642,7 @@ int omap2_clksel_set_rate(struct clk *clk, unsigned long rate)
|
|||
return -EINVAL;
|
||||
|
||||
div_addr = omap2_get_clksel(clk, &field_mask);
|
||||
if (div_addr == 0)
|
||||
if (div_addr == NULL)
|
||||
return -EINVAL;
|
||||
|
||||
field_val = omap2_divisor_to_clksel(clk, new_div);
|
||||
|
@ -642,7 +680,7 @@ int omap2_clk_set_rate(struct clk *clk, unsigned long rate)
|
|||
return -EINVAL;
|
||||
|
||||
/* dpll_ck, core_ck, virt_prcm_set; plus all clksel clocks */
|
||||
if (clk->set_rate != 0)
|
||||
if (clk->set_rate != NULL)
|
||||
ret = clk->set_rate(clk, rate);
|
||||
|
||||
if (unlikely(ret == 0 && (clk->flags & RATE_PROPAGATES)))
|
||||
|
@ -663,7 +701,7 @@ static u32 omap2_clksel_get_src_field(void __iomem **src_addr,
|
|||
const struct clksel_rate *clkr;
|
||||
|
||||
*parent_div = 0;
|
||||
*src_addr = 0;
|
||||
*src_addr = NULL;
|
||||
|
||||
clks = omap2_get_clksel_by_parent(clk, src_clk);
|
||||
if (clks == NULL)
|
||||
|
@ -704,7 +742,7 @@ int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent)
|
|||
|
||||
field_val = omap2_clksel_get_src_field(&src_addr, new_parent,
|
||||
&field_mask, clk, &parent_div);
|
||||
if (src_addr == 0)
|
||||
if (src_addr == NULL)
|
||||
return -EINVAL;
|
||||
|
||||
if (clk->usecount > 0)
|
||||
|
|
|
@ -21,6 +21,7 @@
|
|||
/* The maximum error between a target DPLL rate and the rounded rate in Hz */
|
||||
#define DEFAULT_DPLL_RATE_TOLERANCE 50000
|
||||
|
||||
int omap2_clk_init(void);
|
||||
int omap2_clk_enable(struct clk *clk);
|
||||
void omap2_clk_disable(struct clk *clk);
|
||||
long omap2_clk_round_rate(struct clk *clk, unsigned long rate);
|
||||
|
@ -36,6 +37,7 @@ void omap2_clk_disable_unused(struct clk *clk);
|
|||
#endif
|
||||
|
||||
void omap2_clksel_recalc(struct clk *clk);
|
||||
void omap2_init_clk_clkdm(struct clk *clk);
|
||||
void omap2_init_clksel_parent(struct clk *clk);
|
||||
u32 omap2_clksel_get_divisor(struct clk *clk);
|
||||
u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate,
|
||||
|
|
File diff suppressed because it is too large
Load diff
|
@ -62,11 +62,14 @@ static void omap3_dpll_recalc(struct clk *clk)
|
|||
static void _omap3_dpll_write_clken(struct clk *clk, u8 clken_bits)
|
||||
{
|
||||
const struct dpll_data *dd;
|
||||
u32 v;
|
||||
|
||||
dd = clk->dpll_data;
|
||||
|
||||
cm_rmw_reg_bits(dd->enable_mask, clken_bits << __ffs(dd->enable_mask),
|
||||
dd->control_reg);
|
||||
v = __raw_readl(dd->control_reg);
|
||||
v &= ~dd->enable_mask;
|
||||
v |= clken_bits << __ffs(dd->enable_mask);
|
||||
__raw_writel(v, dd->control_reg);
|
||||
}
|
||||
|
||||
/* _omap3_wait_dpll_status: wait for a DPLL to enter a specific state */
|
||||
|
@ -82,7 +85,7 @@ static int _omap3_wait_dpll_status(struct clk *clk, u8 state)
|
|||
state <<= dd->idlest_bit;
|
||||
idlest_mask = 1 << dd->idlest_bit;
|
||||
|
||||
while (((cm_read_reg(dd->idlest_reg) & idlest_mask) != state) &&
|
||||
while (((__raw_readl(dd->idlest_reg) & idlest_mask) != state) &&
|
||||
i < MAX_DPLL_WAIT_TRIES) {
|
||||
i++;
|
||||
udelay(1);
|
||||
|
@ -285,7 +288,7 @@ static u32 omap3_dpll_autoidle_read(struct clk *clk)
|
|||
|
||||
dd = clk->dpll_data;
|
||||
|
||||
v = cm_read_reg(dd->autoidle_reg);
|
||||
v = __raw_readl(dd->autoidle_reg);
|
||||
v &= dd->autoidle_mask;
|
||||
v >>= __ffs(dd->autoidle_mask);
|
||||
|
||||
|
@ -304,6 +307,7 @@ static u32 omap3_dpll_autoidle_read(struct clk *clk)
|
|||
static void omap3_dpll_allow_idle(struct clk *clk)
|
||||
{
|
||||
const struct dpll_data *dd;
|
||||
u32 v;
|
||||
|
||||
if (!clk || !clk->dpll_data)
|
||||
return;
|
||||
|
@ -315,9 +319,10 @@ static void omap3_dpll_allow_idle(struct clk *clk)
|
|||
* by writing 0x5 instead of 0x1. Add some mechanism to
|
||||
* optionally enter this mode.
|
||||
*/
|
||||
cm_rmw_reg_bits(dd->autoidle_mask,
|
||||
DPLL_AUTOIDLE_LOW_POWER_STOP << __ffs(dd->autoidle_mask),
|
||||
dd->autoidle_reg);
|
||||
v = __raw_readl(dd->autoidle_reg);
|
||||
v &= ~dd->autoidle_mask;
|
||||
v |= DPLL_AUTOIDLE_LOW_POWER_STOP << __ffs(dd->autoidle_mask);
|
||||
__raw_writel(v, dd->autoidle_reg);
|
||||
}
|
||||
|
||||
/**
|
||||
|
@ -329,15 +334,17 @@ static void omap3_dpll_allow_idle(struct clk *clk)
|
|||
static void omap3_dpll_deny_idle(struct clk *clk)
|
||||
{
|
||||
const struct dpll_data *dd;
|
||||
u32 v;
|
||||
|
||||
if (!clk || !clk->dpll_data)
|
||||
return;
|
||||
|
||||
dd = clk->dpll_data;
|
||||
|
||||
cm_rmw_reg_bits(dd->autoidle_mask,
|
||||
DPLL_AUTOIDLE_DISABLE << __ffs(dd->autoidle_mask),
|
||||
dd->autoidle_reg);
|
||||
v = __raw_readl(dd->autoidle_reg);
|
||||
v &= ~dd->autoidle_mask;
|
||||
v |= DPLL_AUTOIDLE_DISABLE << __ffs(dd->autoidle_mask);
|
||||
__raw_writel(v, dd->autoidle_reg);
|
||||
}
|
||||
|
||||
/* Clock control for DPLL outputs */
|
||||
|
@ -482,8 +489,10 @@ int __init omap2_clk_init(void)
|
|||
for (clkp = onchip_34xx_clks;
|
||||
clkp < onchip_34xx_clks + ARRAY_SIZE(onchip_34xx_clks);
|
||||
clkp++) {
|
||||
if ((*clkp)->flags & cpu_clkflg)
|
||||
if ((*clkp)->flags & cpu_clkflg) {
|
||||
clk_register(*clkp);
|
||||
omap2_init_clk_clkdm(*clkp);
|
||||
}
|
||||
}
|
||||
|
||||
/* REVISIT: Not yet ready for OMAP3 */
|
||||
|
|
File diff suppressed because it is too large
Load diff
623
arch/arm/mach-omap2/clockdomain.c
Normal file
623
arch/arm/mach-omap2/clockdomain.c
Normal file
|
@ -0,0 +1,623 @@
|
|||
/*
|
||||
* OMAP2/3 clockdomain framework functions
|
||||
*
|
||||
* Copyright (C) 2008 Texas Instruments, Inc.
|
||||
* Copyright (C) 2008 Nokia Corporation
|
||||
*
|
||||
* Written by Paul Walmsley and Jouni Högander
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
#ifdef CONFIG_OMAP_DEBUG_CLOCKDOMAIN
|
||||
# define DEBUG
|
||||
#endif
|
||||
|
||||
#include <linux/module.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/device.h>
|
||||
#include <linux/list.h>
|
||||
#include <linux/errno.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/clk.h>
|
||||
#include <linux/limits.h>
|
||||
|
||||
#include <linux/io.h>
|
||||
|
||||
#include <linux/bitops.h>
|
||||
|
||||
#include <mach/clock.h>
|
||||
|
||||
#include "prm.h"
|
||||
#include "prm-regbits-24xx.h"
|
||||
#include "cm.h"
|
||||
|
||||
#include <mach/powerdomain.h>
|
||||
#include <mach/clockdomain.h>
|
||||
|
||||
/* clkdm_list contains all registered struct clockdomains */
|
||||
static LIST_HEAD(clkdm_list);
|
||||
|
||||
/* clkdm_mutex protects clkdm_list add and del ops */
|
||||
static DEFINE_MUTEX(clkdm_mutex);
|
||||
|
||||
/* array of powerdomain deps to be added/removed when clkdm in hwsup mode */
|
||||
static struct clkdm_pwrdm_autodep *autodeps;
|
||||
|
||||
|
||||
/* Private functions */
|
||||
|
||||
/*
|
||||
* _autodep_lookup - resolve autodep pwrdm names to pwrdm pointers; store
|
||||
* @autodep: struct clkdm_pwrdm_autodep * to resolve
|
||||
*
|
||||
* Resolve autodep powerdomain names to powerdomain pointers via
|
||||
* pwrdm_lookup() and store the pointers in the autodep structure. An
|
||||
* "autodep" is a powerdomain sleep/wakeup dependency that is
|
||||
* automatically added and removed whenever clocks in the associated
|
||||
* clockdomain are enabled or disabled (respectively) when the
|
||||
* clockdomain is in hardware-supervised mode. Meant to be called
|
||||
* once at clockdomain layer initialization, since these should remain
|
||||
* fixed for a particular architecture. No return value.
|
||||
*/
|
||||
static void _autodep_lookup(struct clkdm_pwrdm_autodep *autodep)
|
||||
{
|
||||
struct powerdomain *pwrdm;
|
||||
|
||||
if (!autodep)
|
||||
return;
|
||||
|
||||
if (!omap_chip_is(autodep->omap_chip))
|
||||
return;
|
||||
|
||||
pwrdm = pwrdm_lookup(autodep->pwrdm_name);
|
||||
if (!pwrdm) {
|
||||
pr_debug("clockdomain: _autodep_lookup: powerdomain %s "
|
||||
"does not exist\n", autodep->pwrdm_name);
|
||||
WARN_ON(1);
|
||||
return;
|
||||
}
|
||||
autodep->pwrdm = pwrdm;
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
/*
|
||||
* _clkdm_add_autodeps - add auto sleepdeps/wkdeps to clkdm upon clock enable
|
||||
* @clkdm: struct clockdomain *
|
||||
*
|
||||
* Add the "autodep" sleep & wakeup dependencies to clockdomain 'clkdm'
|
||||
* in hardware-supervised mode. Meant to be called from clock framework
|
||||
* when a clock inside clockdomain 'clkdm' is enabled. No return value.
|
||||
*/
|
||||
static void _clkdm_add_autodeps(struct clockdomain *clkdm)
|
||||
{
|
||||
struct clkdm_pwrdm_autodep *autodep;
|
||||
|
||||
for (autodep = autodeps; autodep->pwrdm_name; autodep++) {
|
||||
if (!autodep->pwrdm)
|
||||
continue;
|
||||
|
||||
pr_debug("clockdomain: adding %s sleepdep/wkdep for "
|
||||
"pwrdm %s\n", autodep->pwrdm_name,
|
||||
clkdm->pwrdm->name);
|
||||
|
||||
pwrdm_add_sleepdep(clkdm->pwrdm, autodep->pwrdm);
|
||||
pwrdm_add_wkdep(clkdm->pwrdm, autodep->pwrdm);
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* _clkdm_add_autodeps - remove auto sleepdeps/wkdeps from clkdm
|
||||
* @clkdm: struct clockdomain *
|
||||
*
|
||||
* Remove the "autodep" sleep & wakeup dependencies from clockdomain 'clkdm'
|
||||
* in hardware-supervised mode. Meant to be called from clock framework
|
||||
* when a clock inside clockdomain 'clkdm' is disabled. No return value.
|
||||
*/
|
||||
static void _clkdm_del_autodeps(struct clockdomain *clkdm)
|
||||
{
|
||||
struct clkdm_pwrdm_autodep *autodep;
|
||||
|
||||
for (autodep = autodeps; autodep->pwrdm_name; autodep++) {
|
||||
if (!autodep->pwrdm)
|
||||
continue;
|
||||
|
||||
pr_debug("clockdomain: removing %s sleepdep/wkdep for "
|
||||
"pwrdm %s\n", autodep->pwrdm_name,
|
||||
clkdm->pwrdm->name);
|
||||
|
||||
pwrdm_del_sleepdep(clkdm->pwrdm, autodep->pwrdm);
|
||||
pwrdm_del_wkdep(clkdm->pwrdm, autodep->pwrdm);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
static struct clockdomain *_clkdm_lookup(const char *name)
|
||||
{
|
||||
struct clockdomain *clkdm, *temp_clkdm;
|
||||
|
||||
if (!name)
|
||||
return NULL;
|
||||
|
||||
clkdm = NULL;
|
||||
|
||||
list_for_each_entry(temp_clkdm, &clkdm_list, node) {
|
||||
if (!strcmp(name, temp_clkdm->name)) {
|
||||
clkdm = temp_clkdm;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
return clkdm;
|
||||
}
|
||||
|
||||
|
||||
/* Public functions */
|
||||
|
||||
/**
|
||||
* clkdm_init - set up the clockdomain layer
|
||||
* @clkdms: optional pointer to an array of clockdomains to register
|
||||
* @init_autodeps: optional pointer to an array of autodeps to register
|
||||
*
|
||||
* Set up internal state. If a pointer to an array of clockdomains
|
||||
* was supplied, loop through the list of clockdomains, register all
|
||||
* that are available on the current platform. Similarly, if a
|
||||
* pointer to an array of clockdomain-powerdomain autodependencies was
|
||||
* provided, register those. No return value.
|
||||
*/
|
||||
void clkdm_init(struct clockdomain **clkdms,
|
||||
struct clkdm_pwrdm_autodep *init_autodeps)
|
||||
{
|
||||
struct clockdomain **c = NULL;
|
||||
struct clkdm_pwrdm_autodep *autodep = NULL;
|
||||
|
||||
if (clkdms)
|
||||
for (c = clkdms; *c; c++)
|
||||
clkdm_register(*c);
|
||||
|
||||
autodeps = init_autodeps;
|
||||
if (autodeps)
|
||||
for (autodep = autodeps; autodep->pwrdm_name; autodep++)
|
||||
_autodep_lookup(autodep);
|
||||
}
|
||||
|
||||
/**
|
||||
* clkdm_register - register a clockdomain
|
||||
* @clkdm: struct clockdomain * to register
|
||||
*
|
||||
* Adds a clockdomain to the internal clockdomain list.
|
||||
* Returns -EINVAL if given a null pointer, -EEXIST if a clockdomain is
|
||||
* already registered by the provided name, or 0 upon success.
|
||||
*/
|
||||
int clkdm_register(struct clockdomain *clkdm)
|
||||
{
|
||||
int ret = -EINVAL;
|
||||
struct powerdomain *pwrdm;
|
||||
|
||||
if (!clkdm || !clkdm->name)
|
||||
return -EINVAL;
|
||||
|
||||
if (!omap_chip_is(clkdm->omap_chip))
|
||||
return -EINVAL;
|
||||
|
||||
pwrdm = pwrdm_lookup(clkdm->pwrdm_name);
|
||||
if (!pwrdm) {
|
||||
pr_debug("clockdomain: clkdm_register %s: powerdomain %s "
|
||||
"does not exist\n", clkdm->name, clkdm->pwrdm_name);
|
||||
return -EINVAL;
|
||||
}
|
||||
clkdm->pwrdm = pwrdm;
|
||||
|
||||
mutex_lock(&clkdm_mutex);
|
||||
/* Verify that the clockdomain is not already registered */
|
||||
if (_clkdm_lookup(clkdm->name)) {
|
||||
ret = -EEXIST;
|
||||
goto cr_unlock;
|
||||
};
|
||||
|
||||
list_add(&clkdm->node, &clkdm_list);
|
||||
|
||||
pwrdm_add_clkdm(pwrdm, clkdm);
|
||||
|
||||
pr_debug("clockdomain: registered %s\n", clkdm->name);
|
||||
ret = 0;
|
||||
|
||||
cr_unlock:
|
||||
mutex_unlock(&clkdm_mutex);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
* clkdm_unregister - unregister a clockdomain
|
||||
* @clkdm: struct clockdomain * to unregister
|
||||
*
|
||||
* Removes a clockdomain from the internal clockdomain list. Returns
|
||||
* -EINVAL if clkdm argument is NULL.
|
||||
*/
|
||||
int clkdm_unregister(struct clockdomain *clkdm)
|
||||
{
|
||||
if (!clkdm)
|
||||
return -EINVAL;
|
||||
|
||||
pwrdm_del_clkdm(clkdm->pwrdm, clkdm);
|
||||
|
||||
mutex_lock(&clkdm_mutex);
|
||||
list_del(&clkdm->node);
|
||||
mutex_unlock(&clkdm_mutex);
|
||||
|
||||
pr_debug("clockdomain: unregistered %s\n", clkdm->name);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* clkdm_lookup - look up a clockdomain by name, return a pointer
|
||||
* @name: name of clockdomain
|
||||
*
|
||||
* Find a registered clockdomain by its name. Returns a pointer to the
|
||||
* struct clockdomain if found, or NULL otherwise.
|
||||
*/
|
||||
struct clockdomain *clkdm_lookup(const char *name)
|
||||
{
|
||||
struct clockdomain *clkdm, *temp_clkdm;
|
||||
|
||||
if (!name)
|
||||
return NULL;
|
||||
|
||||
clkdm = NULL;
|
||||
|
||||
mutex_lock(&clkdm_mutex);
|
||||
list_for_each_entry(temp_clkdm, &clkdm_list, node) {
|
||||
if (!strcmp(name, temp_clkdm->name)) {
|
||||
clkdm = temp_clkdm;
|
||||
break;
|
||||
}
|
||||
}
|
||||
mutex_unlock(&clkdm_mutex);
|
||||
|
||||
return clkdm;
|
||||
}
|
||||
|
||||
/**
|
||||
* clkdm_for_each - call function on each registered clockdomain
|
||||
* @fn: callback function *
|
||||
*
|
||||
* Call the supplied function for each registered clockdomain.
|
||||
* The callback function can return anything but 0 to bail
|
||||
* out early from the iterator. The callback function is called with
|
||||
* the clkdm_mutex held, so no clockdomain structure manipulation
|
||||
* functions should be called from the callback, although hardware
|
||||
* clockdomain control functions are fine. Returns the last return
|
||||
* value of the callback function, which should be 0 for success or
|
||||
* anything else to indicate failure; or -EINVAL if the function pointer
|
||||
* is null.
|
||||
*/
|
||||
int clkdm_for_each(int (*fn)(struct clockdomain *clkdm))
|
||||
{
|
||||
struct clockdomain *clkdm;
|
||||
int ret = 0;
|
||||
|
||||
if (!fn)
|
||||
return -EINVAL;
|
||||
|
||||
mutex_lock(&clkdm_mutex);
|
||||
list_for_each_entry(clkdm, &clkdm_list, node) {
|
||||
ret = (*fn)(clkdm);
|
||||
if (ret)
|
||||
break;
|
||||
}
|
||||
mutex_unlock(&clkdm_mutex);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* clkdm_get_pwrdm - return a ptr to the pwrdm that this clkdm resides in
|
||||
* @clkdm: struct clockdomain *
|
||||
*
|
||||
* Return a pointer to the struct powerdomain that the specified clockdomain
|
||||
* 'clkdm' exists in, or returns NULL if clkdm argument is NULL.
|
||||
*/
|
||||
struct powerdomain *clkdm_get_pwrdm(struct clockdomain *clkdm)
|
||||
{
|
||||
if (!clkdm)
|
||||
return NULL;
|
||||
|
||||
return clkdm->pwrdm;
|
||||
}
|
||||
|
||||
|
||||
/* Hardware clockdomain control */
|
||||
|
||||
/**
|
||||
* omap2_clkdm_clktrctrl_read - read the clkdm's current state transition mode
|
||||
* @clk: struct clk * of a clockdomain
|
||||
*
|
||||
* Return the clockdomain's current state transition mode from the
|
||||
* corresponding domain CM_CLKSTCTRL register. Returns -EINVAL if clk
|
||||
* is NULL or the current mode upon success.
|
||||
*/
|
||||
static int omap2_clkdm_clktrctrl_read(struct clockdomain *clkdm)
|
||||
{
|
||||
u32 v;
|
||||
|
||||
if (!clkdm)
|
||||
return -EINVAL;
|
||||
|
||||
v = cm_read_mod_reg(clkdm->pwrdm->prcm_offs, CM_CLKSTCTRL);
|
||||
v &= clkdm->clktrctrl_mask;
|
||||
v >>= __ffs(clkdm->clktrctrl_mask);
|
||||
|
||||
return v;
|
||||
}
|
||||
|
||||
/**
|
||||
* omap2_clkdm_sleep - force clockdomain sleep transition
|
||||
* @clkdm: struct clockdomain *
|
||||
*
|
||||
* Instruct the CM to force a sleep transition on the specified
|
||||
* clockdomain 'clkdm'. Returns -EINVAL if clk is NULL or if
|
||||
* clockdomain does not support software-initiated sleep; 0 upon
|
||||
* success.
|
||||
*/
|
||||
int omap2_clkdm_sleep(struct clockdomain *clkdm)
|
||||
{
|
||||
if (!clkdm)
|
||||
return -EINVAL;
|
||||
|
||||
if (!(clkdm->flags & CLKDM_CAN_FORCE_SLEEP)) {
|
||||
pr_debug("clockdomain: %s does not support forcing "
|
||||
"sleep via software\n", clkdm->name);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
pr_debug("clockdomain: forcing sleep on %s\n", clkdm->name);
|
||||
|
||||
if (cpu_is_omap24xx()) {
|
||||
|
||||
cm_set_mod_reg_bits(OMAP24XX_FORCESTATE,
|
||||
clkdm->pwrdm->prcm_offs, PM_PWSTCTRL);
|
||||
|
||||
} else if (cpu_is_omap34xx()) {
|
||||
|
||||
u32 v = (OMAP34XX_CLKSTCTRL_FORCE_SLEEP <<
|
||||
__ffs(clkdm->clktrctrl_mask));
|
||||
|
||||
cm_rmw_mod_reg_bits(clkdm->clktrctrl_mask, v,
|
||||
clkdm->pwrdm->prcm_offs, CM_CLKSTCTRL);
|
||||
|
||||
} else {
|
||||
BUG();
|
||||
};
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* omap2_clkdm_wakeup - force clockdomain wakeup transition
|
||||
* @clkdm: struct clockdomain *
|
||||
*
|
||||
* Instruct the CM to force a wakeup transition on the specified
|
||||
* clockdomain 'clkdm'. Returns -EINVAL if clkdm is NULL or if the
|
||||
* clockdomain does not support software-controlled wakeup; 0 upon
|
||||
* success.
|
||||
*/
|
||||
int omap2_clkdm_wakeup(struct clockdomain *clkdm)
|
||||
{
|
||||
if (!clkdm)
|
||||
return -EINVAL;
|
||||
|
||||
if (!(clkdm->flags & CLKDM_CAN_FORCE_WAKEUP)) {
|
||||
pr_debug("clockdomain: %s does not support forcing "
|
||||
"wakeup via software\n", clkdm->name);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
pr_debug("clockdomain: forcing wakeup on %s\n", clkdm->name);
|
||||
|
||||
if (cpu_is_omap24xx()) {
|
||||
|
||||
cm_clear_mod_reg_bits(OMAP24XX_FORCESTATE,
|
||||
clkdm->pwrdm->prcm_offs, PM_PWSTCTRL);
|
||||
|
||||
} else if (cpu_is_omap34xx()) {
|
||||
|
||||
u32 v = (OMAP34XX_CLKSTCTRL_FORCE_WAKEUP <<
|
||||
__ffs(clkdm->clktrctrl_mask));
|
||||
|
||||
cm_rmw_mod_reg_bits(clkdm->clktrctrl_mask, v,
|
||||
clkdm->pwrdm->prcm_offs, CM_CLKSTCTRL);
|
||||
|
||||
} else {
|
||||
BUG();
|
||||
};
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* omap2_clkdm_allow_idle - enable hwsup idle transitions for clkdm
|
||||
* @clkdm: struct clockdomain *
|
||||
*
|
||||
* Allow the hardware to automatically switch the clockdomain into
|
||||
* active or idle states, as needed by downstream clocks. If the
|
||||
* clockdomain has any downstream clocks enabled in the clock
|
||||
* framework, wkdep/sleepdep autodependencies are added; this is so
|
||||
* device drivers can read and write to the device. No return value.
|
||||
*/
|
||||
void omap2_clkdm_allow_idle(struct clockdomain *clkdm)
|
||||
{
|
||||
u32 v;
|
||||
|
||||
if (!clkdm)
|
||||
return;
|
||||
|
||||
if (!(clkdm->flags & CLKDM_CAN_ENABLE_AUTO)) {
|
||||
pr_debug("clock: automatic idle transitions cannot be enabled "
|
||||
"on clockdomain %s\n", clkdm->name);
|
||||
return;
|
||||
}
|
||||
|
||||
pr_debug("clockdomain: enabling automatic idle transitions for %s\n",
|
||||
clkdm->name);
|
||||
|
||||
if (atomic_read(&clkdm->usecount) > 0)
|
||||
_clkdm_add_autodeps(clkdm);
|
||||
|
||||
if (cpu_is_omap24xx())
|
||||
v = OMAP24XX_CLKSTCTRL_ENABLE_AUTO;
|
||||
else if (cpu_is_omap34xx())
|
||||
v = OMAP34XX_CLKSTCTRL_ENABLE_AUTO;
|
||||
else
|
||||
BUG();
|
||||
|
||||
|
||||
cm_rmw_mod_reg_bits(clkdm->clktrctrl_mask,
|
||||
v << __ffs(clkdm->clktrctrl_mask),
|
||||
clkdm->pwrdm->prcm_offs,
|
||||
CM_CLKSTCTRL);
|
||||
}
|
||||
|
||||
/**
|
||||
* omap2_clkdm_deny_idle - disable hwsup idle transitions for clkdm
|
||||
* @clkdm: struct clockdomain *
|
||||
*
|
||||
* Prevent the hardware from automatically switching the clockdomain
|
||||
* into inactive or idle states. If the clockdomain has downstream
|
||||
* clocks enabled in the clock framework, wkdep/sleepdep
|
||||
* autodependencies are removed. No return value.
|
||||
*/
|
||||
void omap2_clkdm_deny_idle(struct clockdomain *clkdm)
|
||||
{
|
||||
u32 v;
|
||||
|
||||
if (!clkdm)
|
||||
return;
|
||||
|
||||
if (!(clkdm->flags & CLKDM_CAN_DISABLE_AUTO)) {
|
||||
pr_debug("clockdomain: automatic idle transitions cannot be "
|
||||
"disabled on %s\n", clkdm->name);
|
||||
return;
|
||||
}
|
||||
|
||||
pr_debug("clockdomain: disabling automatic idle transitions for %s\n",
|
||||
clkdm->name);
|
||||
|
||||
if (cpu_is_omap24xx())
|
||||
v = OMAP24XX_CLKSTCTRL_DISABLE_AUTO;
|
||||
else if (cpu_is_omap34xx())
|
||||
v = OMAP34XX_CLKSTCTRL_DISABLE_AUTO;
|
||||
else
|
||||
BUG();
|
||||
|
||||
cm_rmw_mod_reg_bits(clkdm->clktrctrl_mask,
|
||||
v << __ffs(clkdm->clktrctrl_mask),
|
||||
clkdm->pwrdm->prcm_offs, CM_CLKSTCTRL);
|
||||
|
||||
if (atomic_read(&clkdm->usecount) > 0)
|
||||
_clkdm_del_autodeps(clkdm);
|
||||
}
|
||||
|
||||
|
||||
/* Clockdomain-to-clock framework interface code */
|
||||
|
||||
/**
|
||||
* omap2_clkdm_clk_enable - add an enabled downstream clock to this clkdm
|
||||
* @clkdm: struct clockdomain *
|
||||
* @clk: struct clk * of the enabled downstream clock
|
||||
*
|
||||
* Increment the usecount of this clockdomain 'clkdm' and ensure that
|
||||
* it is awake. Intended to be called by clk_enable() code. If the
|
||||
* clockdomain is in software-supervised idle mode, force the
|
||||
* clockdomain to wake. If the clockdomain is in hardware-supervised
|
||||
* idle mode, add clkdm-pwrdm autodependencies, to ensure that devices
|
||||
* in the clockdomain can be read from/written to by on-chip processors.
|
||||
* Returns -EINVAL if passed null pointers; returns 0 upon success or
|
||||
* if the clockdomain is in hwsup idle mode.
|
||||
*/
|
||||
int omap2_clkdm_clk_enable(struct clockdomain *clkdm, struct clk *clk)
|
||||
{
|
||||
int v;
|
||||
|
||||
/*
|
||||
* XXX Rewrite this code to maintain a list of enabled
|
||||
* downstream clocks for debugging purposes?
|
||||
*/
|
||||
|
||||
if (!clkdm || !clk)
|
||||
return -EINVAL;
|
||||
|
||||
if (atomic_inc_return(&clkdm->usecount) > 1)
|
||||
return 0;
|
||||
|
||||
/* Clockdomain now has one enabled downstream clock */
|
||||
|
||||
pr_debug("clockdomain: clkdm %s: clk %s now enabled\n", clkdm->name,
|
||||
clk->name);
|
||||
|
||||
v = omap2_clkdm_clktrctrl_read(clkdm);
|
||||
|
||||
if ((cpu_is_omap34xx() && v == OMAP34XX_CLKSTCTRL_ENABLE_AUTO) ||
|
||||
(cpu_is_omap24xx() && v == OMAP24XX_CLKSTCTRL_ENABLE_AUTO))
|
||||
_clkdm_add_autodeps(clkdm);
|
||||
else
|
||||
omap2_clkdm_wakeup(clkdm);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* omap2_clkdm_clk_disable - remove an enabled downstream clock from this clkdm
|
||||
* @clkdm: struct clockdomain *
|
||||
* @clk: struct clk * of the disabled downstream clock
|
||||
*
|
||||
* Decrement the usecount of this clockdomain 'clkdm'. Intended to be
|
||||
* called by clk_disable() code. If the usecount goes to 0, put the
|
||||
* clockdomain to sleep (software-supervised mode) or remove the
|
||||
* clkdm-pwrdm autodependencies (hardware-supervised mode). Returns
|
||||
* -EINVAL if passed null pointers; -ERANGE if the clkdm usecount
|
||||
* underflows and debugging is enabled; or returns 0 upon success or
|
||||
* if the clockdomain is in hwsup idle mode.
|
||||
*/
|
||||
int omap2_clkdm_clk_disable(struct clockdomain *clkdm, struct clk *clk)
|
||||
{
|
||||
int v;
|
||||
|
||||
/*
|
||||
* XXX Rewrite this code to maintain a list of enabled
|
||||
* downstream clocks for debugging purposes?
|
||||
*/
|
||||
|
||||
if (!clkdm || !clk)
|
||||
return -EINVAL;
|
||||
|
||||
#ifdef DEBUG
|
||||
if (atomic_read(&clkdm->usecount) == 0) {
|
||||
WARN_ON(1); /* underflow */
|
||||
return -ERANGE;
|
||||
}
|
||||
#endif
|
||||
|
||||
if (atomic_dec_return(&clkdm->usecount) > 0)
|
||||
return 0;
|
||||
|
||||
/* All downstream clocks of this clockdomain are now disabled */
|
||||
|
||||
pr_debug("clockdomain: clkdm %s: clk %s now disabled\n", clkdm->name,
|
||||
clk->name);
|
||||
|
||||
v = omap2_clkdm_clktrctrl_read(clkdm);
|
||||
|
||||
if ((cpu_is_omap34xx() && v == OMAP34XX_CLKSTCTRL_ENABLE_AUTO) ||
|
||||
(cpu_is_omap24xx() && v == OMAP24XX_CLKSTCTRL_ENABLE_AUTO))
|
||||
_clkdm_del_autodeps(clkdm);
|
||||
else
|
||||
omap2_clkdm_sleep(clkdm);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
305
arch/arm/mach-omap2/clockdomains.h
Normal file
305
arch/arm/mach-omap2/clockdomains.h
Normal file
|
@ -0,0 +1,305 @@
|
|||
/*
|
||||
* OMAP2/3 clockdomains
|
||||
*
|
||||
* Copyright (C) 2008 Texas Instruments, Inc.
|
||||
* Copyright (C) 2008 Nokia Corporation
|
||||
*
|
||||
* Written by Paul Walmsley
|
||||
*/
|
||||
|
||||
#ifndef __ARCH_ARM_MACH_OMAP2_CLOCKDOMAINS_H
|
||||
#define __ARCH_ARM_MACH_OMAP2_CLOCKDOMAINS_H
|
||||
|
||||
#include <mach/clockdomain.h>
|
||||
|
||||
/*
|
||||
* OMAP2/3-common clockdomains
|
||||
*/
|
||||
|
||||
/* This is an implicit clockdomain - it is never defined as such in TRM */
|
||||
static struct clockdomain wkup_clkdm = {
|
||||
.name = "wkup_clkdm",
|
||||
.pwrdm_name = "wkup_pwrdm",
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX | CHIP_IS_OMAP3430),
|
||||
};
|
||||
|
||||
/*
|
||||
* 2420-only clockdomains
|
||||
*/
|
||||
|
||||
#if defined(CONFIG_ARCH_OMAP2420)
|
||||
|
||||
static struct clockdomain mpu_2420_clkdm = {
|
||||
.name = "mpu_clkdm",
|
||||
.pwrdm_name = "mpu_pwrdm",
|
||||
.flags = CLKDM_CAN_HWSUP,
|
||||
.clktrctrl_mask = OMAP24XX_AUTOSTATE_MPU_MASK,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
|
||||
};
|
||||
|
||||
static struct clockdomain iva1_2420_clkdm = {
|
||||
.name = "iva1_clkdm",
|
||||
.pwrdm_name = "dsp_pwrdm",
|
||||
.flags = CLKDM_CAN_HWSUP_SWSUP,
|
||||
.clktrctrl_mask = OMAP2420_AUTOSTATE_IVA_MASK,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
|
||||
};
|
||||
|
||||
#endif /* CONFIG_ARCH_OMAP2420 */
|
||||
|
||||
|
||||
/*
|
||||
* 2430-only clockdomains
|
||||
*/
|
||||
|
||||
#if defined(CONFIG_ARCH_OMAP2430)
|
||||
|
||||
static struct clockdomain mpu_2430_clkdm = {
|
||||
.name = "mpu_clkdm",
|
||||
.pwrdm_name = "mpu_pwrdm",
|
||||
.flags = CLKDM_CAN_HWSUP_SWSUP,
|
||||
.clktrctrl_mask = OMAP24XX_AUTOSTATE_MPU_MASK,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
|
||||
};
|
||||
|
||||
static struct clockdomain mdm_clkdm = {
|
||||
.name = "mdm_clkdm",
|
||||
.pwrdm_name = "mdm_pwrdm",
|
||||
.flags = CLKDM_CAN_HWSUP_SWSUP,
|
||||
.clktrctrl_mask = OMAP2430_AUTOSTATE_MDM_MASK,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
|
||||
};
|
||||
|
||||
#endif /* CONFIG_ARCH_OMAP2430 */
|
||||
|
||||
|
||||
/*
|
||||
* 24XX-only clockdomains
|
||||
*/
|
||||
|
||||
#if defined(CONFIG_ARCH_OMAP24XX)
|
||||
|
||||
static struct clockdomain dsp_clkdm = {
|
||||
.name = "dsp_clkdm",
|
||||
.pwrdm_name = "dsp_pwrdm",
|
||||
.flags = CLKDM_CAN_HWSUP_SWSUP,
|
||||
.clktrctrl_mask = OMAP24XX_AUTOSTATE_DSP_MASK,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX),
|
||||
};
|
||||
|
||||
static struct clockdomain gfx_24xx_clkdm = {
|
||||
.name = "gfx_clkdm",
|
||||
.pwrdm_name = "gfx_pwrdm",
|
||||
.flags = CLKDM_CAN_HWSUP_SWSUP,
|
||||
.clktrctrl_mask = OMAP24XX_AUTOSTATE_GFX_MASK,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX),
|
||||
};
|
||||
|
||||
static struct clockdomain core_l3_24xx_clkdm = {
|
||||
.name = "core_l3_clkdm",
|
||||
.pwrdm_name = "core_pwrdm",
|
||||
.flags = CLKDM_CAN_HWSUP,
|
||||
.clktrctrl_mask = OMAP24XX_AUTOSTATE_L3_MASK,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX),
|
||||
};
|
||||
|
||||
static struct clockdomain core_l4_24xx_clkdm = {
|
||||
.name = "core_l4_clkdm",
|
||||
.pwrdm_name = "core_pwrdm",
|
||||
.flags = CLKDM_CAN_HWSUP,
|
||||
.clktrctrl_mask = OMAP24XX_AUTOSTATE_L4_MASK,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX),
|
||||
};
|
||||
|
||||
static struct clockdomain dss_24xx_clkdm = {
|
||||
.name = "dss_clkdm",
|
||||
.pwrdm_name = "core_pwrdm",
|
||||
.flags = CLKDM_CAN_HWSUP,
|
||||
.clktrctrl_mask = OMAP24XX_AUTOSTATE_DSS_MASK,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX),
|
||||
};
|
||||
|
||||
#endif /* CONFIG_ARCH_OMAP24XX */
|
||||
|
||||
|
||||
/*
|
||||
* 34xx clockdomains
|
||||
*/
|
||||
|
||||
#if defined(CONFIG_ARCH_OMAP34XX)
|
||||
|
||||
static struct clockdomain mpu_34xx_clkdm = {
|
||||
.name = "mpu_clkdm",
|
||||
.pwrdm_name = "mpu_pwrdm",
|
||||
.flags = CLKDM_CAN_HWSUP | CLKDM_CAN_FORCE_WAKEUP,
|
||||
.clktrctrl_mask = OMAP3430_CLKTRCTRL_MPU_MASK,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
|
||||
};
|
||||
|
||||
static struct clockdomain neon_clkdm = {
|
||||
.name = "neon_clkdm",
|
||||
.pwrdm_name = "neon_pwrdm",
|
||||
.flags = CLKDM_CAN_HWSUP_SWSUP,
|
||||
.clktrctrl_mask = OMAP3430_CLKTRCTRL_NEON_MASK,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
|
||||
};
|
||||
|
||||
static struct clockdomain iva2_clkdm = {
|
||||
.name = "iva2_clkdm",
|
||||
.pwrdm_name = "iva2_pwrdm",
|
||||
.flags = CLKDM_CAN_HWSUP_SWSUP,
|
||||
.clktrctrl_mask = OMAP3430_CLKTRCTRL_IVA2_MASK,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
|
||||
};
|
||||
|
||||
static struct clockdomain gfx_3430es1_clkdm = {
|
||||
.name = "gfx_clkdm",
|
||||
.pwrdm_name = "gfx_pwrdm",
|
||||
.flags = CLKDM_CAN_HWSUP_SWSUP,
|
||||
.clktrctrl_mask = OMAP3430ES1_CLKTRCTRL_GFX_MASK,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1),
|
||||
};
|
||||
|
||||
static struct clockdomain sgx_clkdm = {
|
||||
.name = "sgx_clkdm",
|
||||
.pwrdm_name = "sgx_pwrdm",
|
||||
.flags = CLKDM_CAN_HWSUP_SWSUP,
|
||||
.clktrctrl_mask = OMAP3430ES2_CLKTRCTRL_SGX_MASK,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES2),
|
||||
};
|
||||
|
||||
/*
|
||||
* The die-to-die clockdomain was documented in the 34xx ES1 TRM, but
|
||||
* then that information was removed from the 34xx ES2+ TRM. It is
|
||||
* unclear whether the core is still there, but the clockdomain logic
|
||||
* is there, and must be programmed to an appropriate state if the
|
||||
* CORE clockdomain is to become inactive.
|
||||
*/
|
||||
static struct clockdomain d2d_clkdm = {
|
||||
.name = "d2d_clkdm",
|
||||
.pwrdm_name = "core_pwrdm",
|
||||
.flags = CLKDM_CAN_HWSUP,
|
||||
.clktrctrl_mask = OMAP3430ES1_CLKTRCTRL_D2D_MASK,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
|
||||
};
|
||||
|
||||
static struct clockdomain core_l3_34xx_clkdm = {
|
||||
.name = "core_l3_clkdm",
|
||||
.pwrdm_name = "core_pwrdm",
|
||||
.flags = CLKDM_CAN_HWSUP,
|
||||
.clktrctrl_mask = OMAP3430_CLKTRCTRL_L3_MASK,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
|
||||
};
|
||||
|
||||
static struct clockdomain core_l4_34xx_clkdm = {
|
||||
.name = "core_l4_clkdm",
|
||||
.pwrdm_name = "core_pwrdm",
|
||||
.flags = CLKDM_CAN_HWSUP,
|
||||
.clktrctrl_mask = OMAP3430_CLKTRCTRL_L4_MASK,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
|
||||
};
|
||||
|
||||
static struct clockdomain dss_34xx_clkdm = {
|
||||
.name = "dss_clkdm",
|
||||
.pwrdm_name = "dss_pwrdm",
|
||||
.flags = CLKDM_CAN_HWSUP_SWSUP,
|
||||
.clktrctrl_mask = OMAP3430_CLKTRCTRL_DSS_MASK,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
|
||||
};
|
||||
|
||||
static struct clockdomain cam_clkdm = {
|
||||
.name = "cam_clkdm",
|
||||
.pwrdm_name = "cam_pwrdm",
|
||||
.flags = CLKDM_CAN_HWSUP_SWSUP,
|
||||
.clktrctrl_mask = OMAP3430_CLKTRCTRL_CAM_MASK,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
|
||||
};
|
||||
|
||||
static struct clockdomain usbhost_clkdm = {
|
||||
.name = "usbhost_clkdm",
|
||||
.pwrdm_name = "usbhost_pwrdm",
|
||||
.flags = CLKDM_CAN_HWSUP_SWSUP,
|
||||
.clktrctrl_mask = OMAP3430ES2_CLKTRCTRL_USBHOST_MASK,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES2),
|
||||
};
|
||||
|
||||
static struct clockdomain per_clkdm = {
|
||||
.name = "per_clkdm",
|
||||
.pwrdm_name = "per_pwrdm",
|
||||
.flags = CLKDM_CAN_HWSUP_SWSUP,
|
||||
.clktrctrl_mask = OMAP3430_CLKTRCTRL_PER_MASK,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
|
||||
};
|
||||
|
||||
static struct clockdomain emu_clkdm = {
|
||||
.name = "emu_clkdm",
|
||||
.pwrdm_name = "emu_pwrdm",
|
||||
.flags = CLKDM_CAN_ENABLE_AUTO | CLKDM_CAN_SWSUP,
|
||||
.clktrctrl_mask = OMAP3430_CLKTRCTRL_EMU_MASK,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
|
||||
};
|
||||
|
||||
#endif /* CONFIG_ARCH_OMAP34XX */
|
||||
|
||||
/*
|
||||
* Clockdomain-powerdomain hwsup dependencies (34XX only)
|
||||
*/
|
||||
|
||||
static struct clkdm_pwrdm_autodep clkdm_pwrdm_autodeps[] = {
|
||||
{
|
||||
.pwrdm_name = "mpu_pwrdm",
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
|
||||
},
|
||||
{
|
||||
.pwrdm_name = "iva2_pwrdm",
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
|
||||
},
|
||||
{ NULL }
|
||||
};
|
||||
|
||||
/*
|
||||
*
|
||||
*/
|
||||
|
||||
static struct clockdomain *clockdomains_omap[] = {
|
||||
|
||||
&wkup_clkdm,
|
||||
|
||||
#ifdef CONFIG_ARCH_OMAP2420
|
||||
&mpu_2420_clkdm,
|
||||
&iva1_2420_clkdm,
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_ARCH_OMAP2430
|
||||
&mpu_2430_clkdm,
|
||||
&mdm_clkdm,
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_ARCH_OMAP24XX
|
||||
&dsp_clkdm,
|
||||
&gfx_24xx_clkdm,
|
||||
&core_l3_24xx_clkdm,
|
||||
&core_l4_24xx_clkdm,
|
||||
&dss_24xx_clkdm,
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_ARCH_OMAP34XX
|
||||
&mpu_34xx_clkdm,
|
||||
&neon_clkdm,
|
||||
&iva2_clkdm,
|
||||
&gfx_3430es1_clkdm,
|
||||
&sgx_clkdm,
|
||||
&d2d_clkdm,
|
||||
&core_l3_34xx_clkdm,
|
||||
&core_l4_34xx_clkdm,
|
||||
&dss_34xx_clkdm,
|
||||
&cam_clkdm,
|
||||
&usbhost_clkdm,
|
||||
&per_clkdm,
|
||||
&emu_clkdm,
|
||||
#endif
|
||||
|
||||
NULL,
|
||||
};
|
||||
|
||||
#endif
|
|
@ -63,7 +63,8 @@
|
|||
#define OMAP24XX_CLKSEL_MPU_MASK (0x1f << 0)
|
||||
|
||||
/* CM_CLKSTCTRL_MPU */
|
||||
#define OMAP24XX_AUTOSTATE_MPU (1 << 0)
|
||||
#define OMAP24XX_AUTOSTATE_MPU_SHIFT 0
|
||||
#define OMAP24XX_AUTOSTATE_MPU_MASK (1 << 0)
|
||||
|
||||
/* CM_FCLKEN1_CORE specific bits*/
|
||||
#define OMAP24XX_EN_TV_SHIFT 2
|
||||
|
@ -238,9 +239,12 @@
|
|||
#define OMAP24XX_CLKSEL_GPT2_MASK (0x3 << 2)
|
||||
|
||||
/* CM_CLKSTCTRL_CORE */
|
||||
#define OMAP24XX_AUTOSTATE_DSS (1 << 2)
|
||||
#define OMAP24XX_AUTOSTATE_L4 (1 << 1)
|
||||
#define OMAP24XX_AUTOSTATE_L3 (1 << 0)
|
||||
#define OMAP24XX_AUTOSTATE_DSS_SHIFT 2
|
||||
#define OMAP24XX_AUTOSTATE_DSS_MASK (1 << 2)
|
||||
#define OMAP24XX_AUTOSTATE_L4_SHIFT 1
|
||||
#define OMAP24XX_AUTOSTATE_L4_MASK (1 << 1)
|
||||
#define OMAP24XX_AUTOSTATE_L3_SHIFT 0
|
||||
#define OMAP24XX_AUTOSTATE_L3_MASK (1 << 0)
|
||||
|
||||
/* CM_FCLKEN_GFX */
|
||||
#define OMAP24XX_EN_3D_SHIFT 2
|
||||
|
@ -255,7 +259,8 @@
|
|||
/* CM_CLKSEL_GFX specific bits */
|
||||
|
||||
/* CM_CLKSTCTRL_GFX */
|
||||
#define OMAP24XX_AUTOSTATE_GFX (1 << 0)
|
||||
#define OMAP24XX_AUTOSTATE_GFX_SHIFT 0
|
||||
#define OMAP24XX_AUTOSTATE_GFX_MASK (1 << 0)
|
||||
|
||||
/* CM_FCLKEN_WKUP specific bits */
|
||||
|
||||
|
@ -367,8 +372,10 @@
|
|||
#define OMAP24XX_CLKSEL_DSP_MASK (0x1f << 0)
|
||||
|
||||
/* CM_CLKSTCTRL_DSP */
|
||||
#define OMAP2420_AUTOSTATE_IVA (1 << 8)
|
||||
#define OMAP24XX_AUTOSTATE_DSP (1 << 0)
|
||||
#define OMAP2420_AUTOSTATE_IVA_SHIFT 8
|
||||
#define OMAP2420_AUTOSTATE_IVA_MASK (1 << 8)
|
||||
#define OMAP24XX_AUTOSTATE_DSP_SHIFT 0
|
||||
#define OMAP24XX_AUTOSTATE_DSP_MASK (1 << 0)
|
||||
|
||||
/* CM_FCLKEN_MDM */
|
||||
/* 2430 only */
|
||||
|
@ -396,6 +403,7 @@
|
|||
|
||||
/* CM_CLKSTCTRL_MDM */
|
||||
/* 2430 only */
|
||||
#define OMAP2430_AUTOSTATE_MDM (1 << 0)
|
||||
#define OMAP2430_AUTOSTATE_MDM_SHIFT 0
|
||||
#define OMAP2430_AUTOSTATE_MDM_MASK (1 << 0)
|
||||
|
||||
#endif
|
||||
|
|
|
@ -96,7 +96,8 @@
|
|||
#define OMAP3430_CLKTRCTRL_IVA2_MASK (0x3 << 0)
|
||||
|
||||
/* CM_CLKSTST_IVA2 */
|
||||
#define OMAP3430_CLKACTIVITY_IVA2 (1 << 0)
|
||||
#define OMAP3430_CLKACTIVITY_IVA2_SHIFT 0
|
||||
#define OMAP3430_CLKACTIVITY_IVA2_MASK (1 << 0)
|
||||
|
||||
/* CM_REVISION specific bits */
|
||||
|
||||
|
@ -140,7 +141,8 @@
|
|||
#define OMAP3430_CLKTRCTRL_MPU_MASK (0x3 << 0)
|
||||
|
||||
/* CM_CLKSTST_MPU */
|
||||
#define OMAP3430_CLKACTIVITY_MPU (1 << 0)
|
||||
#define OMAP3430_CLKACTIVITY_MPU_SHIFT 0
|
||||
#define OMAP3430_CLKACTIVITY_MPU_MASK (1 << 0)
|
||||
|
||||
/* CM_FCLKEN1_CORE specific bits */
|
||||
|
||||
|
@ -300,9 +302,12 @@
|
|||
#define OMAP3430_CLKTRCTRL_L3_MASK (0x3 << 0)
|
||||
|
||||
/* CM_CLKSTST_CORE */
|
||||
#define OMAP3430ES1_CLKACTIVITY_D2D (1 << 2)
|
||||
#define OMAP3430_CLKACTIVITY_L4 (1 << 1)
|
||||
#define OMAP3430_CLKACTIVITY_L3 (1 << 0)
|
||||
#define OMAP3430ES1_CLKACTIVITY_D2D_SHIFT 2
|
||||
#define OMAP3430ES1_CLKACTIVITY_D2D_MASK (1 << 2)
|
||||
#define OMAP3430_CLKACTIVITY_L4_SHIFT 1
|
||||
#define OMAP3430_CLKACTIVITY_L4_MASK (1 << 1)
|
||||
#define OMAP3430_CLKACTIVITY_L3_SHIFT 0
|
||||
#define OMAP3430_CLKACTIVITY_L3_MASK (1 << 0)
|
||||
|
||||
/* CM_FCLKEN_GFX */
|
||||
#define OMAP3430ES1_EN_3D (1 << 2)
|
||||
|
@ -323,7 +328,8 @@
|
|||
#define OMAP3430ES1_CLKTRCTRL_GFX_MASK (0x3 << 0)
|
||||
|
||||
/* CM_CLKSTST_GFX */
|
||||
#define OMAP3430ES1_CLKACTIVITY_GFX (1 << 0)
|
||||
#define OMAP3430ES1_CLKACTIVITY_GFX_SHIFT 0
|
||||
#define OMAP3430ES1_CLKACTIVITY_GFX_MASK (1 << 0)
|
||||
|
||||
/* CM_FCLKEN_SGX */
|
||||
#define OMAP3430ES2_EN_SGX_SHIFT 1
|
||||
|
@ -333,6 +339,14 @@
|
|||
#define OMAP3430ES2_CLKSEL_SGX_SHIFT 0
|
||||
#define OMAP3430ES2_CLKSEL_SGX_MASK (0x7 << 0)
|
||||
|
||||
/* CM_CLKSTCTRL_SGX */
|
||||
#define OMAP3430ES2_CLKTRCTRL_SGX_SHIFT 0
|
||||
#define OMAP3430ES2_CLKTRCTRL_SGX_MASK (0x3 << 0)
|
||||
|
||||
/* CM_CLKSTST_SGX */
|
||||
#define OMAP3430ES2_CLKACTIVITY_SGX_SHIFT 0
|
||||
#define OMAP3430ES2_CLKACTIVITY_SGX_MASK (1 << 0)
|
||||
|
||||
/* CM_FCLKEN_WKUP specific bits */
|
||||
#define OMAP3430ES2_EN_USIMOCP_SHIFT 9
|
||||
|
||||
|
@ -498,7 +512,8 @@
|
|||
#define OMAP3430_CLKTRCTRL_DSS_MASK (0x3 << 0)
|
||||
|
||||
/* CM_CLKSTST_DSS */
|
||||
#define OMAP3430_CLKACTIVITY_DSS (1 << 0)
|
||||
#define OMAP3430_CLKACTIVITY_DSS_SHIFT 0
|
||||
#define OMAP3430_CLKACTIVITY_DSS_MASK (1 << 0)
|
||||
|
||||
/* CM_FCLKEN_CAM specific bits */
|
||||
|
||||
|
@ -522,7 +537,8 @@
|
|||
#define OMAP3430_CLKTRCTRL_CAM_MASK (0x3 << 0)
|
||||
|
||||
/* CM_CLKSTST_CAM */
|
||||
#define OMAP3430_CLKACTIVITY_CAM (1 << 0)
|
||||
#define OMAP3430_CLKACTIVITY_CAM_SHIFT 0
|
||||
#define OMAP3430_CLKACTIVITY_CAM_MASK (1 << 0)
|
||||
|
||||
/* CM_FCLKEN_PER specific bits */
|
||||
|
||||
|
@ -598,7 +614,8 @@
|
|||
#define OMAP3430_CLKTRCTRL_PER_MASK (0x3 << 0)
|
||||
|
||||
/* CM_CLKSTST_PER */
|
||||
#define OMAP3430_CLKACTIVITY_PER (1 << 0)
|
||||
#define OMAP3430_CLKACTIVITY_PER_SHIFT 0
|
||||
#define OMAP3430_CLKACTIVITY_PER_MASK (1 << 0)
|
||||
|
||||
/* CM_CLKSEL1_EMU */
|
||||
#define OMAP3430_DIV_DPLL4_SHIFT 24
|
||||
|
@ -623,7 +640,8 @@
|
|||
#define OMAP3430_CLKTRCTRL_EMU_MASK (0x3 << 0)
|
||||
|
||||
/* CM_CLKSTST_EMU */
|
||||
#define OMAP3430_CLKACTIVITY_EMU (1 << 0)
|
||||
#define OMAP3430_CLKACTIVITY_EMU_SHIFT 0
|
||||
#define OMAP3430_CLKACTIVITY_EMU_MASK (1 << 0)
|
||||
|
||||
/* CM_CLKSEL2_EMU specific bits */
|
||||
#define OMAP3430_CORE_DPLL_EMU_MULT_SHIFT 8
|
||||
|
@ -673,6 +691,8 @@
|
|||
#define OMAP3430ES2_CLKTRCTRL_USBHOST_SHIFT 0
|
||||
#define OMAP3430ES2_CLKTRCTRL_USBHOST_MASK (3 << 0)
|
||||
|
||||
|
||||
/* CM_CLKSTST_USBHOST */
|
||||
#define OMAP3430ES2_CLKACTIVITY_USBHOST_SHIFT 0
|
||||
#define OMAP3430ES2_CLKACTIVITY_USBHOST_MASK (1 << 0)
|
||||
|
||||
#endif
|
||||
|
|
|
@ -18,7 +18,7 @@
|
|||
|
||||
#ifndef __ASSEMBLER__
|
||||
#define OMAP_CM_REGADDR(module, reg) \
|
||||
(void __iomem *)IO_ADDRESS(OMAP2_CM_BASE + (module) + (reg))
|
||||
IO_ADDRESS(OMAP2_CM_BASE + (module) + (reg))
|
||||
#else
|
||||
#define OMAP2420_CM_REGADDR(module, reg) \
|
||||
IO_ADDRESS(OMAP2420_CM_BASE + (module) + (reg))
|
||||
|
|
|
@ -23,50 +23,7 @@
|
|||
#include <mach/board.h>
|
||||
#include <mach/mux.h>
|
||||
#include <mach/gpio.h>
|
||||
|
||||
#if defined(CONFIG_I2C_OMAP) || defined(CONFIG_I2C_OMAP_MODULE)
|
||||
|
||||
#define OMAP2_I2C_BASE2 0x48072000
|
||||
#define OMAP2_I2C_INT2 57
|
||||
|
||||
static struct resource i2c_resources2[] = {
|
||||
{
|
||||
.start = OMAP2_I2C_BASE2,
|
||||
.end = OMAP2_I2C_BASE2 + 0x3f,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
{
|
||||
.start = OMAP2_I2C_INT2,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device omap_i2c_device2 = {
|
||||
.name = "i2c_omap",
|
||||
.id = 2,
|
||||
.num_resources = ARRAY_SIZE(i2c_resources2),
|
||||
.resource = i2c_resources2,
|
||||
};
|
||||
|
||||
/* See also arch/arm/plat-omap/devices.c for first I2C on 24xx */
|
||||
static void omap_init_i2c(void)
|
||||
{
|
||||
/* REVISIT: Second I2C not in use on H4? */
|
||||
if (machine_is_omap_h4())
|
||||
return;
|
||||
|
||||
if (!cpu_is_omap2430()) {
|
||||
omap_cfg_reg(J15_24XX_I2C2_SCL);
|
||||
omap_cfg_reg(H19_24XX_I2C2_SDA);
|
||||
}
|
||||
(void) platform_device_register(&omap_i2c_device2);
|
||||
}
|
||||
|
||||
#else
|
||||
|
||||
static void omap_init_i2c(void) {}
|
||||
|
||||
#endif
|
||||
#include <mach/eac.h>
|
||||
|
||||
#if defined(CONFIG_OMAP_DSP) || defined(CONFIG_OMAP_DSP_MODULE)
|
||||
#define OMAP2_MBOX_BASE IO_ADDRESS(OMAP24XX_MAILBOX_BASE)
|
||||
|
@ -104,7 +61,9 @@ static inline void omap_init_mbox(void) { }
|
|||
|
||||
#if defined(CONFIG_OMAP_STI)
|
||||
|
||||
#define OMAP2_STI_BASE IO_ADDRESS(0x48068000)
|
||||
#if defined(CONFIG_ARCH_OMAP2)
|
||||
|
||||
#define OMAP2_STI_BASE 0x48068000
|
||||
#define OMAP2_STI_CHANNEL_BASE 0x54000000
|
||||
#define OMAP2_STI_IRQ 4
|
||||
|
||||
|
@ -124,6 +83,25 @@ static struct resource sti_resources[] = {
|
|||
.flags = IORESOURCE_IRQ,
|
||||
}
|
||||
};
|
||||
#elif defined(CONFIG_ARCH_OMAP3)
|
||||
|
||||
#define OMAP3_SDTI_BASE 0x54500000
|
||||
#define OMAP3_SDTI_CHANNEL_BASE 0x54600000
|
||||
|
||||
static struct resource sti_resources[] = {
|
||||
{
|
||||
.start = OMAP3_SDTI_BASE,
|
||||
.end = OMAP3_SDTI_BASE + 0xFFF,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
{
|
||||
.start = OMAP3_SDTI_CHANNEL_BASE,
|
||||
.end = OMAP3_SDTI_CHANNEL_BASE + SZ_1M - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
}
|
||||
};
|
||||
|
||||
#endif
|
||||
|
||||
static struct platform_device sti_device = {
|
||||
.name = "sti",
|
||||
|
@ -140,12 +118,14 @@ static inline void omap_init_sti(void)
|
|||
static inline void omap_init_sti(void) {}
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_SPI_OMAP24XX)
|
||||
#if defined(CONFIG_SPI_OMAP24XX) || defined(CONFIG_SPI_OMAP24XX_MODULE)
|
||||
|
||||
#include <mach/mcspi.h>
|
||||
|
||||
#define OMAP2_MCSPI1_BASE 0x48098000
|
||||
#define OMAP2_MCSPI2_BASE 0x4809a000
|
||||
#define OMAP2_MCSPI3_BASE 0x480b8000
|
||||
#define OMAP2_MCSPI4_BASE 0x480ba000
|
||||
|
||||
static struct omap2_mcspi_platform_config omap2_mcspi1_config = {
|
||||
.num_cs = 4,
|
||||
|
@ -159,7 +139,7 @@ static struct resource omap2_mcspi1_resources[] = {
|
|||
},
|
||||
};
|
||||
|
||||
struct platform_device omap2_mcspi1 = {
|
||||
static struct platform_device omap2_mcspi1 = {
|
||||
.name = "omap2_mcspi",
|
||||
.id = 1,
|
||||
.num_resources = ARRAY_SIZE(omap2_mcspi1_resources),
|
||||
|
@ -181,7 +161,7 @@ static struct resource omap2_mcspi2_resources[] = {
|
|||
},
|
||||
};
|
||||
|
||||
struct platform_device omap2_mcspi2 = {
|
||||
static struct platform_device omap2_mcspi2 = {
|
||||
.name = "omap2_mcspi",
|
||||
.id = 2,
|
||||
.num_resources = ARRAY_SIZE(omap2_mcspi2_resources),
|
||||
|
@ -191,16 +171,162 @@ struct platform_device omap2_mcspi2 = {
|
|||
},
|
||||
};
|
||||
|
||||
#if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3)
|
||||
static struct omap2_mcspi_platform_config omap2_mcspi3_config = {
|
||||
.num_cs = 2,
|
||||
};
|
||||
|
||||
static struct resource omap2_mcspi3_resources[] = {
|
||||
{
|
||||
.start = OMAP2_MCSPI3_BASE,
|
||||
.end = OMAP2_MCSPI3_BASE + 0xff,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device omap2_mcspi3 = {
|
||||
.name = "omap2_mcspi",
|
||||
.id = 3,
|
||||
.num_resources = ARRAY_SIZE(omap2_mcspi3_resources),
|
||||
.resource = omap2_mcspi3_resources,
|
||||
.dev = {
|
||||
.platform_data = &omap2_mcspi3_config,
|
||||
},
|
||||
};
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_ARCH_OMAP3
|
||||
static struct omap2_mcspi_platform_config omap2_mcspi4_config = {
|
||||
.num_cs = 1,
|
||||
};
|
||||
|
||||
static struct resource omap2_mcspi4_resources[] = {
|
||||
{
|
||||
.start = OMAP2_MCSPI4_BASE,
|
||||
.end = OMAP2_MCSPI4_BASE + 0xff,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device omap2_mcspi4 = {
|
||||
.name = "omap2_mcspi",
|
||||
.id = 4,
|
||||
.num_resources = ARRAY_SIZE(omap2_mcspi4_resources),
|
||||
.resource = omap2_mcspi4_resources,
|
||||
.dev = {
|
||||
.platform_data = &omap2_mcspi4_config,
|
||||
},
|
||||
};
|
||||
#endif
|
||||
|
||||
static void omap_init_mcspi(void)
|
||||
{
|
||||
platform_device_register(&omap2_mcspi1);
|
||||
platform_device_register(&omap2_mcspi2);
|
||||
#if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3)
|
||||
platform_device_register(&omap2_mcspi3);
|
||||
#endif
|
||||
#ifdef CONFIG_ARCH_OMAP3
|
||||
platform_device_register(&omap2_mcspi4);
|
||||
#endif
|
||||
}
|
||||
|
||||
#else
|
||||
static inline void omap_init_mcspi(void) {}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SND_OMAP24XX_EAC
|
||||
|
||||
#define OMAP2_EAC_BASE 0x48090000
|
||||
|
||||
static struct resource omap2_eac_resources[] = {
|
||||
{
|
||||
.start = OMAP2_EAC_BASE,
|
||||
.end = OMAP2_EAC_BASE + 0x109,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device omap2_eac_device = {
|
||||
.name = "omap24xx-eac",
|
||||
.id = -1,
|
||||
.num_resources = ARRAY_SIZE(omap2_eac_resources),
|
||||
.resource = omap2_eac_resources,
|
||||
.dev = {
|
||||
.platform_data = NULL,
|
||||
},
|
||||
};
|
||||
|
||||
void omap_init_eac(struct eac_platform_data *pdata)
|
||||
{
|
||||
omap2_eac_device.dev.platform_data = pdata;
|
||||
platform_device_register(&omap2_eac_device);
|
||||
}
|
||||
|
||||
#else
|
||||
void omap_init_eac(struct eac_platform_data *pdata) {}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_OMAP_SHA1_MD5
|
||||
static struct resource sha1_md5_resources[] = {
|
||||
{
|
||||
.start = OMAP24XX_SEC_SHA1MD5_BASE,
|
||||
.end = OMAP24XX_SEC_SHA1MD5_BASE + 0x64,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
{
|
||||
.start = INT_24XX_SHA1MD5,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
}
|
||||
};
|
||||
|
||||
static struct platform_device sha1_md5_device = {
|
||||
.name = "OMAP SHA1/MD5",
|
||||
.id = -1,
|
||||
.num_resources = ARRAY_SIZE(sha1_md5_resources),
|
||||
.resource = sha1_md5_resources,
|
||||
};
|
||||
|
||||
static void omap_init_sha1_md5(void)
|
||||
{
|
||||
platform_device_register(&sha1_md5_device);
|
||||
}
|
||||
#else
|
||||
static inline void omap_init_sha1_md5(void) { }
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_HDQ_MASTER_OMAP) || defined(CONFIG_HDQ_MASTER_OMAP_MODULE)
|
||||
#if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3430)
|
||||
#define OMAP_HDQ_BASE 0x480B2000
|
||||
#endif
|
||||
static struct resource omap_hdq_resources[] = {
|
||||
{
|
||||
.start = OMAP_HDQ_BASE,
|
||||
.end = OMAP_HDQ_BASE + 0x1C,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
{
|
||||
.start = INT_24XX_HDQ_IRQ,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
static struct platform_device omap_hdq_dev = {
|
||||
.name = "omap_hdq",
|
||||
.id = 0,
|
||||
.dev = {
|
||||
.platform_data = NULL,
|
||||
},
|
||||
.num_resources = ARRAY_SIZE(omap_hdq_resources),
|
||||
.resource = omap_hdq_resources,
|
||||
};
|
||||
static inline void omap_hdq_init(void)
|
||||
{
|
||||
(void) platform_device_register(&omap_hdq_dev);
|
||||
}
|
||||
#else
|
||||
static inline void omap_hdq_init(void) {}
|
||||
#endif
|
||||
|
||||
/*-------------------------------------------------------------------------*/
|
||||
|
||||
static int __init omap2_init_devices(void)
|
||||
|
@ -208,10 +334,11 @@ static int __init omap2_init_devices(void)
|
|||
/* please keep these calls, and their implementations above,
|
||||
* in alphabetical order so they're easier to sort through.
|
||||
*/
|
||||
omap_init_i2c();
|
||||
omap_init_mbox();
|
||||
omap_init_mcspi();
|
||||
omap_hdq_init();
|
||||
omap_init_sti();
|
||||
omap_init_sha1_md5();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
|
@ -9,6 +9,8 @@
|
|||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
#undef DEBUG
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/err.h>
|
||||
|
@ -16,20 +18,14 @@
|
|||
#include <linux/ioport.h>
|
||||
#include <linux/spinlock.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/module.h>
|
||||
|
||||
#include <asm/mach-types.h>
|
||||
#include <mach/gpmc.h>
|
||||
|
||||
#undef DEBUG
|
||||
|
||||
#ifdef CONFIG_ARCH_OMAP2420
|
||||
#define GPMC_BASE 0x6800a000
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_ARCH_OMAP2430
|
||||
#define GPMC_BASE 0x6E000000
|
||||
#endif
|
||||
#include <mach/sdrc.h>
|
||||
|
||||
/* GPMC register offsets */
|
||||
#define GPMC_REVISION 0x00
|
||||
#define GPMC_SYSCONFIG 0x10
|
||||
#define GPMC_SYSSTATUS 0x14
|
||||
|
@ -51,7 +47,6 @@
|
|||
#define GPMC_CS0 0x60
|
||||
#define GPMC_CS_SIZE 0x30
|
||||
|
||||
#define GPMC_CS_NUM 8
|
||||
#define GPMC_MEM_START 0x00000000
|
||||
#define GPMC_MEM_END 0x3FFFFFFF
|
||||
#define BOOT_ROM_SPACE 0x100000 /* 1MB */
|
||||
|
@ -64,12 +59,9 @@ static struct resource gpmc_cs_mem[GPMC_CS_NUM];
|
|||
static DEFINE_SPINLOCK(gpmc_mem_lock);
|
||||
static unsigned gpmc_cs_map;
|
||||
|
||||
static void __iomem *gpmc_base =
|
||||
(void __iomem *) IO_ADDRESS(GPMC_BASE);
|
||||
static void __iomem *gpmc_cs_base =
|
||||
(void __iomem *) IO_ADDRESS(GPMC_BASE) + GPMC_CS0;
|
||||
static void __iomem *gpmc_base;
|
||||
|
||||
static struct clk *gpmc_fck;
|
||||
static struct clk *gpmc_l3_clk;
|
||||
|
||||
static void gpmc_write_reg(int idx, u32 val)
|
||||
{
|
||||
|
@ -85,19 +77,32 @@ void gpmc_cs_write_reg(int cs, int idx, u32 val)
|
|||
{
|
||||
void __iomem *reg_addr;
|
||||
|
||||
reg_addr = gpmc_cs_base + (cs * GPMC_CS_SIZE) + idx;
|
||||
reg_addr = gpmc_base + GPMC_CS0 + (cs * GPMC_CS_SIZE) + idx;
|
||||
__raw_writel(val, reg_addr);
|
||||
}
|
||||
|
||||
u32 gpmc_cs_read_reg(int cs, int idx)
|
||||
{
|
||||
return __raw_readl(gpmc_cs_base + (cs * GPMC_CS_SIZE) + idx);
|
||||
void __iomem *reg_addr;
|
||||
|
||||
reg_addr = gpmc_base + GPMC_CS0 + (cs * GPMC_CS_SIZE) + idx;
|
||||
return __raw_readl(reg_addr);
|
||||
}
|
||||
|
||||
/* TODO: Add support for gpmc_fck to clock framework and use it */
|
||||
unsigned long gpmc_get_fclk_period(void)
|
||||
{
|
||||
/* In picoseconds */
|
||||
return 1000000000 / ((clk_get_rate(gpmc_fck)) / 1000);
|
||||
unsigned long rate = clk_get_rate(gpmc_l3_clk);
|
||||
|
||||
if (rate == 0) {
|
||||
printk(KERN_WARNING "gpmc_l3_clk not enabled\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
rate /= 1000;
|
||||
rate = 1000000000 / rate; /* In picoseconds */
|
||||
|
||||
return rate;
|
||||
}
|
||||
|
||||
unsigned int gpmc_ns_to_ticks(unsigned int time_ns)
|
||||
|
@ -110,6 +115,11 @@ unsigned int gpmc_ns_to_ticks(unsigned int time_ns)
|
|||
return (time_ns * 1000 + tick_ps - 1) / tick_ps;
|
||||
}
|
||||
|
||||
unsigned int gpmc_ticks_to_ns(unsigned int ticks)
|
||||
{
|
||||
return ticks * gpmc_get_fclk_period() / 1000;
|
||||
}
|
||||
|
||||
unsigned int gpmc_round_ns_to_ticks(unsigned int time_ns)
|
||||
{
|
||||
unsigned long ticks = gpmc_ns_to_ticks(time_ns);
|
||||
|
@ -210,6 +220,11 @@ int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t)
|
|||
|
||||
GPMC_SET_ONE(GPMC_CS_CONFIG5, 24, 27, page_burst_access);
|
||||
|
||||
if (cpu_is_omap34xx()) {
|
||||
GPMC_SET_ONE(GPMC_CS_CONFIG6, 16, 19, wr_data_mux_bus);
|
||||
GPMC_SET_ONE(GPMC_CS_CONFIG6, 24, 28, wr_access);
|
||||
}
|
||||
|
||||
/* caller is expected to have initialized CONFIG1 to cover
|
||||
* at least sync vs async
|
||||
*/
|
||||
|
@ -350,6 +365,7 @@ out:
|
|||
spin_unlock(&gpmc_mem_lock);
|
||||
return r;
|
||||
}
|
||||
EXPORT_SYMBOL(gpmc_cs_request);
|
||||
|
||||
void gpmc_cs_free(int cs)
|
||||
{
|
||||
|
@ -365,8 +381,9 @@ void gpmc_cs_free(int cs)
|
|||
gpmc_cs_set_reserved(cs, 0);
|
||||
spin_unlock(&gpmc_mem_lock);
|
||||
}
|
||||
EXPORT_SYMBOL(gpmc_cs_free);
|
||||
|
||||
void __init gpmc_mem_init(void)
|
||||
static void __init gpmc_mem_init(void)
|
||||
{
|
||||
int cs;
|
||||
unsigned long boot_rom_space = 0;
|
||||
|
@ -396,12 +413,33 @@ void __init gpmc_mem_init(void)
|
|||
void __init gpmc_init(void)
|
||||
{
|
||||
u32 l;
|
||||
char *ck;
|
||||
|
||||
gpmc_fck = clk_get(NULL, "gpmc_fck"); /* Always on ENABLE_ON_INIT */
|
||||
if (IS_ERR(gpmc_fck))
|
||||
WARN_ON(1);
|
||||
else
|
||||
clk_enable(gpmc_fck);
|
||||
if (cpu_is_omap24xx()) {
|
||||
ck = "core_l3_ck";
|
||||
if (cpu_is_omap2420())
|
||||
l = OMAP2420_GPMC_BASE;
|
||||
else
|
||||
l = OMAP34XX_GPMC_BASE;
|
||||
} else if (cpu_is_omap34xx()) {
|
||||
ck = "gpmc_fck";
|
||||
l = OMAP34XX_GPMC_BASE;
|
||||
}
|
||||
|
||||
gpmc_l3_clk = clk_get(NULL, ck);
|
||||
if (IS_ERR(gpmc_l3_clk)) {
|
||||
printk(KERN_ERR "Could not get GPMC clock %s\n", ck);
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
gpmc_base = ioremap(l, SZ_4K);
|
||||
if (!gpmc_base) {
|
||||
clk_put(gpmc_l3_clk);
|
||||
printk(KERN_ERR "Could not get GPMC register memory\n");
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
BUG_ON(IS_ERR(gpmc_l3_clk));
|
||||
|
||||
l = gpmc_read_reg(GPMC_REVISION);
|
||||
printk(KERN_INFO "GPMC revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f);
|
||||
|
|
|
@ -18,24 +18,15 @@
|
|||
|
||||
#include <asm/cputype.h>
|
||||
|
||||
#include <mach/common.h>
|
||||
#include <mach/control.h>
|
||||
#include <mach/cpu.h>
|
||||
|
||||
#if defined(CONFIG_ARCH_OMAP2420)
|
||||
#define TAP_BASE io_p2v(0x48014000)
|
||||
#elif defined(CONFIG_ARCH_OMAP2430)
|
||||
#define TAP_BASE io_p2v(0x4900A000)
|
||||
#elif defined(CONFIG_ARCH_OMAP34XX)
|
||||
#define TAP_BASE io_p2v(0x4830A000)
|
||||
#endif
|
||||
static u32 class;
|
||||
static void __iomem *tap_base;
|
||||
static u16 tap_prod_id;
|
||||
|
||||
#define OMAP_TAP_IDCODE 0x0204
|
||||
#if defined(CONFIG_ARCH_OMAP34XX)
|
||||
#define OMAP_TAP_PROD_ID 0x0210
|
||||
#else
|
||||
#define OMAP_TAP_PROD_ID 0x0208
|
||||
#endif
|
||||
|
||||
#define OMAP_TAP_DIE_ID_0 0x0218
|
||||
#define OMAP_TAP_DIE_ID_1 0x021C
|
||||
#define OMAP_TAP_DIE_ID_2 0x0220
|
||||
|
@ -94,18 +85,24 @@ static u32 __init read_tap_reg(int reg)
|
|||
* it means its Cortex r0p0 which is 3430 ES1
|
||||
*/
|
||||
if ((((cpuid >> 4) & 0xFFF) == 0xC08) && ((cpuid & 0xF) == 0x0)) {
|
||||
|
||||
if (reg == tap_prod_id) {
|
||||
regval = 0x000F00F0;
|
||||
goto out;
|
||||
}
|
||||
|
||||
switch (reg) {
|
||||
case OMAP_TAP_IDCODE : regval = 0x0B7AE02F; break;
|
||||
/* Making DevType as 0xF in ES1 to differ from ES2 */
|
||||
case OMAP_TAP_PROD_ID : regval = 0x000F00F0; break;
|
||||
case OMAP_TAP_DIE_ID_0: regval = 0x01000000; break;
|
||||
case OMAP_TAP_DIE_ID_1: regval = 0x1012d687; break;
|
||||
case OMAP_TAP_DIE_ID_2: regval = 0x00000000; break;
|
||||
case OMAP_TAP_DIE_ID_3: regval = 0x2d2c0000; break;
|
||||
}
|
||||
} else
|
||||
regval = __raw_readl(TAP_BASE + reg);
|
||||
regval = __raw_readl(tap_base + reg);
|
||||
|
||||
out:
|
||||
return regval;
|
||||
|
||||
}
|
||||
|
@ -204,7 +201,7 @@ void __init omap2_check_revision(void)
|
|||
u8 rev;
|
||||
|
||||
idcode = read_tap_reg(OMAP_TAP_IDCODE);
|
||||
prod_id = read_tap_reg(OMAP_TAP_PROD_ID);
|
||||
prod_id = read_tap_reg(tap_prod_id);
|
||||
hawkeye = (idcode >> 12) & 0xffff;
|
||||
rev = (idcode >> 28) & 0x0f;
|
||||
dev_type = (prod_id >> 16) & 0x0f;
|
||||
|
@ -269,3 +266,13 @@ void __init omap2_check_revision(void)
|
|||
|
||||
}
|
||||
|
||||
void __init omap2_set_globals_tap(struct omap_globals *omap2_globals)
|
||||
{
|
||||
class = omap2_globals->class;
|
||||
tap_base = omap2_globals->tap;
|
||||
|
||||
if (class == 0x3430)
|
||||
tap_prod_id = 0x0210;
|
||||
else
|
||||
tap_prod_id = 0x0208;
|
||||
}
|
||||
|
|
|
@ -4,8 +4,11 @@
|
|||
* OMAP2 I/O mapping code
|
||||
*
|
||||
* Copyright (C) 2005 Nokia Corporation
|
||||
* Author: Juha Yrjölä <juha.yrjola@nokia.com>
|
||||
* Updated map desc to add 2430 support : <x0khasim@ti.com>
|
||||
* Copyright (C) 2007 Texas Instruments
|
||||
*
|
||||
* Author:
|
||||
* Juha Yrjola <juha.yrjola@nokia.com>
|
||||
* Syed Khasim <x0khasim@ti.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
|
@ -23,19 +26,26 @@
|
|||
|
||||
#include <mach/mux.h>
|
||||
#include <mach/omapfb.h>
|
||||
#include <mach/sram.h>
|
||||
|
||||
extern void omap_sram_init(void);
|
||||
extern int omap2_clk_init(void);
|
||||
extern void omap2_check_revision(void);
|
||||
extern void omap2_init_memory(void);
|
||||
extern void gpmc_init(void);
|
||||
extern void omapfb_reserve_sdram(void);
|
||||
#include "memory.h"
|
||||
|
||||
#include "clock.h"
|
||||
|
||||
#include <mach/powerdomain.h>
|
||||
|
||||
#include "powerdomains.h"
|
||||
|
||||
#include <mach/clockdomain.h>
|
||||
#include "clockdomains.h"
|
||||
|
||||
/*
|
||||
* The machine specific code may provide the extra mapping besides the
|
||||
* default mapping provided here.
|
||||
*/
|
||||
static struct map_desc omap2_io_desc[] __initdata = {
|
||||
|
||||
#ifdef CONFIG_ARCH_OMAP24XX
|
||||
static struct map_desc omap24xx_io_desc[] __initdata = {
|
||||
{
|
||||
.virtual = L3_24XX_VIRT,
|
||||
.pfn = __phys_to_pfn(L3_24XX_PHYS),
|
||||
|
@ -43,25 +53,15 @@ static struct map_desc omap2_io_desc[] __initdata = {
|
|||
.type = MT_DEVICE
|
||||
},
|
||||
{
|
||||
.virtual = L4_24XX_VIRT,
|
||||
.pfn = __phys_to_pfn(L4_24XX_PHYS),
|
||||
.length = L4_24XX_SIZE,
|
||||
.type = MT_DEVICE
|
||||
},
|
||||
#ifdef CONFIG_ARCH_OMAP2430
|
||||
{
|
||||
.virtual = L4_WK_243X_VIRT,
|
||||
.pfn = __phys_to_pfn(L4_WK_243X_PHYS),
|
||||
.length = L4_WK_243X_SIZE,
|
||||
.virtual = L4_24XX_VIRT,
|
||||
.pfn = __phys_to_pfn(L4_24XX_PHYS),
|
||||
.length = L4_24XX_SIZE,
|
||||
.type = MT_DEVICE
|
||||
},
|
||||
{
|
||||
.virtual = OMAP243X_GPMC_VIRT,
|
||||
.pfn = __phys_to_pfn(OMAP243X_GPMC_PHYS),
|
||||
.length = OMAP243X_GPMC_SIZE,
|
||||
.type = MT_DEVICE
|
||||
},
|
||||
#endif
|
||||
};
|
||||
|
||||
#ifdef CONFIG_ARCH_OMAP2420
|
||||
static struct map_desc omap242x_io_desc[] __initdata = {
|
||||
{
|
||||
.virtual = DSP_MEM_24XX_VIRT,
|
||||
.pfn = __phys_to_pfn(DSP_MEM_24XX_PHYS),
|
||||
|
@ -79,12 +79,109 @@ static struct map_desc omap2_io_desc[] __initdata = {
|
|||
.pfn = __phys_to_pfn(DSP_MMU_24XX_PHYS),
|
||||
.length = DSP_MMU_24XX_SIZE,
|
||||
.type = MT_DEVICE
|
||||
}
|
||||
},
|
||||
};
|
||||
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_ARCH_OMAP2430
|
||||
static struct map_desc omap243x_io_desc[] __initdata = {
|
||||
{
|
||||
.virtual = L4_WK_243X_VIRT,
|
||||
.pfn = __phys_to_pfn(L4_WK_243X_PHYS),
|
||||
.length = L4_WK_243X_SIZE,
|
||||
.type = MT_DEVICE
|
||||
},
|
||||
{
|
||||
.virtual = OMAP243X_GPMC_VIRT,
|
||||
.pfn = __phys_to_pfn(OMAP243X_GPMC_PHYS),
|
||||
.length = OMAP243X_GPMC_SIZE,
|
||||
.type = MT_DEVICE
|
||||
},
|
||||
{
|
||||
.virtual = OMAP243X_SDRC_VIRT,
|
||||
.pfn = __phys_to_pfn(OMAP243X_SDRC_PHYS),
|
||||
.length = OMAP243X_SDRC_SIZE,
|
||||
.type = MT_DEVICE
|
||||
},
|
||||
{
|
||||
.virtual = OMAP243X_SMS_VIRT,
|
||||
.pfn = __phys_to_pfn(OMAP243X_SMS_PHYS),
|
||||
.length = OMAP243X_SMS_SIZE,
|
||||
.type = MT_DEVICE
|
||||
},
|
||||
};
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_ARCH_OMAP34XX
|
||||
static struct map_desc omap34xx_io_desc[] __initdata = {
|
||||
{
|
||||
.virtual = L3_34XX_VIRT,
|
||||
.pfn = __phys_to_pfn(L3_34XX_PHYS),
|
||||
.length = L3_34XX_SIZE,
|
||||
.type = MT_DEVICE
|
||||
},
|
||||
{
|
||||
.virtual = L4_34XX_VIRT,
|
||||
.pfn = __phys_to_pfn(L4_34XX_PHYS),
|
||||
.length = L4_34XX_SIZE,
|
||||
.type = MT_DEVICE
|
||||
},
|
||||
{
|
||||
.virtual = L4_WK_34XX_VIRT,
|
||||
.pfn = __phys_to_pfn(L4_WK_34XX_PHYS),
|
||||
.length = L4_WK_34XX_SIZE,
|
||||
.type = MT_DEVICE
|
||||
},
|
||||
{
|
||||
.virtual = OMAP34XX_GPMC_VIRT,
|
||||
.pfn = __phys_to_pfn(OMAP34XX_GPMC_PHYS),
|
||||
.length = OMAP34XX_GPMC_SIZE,
|
||||
.type = MT_DEVICE
|
||||
},
|
||||
{
|
||||
.virtual = OMAP343X_SMS_VIRT,
|
||||
.pfn = __phys_to_pfn(OMAP343X_SMS_PHYS),
|
||||
.length = OMAP343X_SMS_SIZE,
|
||||
.type = MT_DEVICE
|
||||
},
|
||||
{
|
||||
.virtual = OMAP343X_SDRC_VIRT,
|
||||
.pfn = __phys_to_pfn(OMAP343X_SDRC_PHYS),
|
||||
.length = OMAP343X_SDRC_SIZE,
|
||||
.type = MT_DEVICE
|
||||
},
|
||||
{
|
||||
.virtual = L4_PER_34XX_VIRT,
|
||||
.pfn = __phys_to_pfn(L4_PER_34XX_PHYS),
|
||||
.length = L4_PER_34XX_SIZE,
|
||||
.type = MT_DEVICE
|
||||
},
|
||||
{
|
||||
.virtual = L4_EMU_34XX_VIRT,
|
||||
.pfn = __phys_to_pfn(L4_EMU_34XX_PHYS),
|
||||
.length = L4_EMU_34XX_SIZE,
|
||||
.type = MT_DEVICE
|
||||
},
|
||||
};
|
||||
#endif
|
||||
|
||||
void __init omap2_map_common_io(void)
|
||||
{
|
||||
iotable_init(omap2_io_desc, ARRAY_SIZE(omap2_io_desc));
|
||||
#if defined(CONFIG_ARCH_OMAP2420)
|
||||
iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
|
||||
iotable_init(omap242x_io_desc, ARRAY_SIZE(omap242x_io_desc));
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_ARCH_OMAP2430)
|
||||
iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
|
||||
iotable_init(omap243x_io_desc, ARRAY_SIZE(omap243x_io_desc));
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_ARCH_OMAP34XX)
|
||||
iotable_init(omap34xx_io_desc, ARRAY_SIZE(omap34xx_io_desc));
|
||||
#endif
|
||||
|
||||
/* Normally devicemaps_init() would flush caches and tlb after
|
||||
* mdesc->map_io(), but we must also do it here because of the CPU
|
||||
|
@ -101,12 +198,9 @@ void __init omap2_map_common_io(void)
|
|||
void __init omap2_init_common_hw(void)
|
||||
{
|
||||
omap2_mux_init();
|
||||
pwrdm_init(powerdomains_omap);
|
||||
clkdm_init(clockdomains_omap, clkdm_pwrdm_autodeps);
|
||||
omap2_clk_init();
|
||||
/*
|
||||
* Need to Fix this for 2430
|
||||
*/
|
||||
#ifndef CONFIG_ARCH_OMAP2430
|
||||
omap2_init_memory();
|
||||
#endif
|
||||
gpmc_init();
|
||||
}
|
||||
|
|
|
@ -16,14 +16,20 @@
|
|||
#include <linux/io.h>
|
||||
#include <mach/hardware.h>
|
||||
#include <asm/mach/irq.h>
|
||||
#include <asm/irq.h>
|
||||
|
||||
#define INTC_REVISION 0x0000
|
||||
#define INTC_SYSCONFIG 0x0010
|
||||
#define INTC_SYSSTATUS 0x0014
|
||||
#define INTC_CONTROL 0x0048
|
||||
#define INTC_MIR_CLEAR0 0x0088
|
||||
#define INTC_MIR_SET0 0x008c
|
||||
|
||||
/* selected INTC register offsets */
|
||||
|
||||
#define INTC_REVISION 0x0000
|
||||
#define INTC_SYSCONFIG 0x0010
|
||||
#define INTC_SYSSTATUS 0x0014
|
||||
#define INTC_CONTROL 0x0048
|
||||
#define INTC_MIR_CLEAR0 0x0088
|
||||
#define INTC_MIR_SET0 0x008c
|
||||
#define INTC_PENDING_IRQ0 0x0098
|
||||
|
||||
/* Number of IRQ state bits in each MIR register */
|
||||
#define IRQ_BITS_PER_REG 32
|
||||
|
||||
/*
|
||||
* OMAP2 has a number of different interrupt controllers, each interrupt
|
||||
|
@ -32,48 +38,50 @@
|
|||
* for each bank.. when in doubt, consult the TRM.
|
||||
*/
|
||||
static struct omap_irq_bank {
|
||||
unsigned long base_reg;
|
||||
void __iomem *base_reg;
|
||||
unsigned int nr_irqs;
|
||||
} __attribute__ ((aligned(4))) irq_banks[] = {
|
||||
{
|
||||
/* MPU INTC */
|
||||
.base_reg = IO_ADDRESS(OMAP24XX_IC_BASE),
|
||||
.base_reg = 0,
|
||||
.nr_irqs = 96,
|
||||
}, {
|
||||
/* XXX: DSP INTC */
|
||||
}
|
||||
},
|
||||
};
|
||||
|
||||
/* INTC bank register get/set */
|
||||
|
||||
static void intc_bank_write_reg(u32 val, struct omap_irq_bank *bank, u16 reg)
|
||||
{
|
||||
__raw_writel(val, bank->base_reg + reg);
|
||||
}
|
||||
|
||||
static u32 intc_bank_read_reg(struct omap_irq_bank *bank, u16 reg)
|
||||
{
|
||||
return __raw_readl(bank->base_reg + reg);
|
||||
}
|
||||
|
||||
/* XXX: FIQ and additional INTC support (only MPU at the moment) */
|
||||
static void omap_ack_irq(unsigned int irq)
|
||||
{
|
||||
__raw_writel(0x1, irq_banks[0].base_reg + INTC_CONTROL);
|
||||
intc_bank_write_reg(0x1, &irq_banks[0], INTC_CONTROL);
|
||||
}
|
||||
|
||||
static void omap_mask_irq(unsigned int irq)
|
||||
{
|
||||
int offset = (irq >> 5) << 5;
|
||||
int offset = irq & (~(IRQ_BITS_PER_REG - 1));
|
||||
|
||||
if (irq >= 64) {
|
||||
irq %= 64;
|
||||
} else if (irq >= 32) {
|
||||
irq %= 32;
|
||||
}
|
||||
irq &= (IRQ_BITS_PER_REG - 1);
|
||||
|
||||
__raw_writel(1 << irq, irq_banks[0].base_reg + INTC_MIR_SET0 + offset);
|
||||
intc_bank_write_reg(1 << irq, &irq_banks[0], INTC_MIR_SET0 + offset);
|
||||
}
|
||||
|
||||
static void omap_unmask_irq(unsigned int irq)
|
||||
{
|
||||
int offset = (irq >> 5) << 5;
|
||||
int offset = irq & (~(IRQ_BITS_PER_REG - 1));
|
||||
|
||||
if (irq >= 64) {
|
||||
irq %= 64;
|
||||
} else if (irq >= 32) {
|
||||
irq %= 32;
|
||||
}
|
||||
irq &= (IRQ_BITS_PER_REG - 1);
|
||||
|
||||
__raw_writel(1 << irq, irq_banks[0].base_reg + INTC_MIR_CLEAR0 + offset);
|
||||
intc_bank_write_reg(1 << irq, &irq_banks[0], INTC_MIR_CLEAR0 + offset);
|
||||
}
|
||||
|
||||
static void omap_mask_ack_irq(unsigned int irq)
|
||||
|
@ -93,20 +101,20 @@ static void __init omap_irq_bank_init_one(struct omap_irq_bank *bank)
|
|||
{
|
||||
unsigned long tmp;
|
||||
|
||||
tmp = __raw_readl(bank->base_reg + INTC_REVISION) & 0xff;
|
||||
printk(KERN_INFO "IRQ: Found an INTC at 0x%08lx "
|
||||
tmp = intc_bank_read_reg(bank, INTC_REVISION) & 0xff;
|
||||
printk(KERN_INFO "IRQ: Found an INTC at 0x%p "
|
||||
"(revision %ld.%ld) with %d interrupts\n",
|
||||
bank->base_reg, tmp >> 4, tmp & 0xf, bank->nr_irqs);
|
||||
|
||||
tmp = __raw_readl(bank->base_reg + INTC_SYSCONFIG);
|
||||
tmp = intc_bank_read_reg(bank, INTC_SYSCONFIG);
|
||||
tmp |= 1 << 1; /* soft reset */
|
||||
__raw_writel(tmp, bank->base_reg + INTC_SYSCONFIG);
|
||||
intc_bank_write_reg(tmp, bank, INTC_SYSCONFIG);
|
||||
|
||||
while (!(__raw_readl(bank->base_reg + INTC_SYSSTATUS) & 0x1))
|
||||
while (!(intc_bank_read_reg(bank, INTC_SYSSTATUS) & 0x1))
|
||||
/* Wait for reset to complete */;
|
||||
|
||||
/* Enable autoidle */
|
||||
__raw_writel(1 << 0, bank->base_reg + INTC_SYSCONFIG);
|
||||
intc_bank_write_reg(1 << 0, bank, INTC_SYSCONFIG);
|
||||
}
|
||||
|
||||
void __init omap_init_irq(void)
|
||||
|
@ -118,9 +126,10 @@ void __init omap_init_irq(void)
|
|||
for (i = 0; i < ARRAY_SIZE(irq_banks); i++) {
|
||||
struct omap_irq_bank *bank = irq_banks + i;
|
||||
|
||||
/* XXX */
|
||||
if (!bank->base_reg)
|
||||
continue;
|
||||
if (cpu_is_omap24xx())
|
||||
bank->base_reg = OMAP2_IO_ADDRESS(OMAP24XX_IC_BASE);
|
||||
else if (cpu_is_omap34xx())
|
||||
bank->base_reg = OMAP2_IO_ADDRESS(OMAP34XX_IC_BASE);
|
||||
|
||||
omap_irq_bank_init_one(bank);
|
||||
|
||||
|
|
|
@ -89,6 +89,30 @@ static struct mcbsp_internal_clk omap_mcbsp_clks[] = {
|
|||
.disable = omap_mcbsp_clk_disable,
|
||||
},
|
||||
},
|
||||
{
|
||||
.clk = {
|
||||
.name = "mcbsp_clk",
|
||||
.id = 3,
|
||||
.enable = omap_mcbsp_clk_enable,
|
||||
.disable = omap_mcbsp_clk_disable,
|
||||
},
|
||||
},
|
||||
{
|
||||
.clk = {
|
||||
.name = "mcbsp_clk",
|
||||
.id = 4,
|
||||
.enable = omap_mcbsp_clk_enable,
|
||||
.disable = omap_mcbsp_clk_disable,
|
||||
},
|
||||
},
|
||||
{
|
||||
.clk = {
|
||||
.name = "mcbsp_clk",
|
||||
.id = 5,
|
||||
.enable = omap_mcbsp_clk_enable,
|
||||
.disable = omap_mcbsp_clk_disable,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
#define omap_mcbsp_clks_size ARRAY_SIZE(omap_mcbsp_clks)
|
||||
|
@ -117,25 +141,14 @@ static void omap2_mcbsp_request(unsigned int id)
|
|||
omap2_mcbsp2_mux_setup();
|
||||
}
|
||||
|
||||
static int omap2_mcbsp_check(unsigned int id)
|
||||
{
|
||||
if (id > OMAP_MAX_MCBSP_COUNT - 1) {
|
||||
printk(KERN_ERR "OMAP-McBSP: McBSP%d doesn't exist\n", id + 1);
|
||||
return -ENODEV;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct omap_mcbsp_ops omap2_mcbsp_ops = {
|
||||
.request = omap2_mcbsp_request,
|
||||
.check = omap2_mcbsp_check,
|
||||
};
|
||||
|
||||
#ifdef CONFIG_ARCH_OMAP24XX
|
||||
static struct omap_mcbsp_platform_data omap24xx_mcbsp_pdata[] = {
|
||||
#ifdef CONFIG_ARCH_OMAP2420
|
||||
static struct omap_mcbsp_platform_data omap2420_mcbsp_pdata[] = {
|
||||
{
|
||||
.phys_base = OMAP24XX_MCBSP1_BASE,
|
||||
.virt_base = IO_ADDRESS(OMAP24XX_MCBSP1_BASE),
|
||||
.dma_rx_sync = OMAP24XX_DMA_MCBSP1_RX,
|
||||
.dma_tx_sync = OMAP24XX_DMA_MCBSP1_TX,
|
||||
.rx_irq = INT_24XX_MCBSP1_IRQ_RX,
|
||||
|
@ -145,7 +158,6 @@ static struct omap_mcbsp_platform_data omap24xx_mcbsp_pdata[] = {
|
|||
},
|
||||
{
|
||||
.phys_base = OMAP24XX_MCBSP2_BASE,
|
||||
.virt_base = IO_ADDRESS(OMAP24XX_MCBSP2_BASE),
|
||||
.dma_rx_sync = OMAP24XX_DMA_MCBSP2_RX,
|
||||
.dma_tx_sync = OMAP24XX_DMA_MCBSP2_TX,
|
||||
.rx_irq = INT_24XX_MCBSP2_IRQ_RX,
|
||||
|
@ -154,17 +166,70 @@ static struct omap_mcbsp_platform_data omap24xx_mcbsp_pdata[] = {
|
|||
.clk_name = "mcbsp_clk",
|
||||
},
|
||||
};
|
||||
#define OMAP24XX_MCBSP_PDATA_SZ ARRAY_SIZE(omap24xx_mcbsp_pdata)
|
||||
#define OMAP2420_MCBSP_PDATA_SZ ARRAY_SIZE(omap2420_mcbsp_pdata)
|
||||
#else
|
||||
#define omap24xx_mcbsp_pdata NULL
|
||||
#define OMAP24XX_MCBSP_PDATA_SZ 0
|
||||
#define omap2420_mcbsp_pdata NULL
|
||||
#define OMAP2420_MCBSP_PDATA_SZ 0
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_ARCH_OMAP2430
|
||||
static struct omap_mcbsp_platform_data omap2430_mcbsp_pdata[] = {
|
||||
{
|
||||
.phys_base = OMAP24XX_MCBSP1_BASE,
|
||||
.dma_rx_sync = OMAP24XX_DMA_MCBSP1_RX,
|
||||
.dma_tx_sync = OMAP24XX_DMA_MCBSP1_TX,
|
||||
.rx_irq = INT_24XX_MCBSP1_IRQ_RX,
|
||||
.tx_irq = INT_24XX_MCBSP1_IRQ_TX,
|
||||
.ops = &omap2_mcbsp_ops,
|
||||
.clk_name = "mcbsp_clk",
|
||||
},
|
||||
{
|
||||
.phys_base = OMAP24XX_MCBSP2_BASE,
|
||||
.dma_rx_sync = OMAP24XX_DMA_MCBSP2_RX,
|
||||
.dma_tx_sync = OMAP24XX_DMA_MCBSP2_TX,
|
||||
.rx_irq = INT_24XX_MCBSP2_IRQ_RX,
|
||||
.tx_irq = INT_24XX_MCBSP2_IRQ_TX,
|
||||
.ops = &omap2_mcbsp_ops,
|
||||
.clk_name = "mcbsp_clk",
|
||||
},
|
||||
{
|
||||
.phys_base = OMAP2430_MCBSP3_BASE,
|
||||
.dma_rx_sync = OMAP24XX_DMA_MCBSP3_RX,
|
||||
.dma_tx_sync = OMAP24XX_DMA_MCBSP3_TX,
|
||||
.rx_irq = INT_24XX_MCBSP3_IRQ_RX,
|
||||
.tx_irq = INT_24XX_MCBSP3_IRQ_TX,
|
||||
.ops = &omap2_mcbsp_ops,
|
||||
.clk_name = "mcbsp_clk",
|
||||
},
|
||||
{
|
||||
.phys_base = OMAP2430_MCBSP4_BASE,
|
||||
.dma_rx_sync = OMAP24XX_DMA_MCBSP4_RX,
|
||||
.dma_tx_sync = OMAP24XX_DMA_MCBSP4_TX,
|
||||
.rx_irq = INT_24XX_MCBSP4_IRQ_RX,
|
||||
.tx_irq = INT_24XX_MCBSP4_IRQ_TX,
|
||||
.ops = &omap2_mcbsp_ops,
|
||||
.clk_name = "mcbsp_clk",
|
||||
},
|
||||
{
|
||||
.phys_base = OMAP2430_MCBSP5_BASE,
|
||||
.dma_rx_sync = OMAP24XX_DMA_MCBSP5_RX,
|
||||
.dma_tx_sync = OMAP24XX_DMA_MCBSP5_TX,
|
||||
.rx_irq = INT_24XX_MCBSP5_IRQ_RX,
|
||||
.tx_irq = INT_24XX_MCBSP5_IRQ_TX,
|
||||
.ops = &omap2_mcbsp_ops,
|
||||
.clk_name = "mcbsp_clk",
|
||||
},
|
||||
};
|
||||
#define OMAP2430_MCBSP_PDATA_SZ ARRAY_SIZE(omap2430_mcbsp_pdata)
|
||||
#else
|
||||
#define omap2430_mcbsp_pdata NULL
|
||||
#define OMAP2430_MCBSP_PDATA_SZ 0
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_ARCH_OMAP34XX
|
||||
static struct omap_mcbsp_platform_data omap34xx_mcbsp_pdata[] = {
|
||||
{
|
||||
.phys_base = OMAP34XX_MCBSP1_BASE,
|
||||
.virt_base = IO_ADDRESS(OMAP34XX_MCBSP1_BASE),
|
||||
.dma_rx_sync = OMAP24XX_DMA_MCBSP1_RX,
|
||||
.dma_tx_sync = OMAP24XX_DMA_MCBSP1_TX,
|
||||
.rx_irq = INT_24XX_MCBSP1_IRQ_RX,
|
||||
|
@ -174,7 +239,6 @@ static struct omap_mcbsp_platform_data omap34xx_mcbsp_pdata[] = {
|
|||
},
|
||||
{
|
||||
.phys_base = OMAP34XX_MCBSP2_BASE,
|
||||
.virt_base = IO_ADDRESS(OMAP34XX_MCBSP2_BASE),
|
||||
.dma_rx_sync = OMAP24XX_DMA_MCBSP2_RX,
|
||||
.dma_tx_sync = OMAP24XX_DMA_MCBSP2_TX,
|
||||
.rx_irq = INT_24XX_MCBSP2_IRQ_RX,
|
||||
|
@ -182,6 +246,33 @@ static struct omap_mcbsp_platform_data omap34xx_mcbsp_pdata[] = {
|
|||
.ops = &omap2_mcbsp_ops,
|
||||
.clk_name = "mcbsp_clk",
|
||||
},
|
||||
{
|
||||
.phys_base = OMAP34XX_MCBSP3_BASE,
|
||||
.dma_rx_sync = OMAP24XX_DMA_MCBSP3_RX,
|
||||
.dma_tx_sync = OMAP24XX_DMA_MCBSP3_TX,
|
||||
.rx_irq = INT_24XX_MCBSP3_IRQ_RX,
|
||||
.tx_irq = INT_24XX_MCBSP3_IRQ_TX,
|
||||
.ops = &omap2_mcbsp_ops,
|
||||
.clk_name = "mcbsp_clk",
|
||||
},
|
||||
{
|
||||
.phys_base = OMAP34XX_MCBSP4_BASE,
|
||||
.dma_rx_sync = OMAP24XX_DMA_MCBSP4_RX,
|
||||
.dma_tx_sync = OMAP24XX_DMA_MCBSP4_TX,
|
||||
.rx_irq = INT_24XX_MCBSP4_IRQ_RX,
|
||||
.tx_irq = INT_24XX_MCBSP4_IRQ_TX,
|
||||
.ops = &omap2_mcbsp_ops,
|
||||
.clk_name = "mcbsp_clk",
|
||||
},
|
||||
{
|
||||
.phys_base = OMAP34XX_MCBSP5_BASE,
|
||||
.dma_rx_sync = OMAP24XX_DMA_MCBSP5_RX,
|
||||
.dma_tx_sync = OMAP24XX_DMA_MCBSP5_TX,
|
||||
.rx_irq = INT_24XX_MCBSP5_IRQ_RX,
|
||||
.tx_irq = INT_24XX_MCBSP5_IRQ_TX,
|
||||
.ops = &omap2_mcbsp_ops,
|
||||
.clk_name = "mcbsp_clk",
|
||||
},
|
||||
};
|
||||
#define OMAP34XX_MCBSP_PDATA_SZ ARRAY_SIZE(omap34xx_mcbsp_pdata)
|
||||
#else
|
||||
|
@ -189,7 +280,7 @@ static struct omap_mcbsp_platform_data omap34xx_mcbsp_pdata[] = {
|
|||
#define OMAP34XX_MCBSP_PDATA_SZ 0
|
||||
#endif
|
||||
|
||||
int __init omap2_mcbsp_init(void)
|
||||
static int __init omap2_mcbsp_init(void)
|
||||
{
|
||||
int i;
|
||||
|
||||
|
@ -199,10 +290,24 @@ int __init omap2_mcbsp_init(void)
|
|||
clk_register(&omap_mcbsp_clks[i].clk);
|
||||
}
|
||||
|
||||
if (cpu_is_omap24xx())
|
||||
omap_mcbsp_register_board_cfg(omap24xx_mcbsp_pdata,
|
||||
OMAP24XX_MCBSP_PDATA_SZ);
|
||||
if (cpu_is_omap2420())
|
||||
omap_mcbsp_count = OMAP2420_MCBSP_PDATA_SZ;
|
||||
if (cpu_is_omap2430())
|
||||
omap_mcbsp_count = OMAP2430_MCBSP_PDATA_SZ;
|
||||
if (cpu_is_omap34xx())
|
||||
omap_mcbsp_count = OMAP34XX_MCBSP_PDATA_SZ;
|
||||
|
||||
mcbsp_ptr = kzalloc(omap_mcbsp_count * sizeof(struct omap_mcbsp *),
|
||||
GFP_KERNEL);
|
||||
if (!mcbsp_ptr)
|
||||
return -ENOMEM;
|
||||
|
||||
if (cpu_is_omap2420())
|
||||
omap_mcbsp_register_board_cfg(omap2420_mcbsp_pdata,
|
||||
OMAP2420_MCBSP_PDATA_SZ);
|
||||
if (cpu_is_omap2430())
|
||||
omap_mcbsp_register_board_cfg(omap2430_mcbsp_pdata,
|
||||
OMAP2430_MCBSP_PDATA_SZ);
|
||||
if (cpu_is_omap34xx())
|
||||
omap_mcbsp_register_board_cfg(omap34xx_mcbsp_pdata,
|
||||
OMAP34XX_MCBSP_PDATA_SZ);
|
||||
|
|
|
@ -101,6 +101,17 @@ u32 omap2_reprogram_sdrc(u32 level, u32 force)
|
|||
return prev;
|
||||
}
|
||||
|
||||
#if !defined(CONFIG_ARCH_OMAP2)
|
||||
void omap2_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
|
||||
u32 base_cs, u32 force_unlock)
|
||||
{
|
||||
}
|
||||
void omap2_sram_reprogram_sdrc(u32 perf_level, u32 dll_val,
|
||||
u32 mem_type)
|
||||
{
|
||||
}
|
||||
#endif
|
||||
|
||||
void omap2_init_memory_params(u32 force_lock_to_unlock_mode)
|
||||
{
|
||||
unsigned long dll_cnt;
|
||||
|
@ -165,6 +176,9 @@ void __init omap2_init_memory(void)
|
|||
{
|
||||
u32 l;
|
||||
|
||||
if (!cpu_is_omap2420())
|
||||
return;
|
||||
|
||||
l = sms_read_reg(SMS_SYSCONFIG);
|
||||
l &= ~(0x3 << 3);
|
||||
l |= (0x2 << 3);
|
||||
|
|
|
@ -14,6 +14,9 @@
|
|||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef ARCH_ARM_MACH_OMAP2_MEMORY_H
|
||||
#define ARCH_ARM_MACH_OMAP2_MEMORY_H
|
||||
|
||||
/* Memory timings */
|
||||
#define M_DDR 1
|
||||
#define M_LOCK_CTRL (1 << 2)
|
||||
|
@ -34,3 +37,7 @@ extern u32 omap2_memory_get_fast_dll_ctrl(void);
|
|||
extern u32 omap2_memory_get_type(void);
|
||||
u32 omap2_dll_force_needed(void);
|
||||
u32 omap2_reprogram_sdrc(u32 level, u32 force);
|
||||
void __init omap2_init_memory(void);
|
||||
void __init gpmc_init(void);
|
||||
|
||||
#endif
|
||||
|
|
|
@ -1,7 +1,7 @@
|
|||
/*
|
||||
* linux/arch/arm/mach-omap2/mux.c
|
||||
*
|
||||
* OMAP2 pin multiplexing configurations
|
||||
* OMAP2 and OMAP3 pin multiplexing configurations
|
||||
*
|
||||
* Copyright (C) 2004 - 2008 Texas Instruments Inc.
|
||||
* Copyright (C) 2003 - 2008 Nokia Corporation
|
||||
|
@ -220,16 +220,222 @@ MUX_CFG_24XX("AD13_2430_MCBSP2_DR_OFF", 0x0131, 0, 0, 0, 1)
|
|||
#define OMAP24XX_PINS_SZ 0
|
||||
#endif /* CONFIG_ARCH_OMAP24XX */
|
||||
|
||||
#define OMAP24XX_PULL_ENA (1 << 3)
|
||||
#define OMAP24XX_PULL_UP (1 << 4)
|
||||
#ifdef CONFIG_ARCH_OMAP34XX
|
||||
static struct pin_config __initdata_or_module omap34xx_pins[] = {
|
||||
/*
|
||||
* Name, reg-offset,
|
||||
* mux-mode | [active-mode | off-mode]
|
||||
*/
|
||||
|
||||
/* 34xx I2C */
|
||||
MUX_CFG_34XX("K21_34XX_I2C1_SCL", 0x1ba,
|
||||
OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
|
||||
MUX_CFG_34XX("J21_34XX_I2C1_SDA", 0x1bc,
|
||||
OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
|
||||
MUX_CFG_34XX("AF15_34XX_I2C2_SCL", 0x1be,
|
||||
OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
|
||||
MUX_CFG_34XX("AE15_34XX_I2C2_SDA", 0x1c0,
|
||||
OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
|
||||
MUX_CFG_34XX("AF14_34XX_I2C3_SCL", 0x1c2,
|
||||
OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
|
||||
MUX_CFG_34XX("AG14_34XX_I2C3_SDA", 0x1c4,
|
||||
OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
|
||||
MUX_CFG_34XX("AD26_34XX_I2C4_SCL", 0xa00,
|
||||
OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
|
||||
MUX_CFG_34XX("AE26_34XX_I2C4_SDA", 0xa02,
|
||||
OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
|
||||
|
||||
/* PHY - HSUSB: 12-pin ULPI PHY: Port 1*/
|
||||
MUX_CFG_34XX("Y8_3430_USB1HS_PHY_CLK", 0x5da,
|
||||
OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_OUTPUT)
|
||||
MUX_CFG_34XX("Y9_3430_USB1HS_PHY_STP", 0x5d8,
|
||||
OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_OUTPUT)
|
||||
MUX_CFG_34XX("AA14_3430_USB1HS_PHY_DIR", 0x5ec,
|
||||
OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
|
||||
MUX_CFG_34XX("AA11_3430_USB1HS_PHY_NXT", 0x5ee,
|
||||
OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
|
||||
MUX_CFG_34XX("W13_3430_USB1HS_PHY_D0", 0x5dc,
|
||||
OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
|
||||
MUX_CFG_34XX("W12_3430_USB1HS_PHY_D1", 0x5de,
|
||||
OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
|
||||
MUX_CFG_34XX("W11_3430_USB1HS_PHY_D2", 0x5e0,
|
||||
OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
|
||||
MUX_CFG_34XX("Y11_3430_USB1HS_PHY_D3", 0x5ea,
|
||||
OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
|
||||
MUX_CFG_34XX("W9_3430_USB1HS_PHY_D4", 0x5e4,
|
||||
OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
|
||||
MUX_CFG_34XX("Y12_3430_USB1HS_PHY_D5", 0x5e6,
|
||||
OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
|
||||
MUX_CFG_34XX("W8_3430_USB1HS_PHY_D6", 0x5e8,
|
||||
OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
|
||||
MUX_CFG_34XX("Y13_3430_USB1HS_PHY_D7", 0x5e2,
|
||||
OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
|
||||
|
||||
/* PHY - HSUSB: 12-pin ULPI PHY: Port 2*/
|
||||
MUX_CFG_34XX("AA8_3430_USB2HS_PHY_CLK", 0x5f0,
|
||||
OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_OUTPUT)
|
||||
MUX_CFG_34XX("AA10_3430_USB2HS_PHY_STP", 0x5f2,
|
||||
OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_OUTPUT)
|
||||
MUX_CFG_34XX("AA9_3430_USB2HS_PHY_DIR", 0x5f4,
|
||||
OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
|
||||
MUX_CFG_34XX("AB11_3430_USB2HS_PHY_NXT", 0x5f6,
|
||||
OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
|
||||
MUX_CFG_34XX("AB10_3430_USB2HS_PHY_D0", 0x5f8,
|
||||
OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
|
||||
MUX_CFG_34XX("AB9_3430_USB2HS_PHY_D1", 0x5fa,
|
||||
OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
|
||||
MUX_CFG_34XX("W3_3430_USB2HS_PHY_D2", 0x1d4,
|
||||
OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
|
||||
MUX_CFG_34XX("T4_3430_USB2HS_PHY_D3", 0x1de,
|
||||
OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
|
||||
MUX_CFG_34XX("T3_3430_USB2HS_PHY_D4", 0x1d8,
|
||||
OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
|
||||
MUX_CFG_34XX("R3_3430_USB2HS_PHY_D5", 0x1da,
|
||||
OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
|
||||
MUX_CFG_34XX("R4_3430_USB2HS_PHY_D6", 0x1dc,
|
||||
OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
|
||||
MUX_CFG_34XX("T2_3430_USB2HS_PHY_D7", 0x1d6,
|
||||
OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
|
||||
|
||||
/* TLL - HSUSB: 12-pin TLL Port 1*/
|
||||
MUX_CFG_34XX("Y8_3430_USB1HS_TLL_CLK", 0x5da,
|
||||
OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
|
||||
MUX_CFG_34XX("Y9_3430_USB1HS_TLL_STP", 0x5d8,
|
||||
OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLUP)
|
||||
MUX_CFG_34XX("AA14_3430_USB1HS_TLL_DIR", 0x5ec,
|
||||
OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
|
||||
MUX_CFG_34XX("AA11_3430_USB1HS_TLL_NXT", 0x5ee,
|
||||
OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
|
||||
MUX_CFG_34XX("W13_3430_USB1HS_TLL_D0", 0x5dc,
|
||||
OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
|
||||
MUX_CFG_34XX("W12_3430_USB1HS_TLL_D1", 0x5de,
|
||||
OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
|
||||
MUX_CFG_34XX("W11_3430_USB1HS_TLL_D2", 0x5e0,
|
||||
OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
|
||||
MUX_CFG_34XX("Y11_3430_USB1HS_TLL_D3", 0x5ea,
|
||||
OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
|
||||
MUX_CFG_34XX("W9_3430_USB1HS_TLL_D4", 0x5e4,
|
||||
OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
|
||||
MUX_CFG_34XX("Y12_3430_USB1HS_TLL_D5", 0x5e6,
|
||||
OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
|
||||
MUX_CFG_34XX("W8_3430_USB1HS_TLL_D6", 0x5e8,
|
||||
OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
|
||||
MUX_CFG_34XX("Y13_3430_USB1HS_TLL_D7", 0x5e2,
|
||||
OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
|
||||
|
||||
/* TLL - HSUSB: 12-pin TLL Port 2*/
|
||||
MUX_CFG_34XX("AA8_3430_USB2HS_TLL_CLK", 0x5f0,
|
||||
OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
|
||||
MUX_CFG_34XX("AA10_3430_USB2HS_TLL_STP", 0x5f2,
|
||||
OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLUP)
|
||||
MUX_CFG_34XX("AA9_3430_USB2HS_TLL_DIR", 0x5f4,
|
||||
OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
|
||||
MUX_CFG_34XX("AB11_3430_USB2HS_TLL_NXT", 0x5f6,
|
||||
OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
|
||||
MUX_CFG_34XX("AB10_3430_USB2HS_TLL_D0", 0x5f8,
|
||||
OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
|
||||
MUX_CFG_34XX("AB9_3430_USB2HS_TLL_D1", 0x5fa,
|
||||
OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
|
||||
MUX_CFG_34XX("W3_3430_USB2HS_TLL_D2", 0x1d4,
|
||||
OMAP34XX_MUX_MODE2 | OMAP34XX_PIN_INPUT_PULLDOWN)
|
||||
MUX_CFG_34XX("T4_3430_USB2HS_TLL_D3", 0x1de,
|
||||
OMAP34XX_MUX_MODE2 | OMAP34XX_PIN_INPUT_PULLDOWN)
|
||||
MUX_CFG_34XX("T3_3430_USB2HS_TLL_D4", 0x1d8,
|
||||
OMAP34XX_MUX_MODE2 | OMAP34XX_PIN_INPUT_PULLDOWN)
|
||||
MUX_CFG_34XX("R3_3430_USB2HS_TLL_D5", 0x1da,
|
||||
OMAP34XX_MUX_MODE2 | OMAP34XX_PIN_INPUT_PULLDOWN)
|
||||
MUX_CFG_34XX("R4_3430_USB2HS_TLL_D6", 0x1dc,
|
||||
OMAP34XX_MUX_MODE2 | OMAP34XX_PIN_INPUT_PULLDOWN)
|
||||
MUX_CFG_34XX("T2_3430_USB2HS_TLL_D7", 0x1d6,
|
||||
OMAP34XX_MUX_MODE2 | OMAP34XX_PIN_INPUT_PULLDOWN)
|
||||
|
||||
/* TLL - HSUSB: 12-pin TLL Port 3*/
|
||||
MUX_CFG_34XX("AA6_3430_USB3HS_TLL_CLK", 0x180,
|
||||
OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
|
||||
MUX_CFG_34XX("AB3_3430_USB3HS_TLL_STP", 0x166,
|
||||
OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLUP)
|
||||
MUX_CFG_34XX("AA3_3430_USB3HS_TLL_DIR", 0x168,
|
||||
OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
|
||||
MUX_CFG_34XX("Y3_3430_USB3HS_TLL_NXT", 0x16a,
|
||||
OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
|
||||
MUX_CFG_34XX("AA5_3430_USB3HS_TLL_D0", 0x186,
|
||||
OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
|
||||
MUX_CFG_34XX("Y4_3430_USB3HS_TLL_D1", 0x184,
|
||||
OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
|
||||
MUX_CFG_34XX("Y5_3430_USB3HS_TLL_D2", 0x188,
|
||||
OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
|
||||
MUX_CFG_34XX("W5_3430_USB3HS_TLL_D3", 0x18a,
|
||||
OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
|
||||
MUX_CFG_34XX("AB12_3430_USB3HS_TLL_D4", 0x16c,
|
||||
OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
|
||||
MUX_CFG_34XX("AB13_3430_USB3HS_TLL_D5", 0x16e,
|
||||
OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
|
||||
MUX_CFG_34XX("AA13_3430_USB3HS_TLL_D6", 0x170,
|
||||
OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
|
||||
MUX_CFG_34XX("AA12_3430_USB3HS_TLL_D7", 0x172,
|
||||
OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
|
||||
|
||||
/* PHY FSUSB: FS Serial for Port 1 (multiple PHY modes supported) */
|
||||
MUX_CFG_34XX("AF10_3430_USB1FS_PHY_MM1_RXDP", 0x5d8,
|
||||
OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
|
||||
MUX_CFG_34XX("AG9_3430_USB1FS_PHY_MM1_RXDM", 0x5ee,
|
||||
OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
|
||||
MUX_CFG_34XX("W13_3430_USB1FS_PHY_MM1_RXRCV", 0x5dc,
|
||||
OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
|
||||
MUX_CFG_34XX("W12_3430_USB1FS_PHY_MM1_TXSE0", 0x5de,
|
||||
OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
|
||||
MUX_CFG_34XX("W11_3430_USB1FS_PHY_MM1_TXDAT", 0x5e0,
|
||||
OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
|
||||
MUX_CFG_34XX("Y11_3430_USB1FS_PHY_MM1_TXEN_N", 0x5ea,
|
||||
OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_OUTPUT)
|
||||
|
||||
/* PHY FSUSB: FS Serial for Port 2 (multiple PHY modes supported) */
|
||||
MUX_CFG_34XX("AF7_3430_USB2FS_PHY_MM2_RXDP", 0x5f2,
|
||||
OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
|
||||
MUX_CFG_34XX("AH7_3430_USB2FS_PHY_MM2_RXDM", 0x5f6,
|
||||
OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
|
||||
MUX_CFG_34XX("AB10_3430_USB2FS_PHY_MM2_RXRCV", 0x5f8,
|
||||
OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
|
||||
MUX_CFG_34XX("AB9_3430_USB2FS_PHY_MM2_TXSE0", 0x5fa,
|
||||
OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
|
||||
MUX_CFG_34XX("W3_3430_USB2FS_PHY_MM2_TXDAT", 0x1d4,
|
||||
OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
|
||||
MUX_CFG_34XX("T4_3430_USB2FS_PHY_MM2_TXEN_N", 0x1de,
|
||||
OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_OUTPUT)
|
||||
|
||||
/* PHY FSUSB: FS Serial for Port 3 (multiple PHY modes supported) */
|
||||
MUX_CFG_34XX("AH3_3430_USB3FS_PHY_MM3_RXDP", 0x166,
|
||||
OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
|
||||
MUX_CFG_34XX("AE3_3430_USB3FS_PHY_MM3_RXDM", 0x16a,
|
||||
OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
|
||||
MUX_CFG_34XX("AD1_3430_USB3FS_PHY_MM3_RXRCV", 0x186,
|
||||
OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
|
||||
MUX_CFG_34XX("AE1_3430_USB3FS_PHY_MM3_TXSE0", 0x184,
|
||||
OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
|
||||
MUX_CFG_34XX("AD2_3430_USB3FS_PHY_MM3_TXDAT", 0x188,
|
||||
OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
|
||||
MUX_CFG_34XX("AC1_3430_USB3FS_PHY_MM3_TXEN_N", 0x18a,
|
||||
OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_OUTPUT)
|
||||
|
||||
};
|
||||
|
||||
#define OMAP34XX_PINS_SZ ARRAY_SIZE(omap34xx_pins)
|
||||
|
||||
#else
|
||||
#define omap34xx_pins NULL
|
||||
#define OMAP34XX_PINS_SZ 0
|
||||
#endif /* CONFIG_ARCH_OMAP34XX */
|
||||
|
||||
#if defined(CONFIG_OMAP_MUX_DEBUG) || defined(CONFIG_OMAP_MUX_WARNINGS)
|
||||
void __init_or_module omap2_cfg_debug(const struct pin_config *cfg, u8 reg)
|
||||
static void __init_or_module omap2_cfg_debug(const struct pin_config *cfg, u16 reg)
|
||||
{
|
||||
u16 orig;
|
||||
u8 warn = 0, debug = 0;
|
||||
|
||||
orig = omap_ctrl_readb(cfg->mux_reg);
|
||||
if (cpu_is_omap24xx())
|
||||
orig = omap_ctrl_readb(cfg->mux_reg);
|
||||
else
|
||||
orig = omap_ctrl_readw(cfg->mux_reg);
|
||||
|
||||
#ifdef CONFIG_OMAP_MUX_DEBUG
|
||||
debug = cfg->debug;
|
||||
|
@ -255,9 +461,9 @@ int __init_or_module omap24xx_cfg_reg(const struct pin_config *cfg)
|
|||
spin_lock_irqsave(&mux_spin_lock, flags);
|
||||
reg |= cfg->mask & 0x7;
|
||||
if (cfg->pull_val)
|
||||
reg |= OMAP24XX_PULL_ENA;
|
||||
reg |= OMAP2_PULL_ENA;
|
||||
if (cfg->pu_pd_val)
|
||||
reg |= OMAP24XX_PULL_UP;
|
||||
reg |= OMAP2_PULL_UP;
|
||||
omap2_cfg_debug(cfg, reg);
|
||||
omap_ctrl_writeb(reg, cfg->mux_reg);
|
||||
spin_unlock_irqrestore(&mux_spin_lock, flags);
|
||||
|
@ -265,7 +471,26 @@ int __init_or_module omap24xx_cfg_reg(const struct pin_config *cfg)
|
|||
return 0;
|
||||
}
|
||||
#else
|
||||
#define omap24xx_cfg_reg 0
|
||||
#define omap24xx_cfg_reg NULL
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_ARCH_OMAP34XX
|
||||
static int __init_or_module omap34xx_cfg_reg(const struct pin_config *cfg)
|
||||
{
|
||||
static DEFINE_SPINLOCK(mux_spin_lock);
|
||||
unsigned long flags;
|
||||
u16 reg = 0;
|
||||
|
||||
spin_lock_irqsave(&mux_spin_lock, flags);
|
||||
reg |= cfg->mux_val;
|
||||
omap2_cfg_debug(cfg, reg);
|
||||
omap_ctrl_writew(reg, cfg->mux_reg);
|
||||
spin_unlock_irqrestore(&mux_spin_lock, flags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
#else
|
||||
#define omap34xx_cfg_reg NULL
|
||||
#endif
|
||||
|
||||
int __init omap2_mux_init(void)
|
||||
|
@ -274,6 +499,10 @@ int __init omap2_mux_init(void)
|
|||
arch_mux_cfg.pins = omap24xx_pins;
|
||||
arch_mux_cfg.size = OMAP24XX_PINS_SZ;
|
||||
arch_mux_cfg.cfg_reg = omap24xx_cfg_reg;
|
||||
} else if (cpu_is_omap34xx()) {
|
||||
arch_mux_cfg.pins = omap34xx_pins;
|
||||
arch_mux_cfg.size = OMAP34XX_PINS_SZ;
|
||||
arch_mux_cfg.cfg_reg = omap34xx_cfg_reg;
|
||||
}
|
||||
|
||||
return omap_mux_register(&arch_mux_cfg);
|
||||
|
|
1113
arch/arm/mach-omap2/powerdomain.c
Normal file
1113
arch/arm/mach-omap2/powerdomain.c
Normal file
File diff suppressed because it is too large
Load diff
187
arch/arm/mach-omap2/powerdomains.h
Normal file
187
arch/arm/mach-omap2/powerdomains.h
Normal file
|
@ -0,0 +1,187 @@
|
|||
/*
|
||||
* OMAP2/3 common powerdomain definitions
|
||||
*
|
||||
* Copyright (C) 2007-8 Texas Instruments, Inc.
|
||||
* Copyright (C) 2007-8 Nokia Corporation
|
||||
*
|
||||
* Written by Paul Walmsley
|
||||
* Debugging and integration fixes by Jouni Högander
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef ARCH_ARM_MACH_OMAP2_POWERDOMAINS
|
||||
#define ARCH_ARM_MACH_OMAP2_POWERDOMAINS
|
||||
|
||||
/*
|
||||
* This file contains all of the powerdomains that have some element
|
||||
* of software control for the OMAP24xx and OMAP34XX chips.
|
||||
*
|
||||
* A few notes:
|
||||
*
|
||||
* This is not an exhaustive listing of powerdomains on the chips; only
|
||||
* powerdomains that can be controlled in software.
|
||||
*
|
||||
* A useful validation rule for struct powerdomain:
|
||||
* Any powerdomain referenced by a wkdep_srcs or sleepdep_srcs array
|
||||
* must have a dep_bit assigned. So wkdep_srcs/sleepdep_srcs are really
|
||||
* just software-controllable dependencies. Non-software-controllable
|
||||
* dependencies do exist, but they are not encoded below (yet).
|
||||
*
|
||||
* 24xx does not support programmable sleep dependencies (SLEEPDEP)
|
||||
*
|
||||
*/
|
||||
|
||||
/*
|
||||
* The names for the DSP/IVA2 powerdomains are confusing.
|
||||
*
|
||||
* Most OMAP chips have an on-board DSP.
|
||||
*
|
||||
* On the 2420, this is a 'C55 DSP called, simply, the DSP. Its
|
||||
* powerdomain is called the "DSP power domain." On the 2430, the
|
||||
* on-board DSP is a 'C64 DSP, now called the IVA2 or IVA2.1. Its
|
||||
* powerdomain is still called the "DSP power domain." On the 3430,
|
||||
* the DSP is a 'C64 DSP like the 2430, also known as the IVA2; but
|
||||
* its powerdomain is now called the "IVA2 power domain."
|
||||
*
|
||||
* The 2420 also has something called the IVA, which is a separate ARM
|
||||
* core, and has nothing to do with the DSP/IVA2.
|
||||
*
|
||||
* Ideally the DSP/IVA2 could just be the same powerdomain, but the PRCM
|
||||
* address offset is different between the C55 and C64 DSPs.
|
||||
*
|
||||
* The overly-specific dep_bit names are due to a bit name collision
|
||||
* with CM_FCLKEN_{DSP,IVA2}. The DSP/IVA2 PM_WKDEP and CM_SLEEPDEP shift
|
||||
* value are the same for all powerdomains: 2
|
||||
*/
|
||||
|
||||
/*
|
||||
* XXX should dep_bit be a mask, so we can test to see if it is 0 as a
|
||||
* sanity check?
|
||||
* XXX encode hardware fixed wakeup dependencies -- esp. for 3430 CORE
|
||||
*/
|
||||
|
||||
#include <mach/powerdomain.h>
|
||||
|
||||
#include "prcm-common.h"
|
||||
#include "prm.h"
|
||||
#include "cm.h"
|
||||
|
||||
/* OMAP2/3-common powerdomains and wakeup dependencies */
|
||||
|
||||
/*
|
||||
* 2420/2430 PM_WKDEP_GFX: CORE, MPU, WKUP
|
||||
* 3430ES1 PM_WKDEP_GFX: adds IVA2, removes CORE
|
||||
* 3430ES2 PM_WKDEP_SGX: adds IVA2, removes CORE
|
||||
*/
|
||||
static struct pwrdm_dep gfx_sgx_wkdeps[] = {
|
||||
{
|
||||
.pwrdm_name = "core_pwrdm",
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
|
||||
},
|
||||
{
|
||||
.pwrdm_name = "iva2_pwrdm",
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
|
||||
},
|
||||
{
|
||||
.pwrdm_name = "mpu_pwrdm",
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX |
|
||||
CHIP_IS_OMAP3430)
|
||||
},
|
||||
{
|
||||
.pwrdm_name = "wkup_pwrdm",
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX |
|
||||
CHIP_IS_OMAP3430)
|
||||
},
|
||||
{ NULL },
|
||||
};
|
||||
|
||||
/*
|
||||
* 3430: CM_SLEEPDEP_CAM: MPU
|
||||
* 3430ES1: CM_SLEEPDEP_GFX: MPU
|
||||
* 3430ES2: CM_SLEEPDEP_SGX: MPU
|
||||
*/
|
||||
static struct pwrdm_dep cam_gfx_sleepdeps[] = {
|
||||
{
|
||||
.pwrdm_name = "mpu_pwrdm",
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
|
||||
},
|
||||
{ NULL },
|
||||
};
|
||||
|
||||
|
||||
#include "powerdomains24xx.h"
|
||||
#include "powerdomains34xx.h"
|
||||
|
||||
|
||||
/*
|
||||
* OMAP2/3 common powerdomains
|
||||
*/
|
||||
|
||||
/*
|
||||
* The GFX powerdomain is not present on 3430ES2, but currently we do not
|
||||
* have a macro to filter it out at compile-time.
|
||||
*/
|
||||
static struct powerdomain gfx_pwrdm = {
|
||||
.name = "gfx_pwrdm",
|
||||
.prcm_offs = GFX_MOD,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX |
|
||||
CHIP_IS_OMAP3430ES1),
|
||||
.wkdep_srcs = gfx_sgx_wkdeps,
|
||||
.sleepdep_srcs = cam_gfx_sleepdeps,
|
||||
.pwrsts = PWRSTS_OFF_RET_ON,
|
||||
.pwrsts_logic_ret = PWRDM_POWER_RET,
|
||||
.banks = 1,
|
||||
.pwrsts_mem_ret = {
|
||||
[0] = PWRDM_POWER_RET, /* MEMRETSTATE */
|
||||
},
|
||||
.pwrsts_mem_on = {
|
||||
[0] = PWRDM_POWER_ON, /* MEMONSTATE */
|
||||
},
|
||||
};
|
||||
|
||||
static struct powerdomain wkup_pwrdm = {
|
||||
.name = "wkup_pwrdm",
|
||||
.prcm_offs = WKUP_MOD,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX | CHIP_IS_OMAP3430),
|
||||
.dep_bit = OMAP_EN_WKUP_SHIFT,
|
||||
};
|
||||
|
||||
|
||||
|
||||
/* As powerdomains are added or removed above, this list must also be changed */
|
||||
static struct powerdomain *powerdomains_omap[] __initdata = {
|
||||
|
||||
&gfx_pwrdm,
|
||||
&wkup_pwrdm,
|
||||
|
||||
#ifdef CONFIG_ARCH_OMAP24XX
|
||||
&dsp_pwrdm,
|
||||
&mpu_24xx_pwrdm,
|
||||
&core_24xx_pwrdm,
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_ARCH_OMAP2430
|
||||
&mdm_pwrdm,
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_ARCH_OMAP34XX
|
||||
&iva2_pwrdm,
|
||||
&mpu_34xx_pwrdm,
|
||||
&neon_pwrdm,
|
||||
&core_34xx_pwrdm,
|
||||
&cam_pwrdm,
|
||||
&dss_pwrdm,
|
||||
&per_pwrdm,
|
||||
&emu_pwrdm,
|
||||
&sgx_pwrdm,
|
||||
&usbhost_pwrdm,
|
||||
#endif
|
||||
|
||||
NULL
|
||||
};
|
||||
|
||||
|
||||
#endif
|
200
arch/arm/mach-omap2/powerdomains24xx.h
Normal file
200
arch/arm/mach-omap2/powerdomains24xx.h
Normal file
|
@ -0,0 +1,200 @@
|
|||
/*
|
||||
* OMAP24XX powerdomain definitions
|
||||
*
|
||||
* Copyright (C) 2007-2008 Texas Instruments, Inc.
|
||||
* Copyright (C) 2007-2008 Nokia Corporation
|
||||
*
|
||||
* Written by Paul Walmsley
|
||||
* Debugging and integration fixes by Jouni Högander
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef ARCH_ARM_MACH_OMAP2_POWERDOMAINS24XX
|
||||
#define ARCH_ARM_MACH_OMAP2_POWERDOMAINS24XX
|
||||
|
||||
/*
|
||||
* N.B. If powerdomains are added or removed from this file, update
|
||||
* the array in mach-omap2/powerdomains.h.
|
||||
*/
|
||||
|
||||
#include <mach/powerdomain.h>
|
||||
|
||||
#include "prcm-common.h"
|
||||
#include "prm.h"
|
||||
#include "prm-regbits-24xx.h"
|
||||
#include "cm.h"
|
||||
#include "cm-regbits-24xx.h"
|
||||
|
||||
/* 24XX powerdomains and dependencies */
|
||||
|
||||
#ifdef CONFIG_ARCH_OMAP24XX
|
||||
|
||||
|
||||
/* Wakeup dependency source arrays */
|
||||
|
||||
/*
|
||||
* 2420/2430 PM_WKDEP_DSP: CORE, MPU, WKUP
|
||||
* 2430 PM_WKDEP_MDM: same as above
|
||||
*/
|
||||
static struct pwrdm_dep dsp_mdm_24xx_wkdeps[] = {
|
||||
{
|
||||
.pwrdm_name = "core_pwrdm",
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
|
||||
},
|
||||
{
|
||||
.pwrdm_name = "mpu_pwrdm",
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
|
||||
},
|
||||
{
|
||||
.pwrdm_name = "wkup_pwrdm",
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
|
||||
},
|
||||
{ NULL },
|
||||
};
|
||||
|
||||
/*
|
||||
* 2420 PM_WKDEP_MPU: CORE, DSP, WKUP
|
||||
* 2430 adds MDM
|
||||
*/
|
||||
static struct pwrdm_dep mpu_24xx_wkdeps[] = {
|
||||
{
|
||||
.pwrdm_name = "core_pwrdm",
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
|
||||
},
|
||||
{
|
||||
.pwrdm_name = "dsp_pwrdm",
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
|
||||
},
|
||||
{
|
||||
.pwrdm_name = "wkup_pwrdm",
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
|
||||
},
|
||||
{
|
||||
.pwrdm_name = "mdm_pwrdm",
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
|
||||
},
|
||||
{ NULL },
|
||||
};
|
||||
|
||||
/*
|
||||
* 2420 PM_WKDEP_CORE: DSP, GFX, MPU, WKUP
|
||||
* 2430 adds MDM
|
||||
*/
|
||||
static struct pwrdm_dep core_24xx_wkdeps[] = {
|
||||
{
|
||||
.pwrdm_name = "dsp_pwrdm",
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
|
||||
},
|
||||
{
|
||||
.pwrdm_name = "gfx_pwrdm",
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
|
||||
},
|
||||
{
|
||||
.pwrdm_name = "mpu_pwrdm",
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
|
||||
},
|
||||
{
|
||||
.pwrdm_name = "wkup_pwrdm",
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
|
||||
},
|
||||
{
|
||||
.pwrdm_name = "mdm_pwrdm",
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
|
||||
},
|
||||
{ NULL },
|
||||
};
|
||||
|
||||
|
||||
/* Powerdomains */
|
||||
|
||||
static struct powerdomain dsp_pwrdm = {
|
||||
.name = "dsp_pwrdm",
|
||||
.prcm_offs = OMAP24XX_DSP_MOD,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX),
|
||||
.dep_bit = OMAP24XX_PM_WKDEP_MPU_EN_DSP_SHIFT,
|
||||
.wkdep_srcs = dsp_mdm_24xx_wkdeps,
|
||||
.pwrsts = PWRSTS_OFF_RET_ON,
|
||||
.pwrsts_logic_ret = PWRDM_POWER_RET,
|
||||
.banks = 1,
|
||||
.pwrsts_mem_ret = {
|
||||
[0] = PWRDM_POWER_RET,
|
||||
},
|
||||
.pwrsts_mem_on = {
|
||||
[0] = PWRDM_POWER_ON,
|
||||
},
|
||||
};
|
||||
|
||||
static struct powerdomain mpu_24xx_pwrdm = {
|
||||
.name = "mpu_pwrdm",
|
||||
.prcm_offs = MPU_MOD,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX),
|
||||
.dep_bit = OMAP24XX_EN_MPU_SHIFT,
|
||||
.wkdep_srcs = mpu_24xx_wkdeps,
|
||||
.pwrsts = PWRSTS_OFF_RET_ON,
|
||||
.pwrsts_logic_ret = PWRSTS_OFF_RET,
|
||||
.banks = 1,
|
||||
.pwrsts_mem_ret = {
|
||||
[0] = PWRDM_POWER_RET,
|
||||
},
|
||||
.pwrsts_mem_on = {
|
||||
[0] = PWRDM_POWER_ON,
|
||||
},
|
||||
};
|
||||
|
||||
static struct powerdomain core_24xx_pwrdm = {
|
||||
.name = "core_pwrdm",
|
||||
.prcm_offs = CORE_MOD,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX),
|
||||
.wkdep_srcs = core_24xx_wkdeps,
|
||||
.pwrsts = PWRSTS_OFF_RET_ON,
|
||||
.dep_bit = OMAP24XX_EN_CORE_SHIFT,
|
||||
.banks = 3,
|
||||
.pwrsts_mem_ret = {
|
||||
[0] = PWRSTS_OFF_RET, /* MEM1RETSTATE */
|
||||
[1] = PWRSTS_OFF_RET, /* MEM2RETSTATE */
|
||||
[2] = PWRSTS_OFF_RET, /* MEM3RETSTATE */
|
||||
},
|
||||
.pwrsts_mem_on = {
|
||||
[0] = PWRSTS_OFF_RET_ON, /* MEM1ONSTATE */
|
||||
[1] = PWRSTS_OFF_RET_ON, /* MEM2ONSTATE */
|
||||
[2] = PWRSTS_OFF_RET_ON, /* MEM3ONSTATE */
|
||||
},
|
||||
};
|
||||
|
||||
#endif /* CONFIG_ARCH_OMAP24XX */
|
||||
|
||||
|
||||
|
||||
/*
|
||||
* 2430-specific powerdomains
|
||||
*/
|
||||
|
||||
#ifdef CONFIG_ARCH_OMAP2430
|
||||
|
||||
/* XXX 2430 KILLDOMAINWKUP bit? No current users apparently */
|
||||
|
||||
/* Another case of bit name collisions between several registers: EN_MDM */
|
||||
static struct powerdomain mdm_pwrdm = {
|
||||
.name = "mdm_pwrdm",
|
||||
.prcm_offs = OMAP2430_MDM_MOD,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
|
||||
.dep_bit = OMAP2430_PM_WKDEP_MPU_EN_MDM_SHIFT,
|
||||
.wkdep_srcs = dsp_mdm_24xx_wkdeps,
|
||||
.pwrsts = PWRSTS_OFF_RET_ON,
|
||||
.pwrsts_logic_ret = PWRDM_POWER_RET,
|
||||
.banks = 1,
|
||||
.pwrsts_mem_ret = {
|
||||
[0] = PWRDM_POWER_RET, /* MEMRETSTATE */
|
||||
},
|
||||
.pwrsts_mem_on = {
|
||||
[0] = PWRDM_POWER_ON, /* MEMONSTATE */
|
||||
},
|
||||
};
|
||||
|
||||
#endif /* CONFIG_ARCH_OMAP2430 */
|
||||
|
||||
|
||||
#endif
|
327
arch/arm/mach-omap2/powerdomains34xx.h
Normal file
327
arch/arm/mach-omap2/powerdomains34xx.h
Normal file
|
@ -0,0 +1,327 @@
|
|||
/*
|
||||
* OMAP34XX powerdomain definitions
|
||||
*
|
||||
* Copyright (C) 2007-2008 Texas Instruments, Inc.
|
||||
* Copyright (C) 2007-2008 Nokia Corporation
|
||||
*
|
||||
* Written by Paul Walmsley
|
||||
* Debugging and integration fixes by Jouni Högander
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef ARCH_ARM_MACH_OMAP2_POWERDOMAINS34XX
|
||||
#define ARCH_ARM_MACH_OMAP2_POWERDOMAINS34XX
|
||||
|
||||
/*
|
||||
* N.B. If powerdomains are added or removed from this file, update
|
||||
* the array in mach-omap2/powerdomains.h.
|
||||
*/
|
||||
|
||||
#include <mach/powerdomain.h>
|
||||
|
||||
#include "prcm-common.h"
|
||||
#include "prm.h"
|
||||
#include "prm-regbits-34xx.h"
|
||||
#include "cm.h"
|
||||
#include "cm-regbits-34xx.h"
|
||||
|
||||
/*
|
||||
* 34XX-specific powerdomains, dependencies
|
||||
*/
|
||||
|
||||
#ifdef CONFIG_ARCH_OMAP34XX
|
||||
|
||||
/*
|
||||
* 3430: PM_WKDEP_{PER,USBHOST}: CORE, IVA2, MPU, WKUP
|
||||
* (USBHOST is ES2 only)
|
||||
*/
|
||||
static struct pwrdm_dep per_usbhost_wkdeps[] = {
|
||||
{
|
||||
.pwrdm_name = "core_pwrdm",
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
|
||||
},
|
||||
{
|
||||
.pwrdm_name = "iva2_pwrdm",
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
|
||||
},
|
||||
{
|
||||
.pwrdm_name = "mpu_pwrdm",
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
|
||||
},
|
||||
{
|
||||
.pwrdm_name = "wkup_pwrdm",
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
|
||||
},
|
||||
{ NULL },
|
||||
};
|
||||
|
||||
/*
|
||||
* 3430 PM_WKDEP_MPU: CORE, IVA2, DSS, PER
|
||||
*/
|
||||
static struct pwrdm_dep mpu_34xx_wkdeps[] = {
|
||||
{
|
||||
.pwrdm_name = "core_pwrdm",
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
|
||||
},
|
||||
{
|
||||
.pwrdm_name = "iva2_pwrdm",
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
|
||||
},
|
||||
{
|
||||
.pwrdm_name = "dss_pwrdm",
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
|
||||
},
|
||||
{
|
||||
.pwrdm_name = "per_pwrdm",
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
|
||||
},
|
||||
{ NULL },
|
||||
};
|
||||
|
||||
/*
|
||||
* 3430 PM_WKDEP_IVA2: CORE, MPU, WKUP, DSS, PER
|
||||
*/
|
||||
static struct pwrdm_dep iva2_wkdeps[] = {
|
||||
{
|
||||
.pwrdm_name = "core_pwrdm",
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
|
||||
},
|
||||
{
|
||||
.pwrdm_name = "mpu_pwrdm",
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
|
||||
},
|
||||
{
|
||||
.pwrdm_name = "wkup_pwrdm",
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
|
||||
},
|
||||
{
|
||||
.pwrdm_name = "dss_pwrdm",
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
|
||||
},
|
||||
{
|
||||
.pwrdm_name = "per_pwrdm",
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
|
||||
},
|
||||
{ NULL },
|
||||
};
|
||||
|
||||
|
||||
/* 3430 PM_WKDEP_{CAM,DSS}: IVA2, MPU, WKUP */
|
||||
static struct pwrdm_dep cam_dss_wkdeps[] = {
|
||||
{
|
||||
.pwrdm_name = "iva2_pwrdm",
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
|
||||
},
|
||||
{
|
||||
.pwrdm_name = "mpu_pwrdm",
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
|
||||
},
|
||||
{
|
||||
.pwrdm_name = "wkup_pwrdm",
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
|
||||
},
|
||||
{ NULL },
|
||||
};
|
||||
|
||||
/* 3430: PM_WKDEP_NEON: MPU */
|
||||
static struct pwrdm_dep neon_wkdeps[] = {
|
||||
{
|
||||
.pwrdm_name = "mpu_pwrdm",
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
|
||||
},
|
||||
{ NULL },
|
||||
};
|
||||
|
||||
|
||||
/* Sleep dependency source arrays for 34xx-specific pwrdms - 34XX only */
|
||||
|
||||
/*
|
||||
* 3430: CM_SLEEPDEP_{DSS,PER}: MPU, IVA
|
||||
* 3430ES2: CM_SLEEPDEP_USBHOST: MPU, IVA
|
||||
*/
|
||||
static struct pwrdm_dep dss_per_usbhost_sleepdeps[] = {
|
||||
{
|
||||
.pwrdm_name = "mpu_pwrdm",
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
|
||||
},
|
||||
{
|
||||
.pwrdm_name = "iva2_pwrdm",
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
|
||||
},
|
||||
{ NULL },
|
||||
};
|
||||
|
||||
|
||||
/*
|
||||
* Powerdomains
|
||||
*/
|
||||
|
||||
static struct powerdomain iva2_pwrdm = {
|
||||
.name = "iva2_pwrdm",
|
||||
.prcm_offs = OMAP3430_IVA2_MOD,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
|
||||
.dep_bit = OMAP3430_PM_WKDEP_MPU_EN_IVA2_SHIFT,
|
||||
.wkdep_srcs = iva2_wkdeps,
|
||||
.pwrsts = PWRSTS_OFF_RET_ON,
|
||||
.pwrsts_logic_ret = PWRSTS_OFF_RET,
|
||||
.banks = 4,
|
||||
.pwrsts_mem_ret = {
|
||||
[0] = PWRSTS_OFF_RET,
|
||||
[1] = PWRSTS_OFF_RET,
|
||||
[2] = PWRSTS_OFF_RET,
|
||||
[3] = PWRSTS_OFF_RET,
|
||||
},
|
||||
.pwrsts_mem_on = {
|
||||
[0] = PWRDM_POWER_ON,
|
||||
[1] = PWRDM_POWER_ON,
|
||||
[2] = PWRSTS_OFF_ON,
|
||||
[3] = PWRDM_POWER_ON,
|
||||
},
|
||||
};
|
||||
|
||||
static struct powerdomain mpu_34xx_pwrdm = {
|
||||
.name = "mpu_pwrdm",
|
||||
.prcm_offs = MPU_MOD,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
|
||||
.dep_bit = OMAP3430_EN_MPU_SHIFT,
|
||||
.wkdep_srcs = mpu_34xx_wkdeps,
|
||||
.pwrsts = PWRSTS_OFF_RET_ON,
|
||||
.pwrsts_logic_ret = PWRSTS_OFF_RET,
|
||||
.banks = 1,
|
||||
.pwrsts_mem_ret = {
|
||||
[0] = PWRSTS_OFF_RET,
|
||||
},
|
||||
.pwrsts_mem_on = {
|
||||
[0] = PWRSTS_OFF_ON,
|
||||
},
|
||||
};
|
||||
|
||||
/* No wkdeps or sleepdeps for 34xx core apparently */
|
||||
static struct powerdomain core_34xx_pwrdm = {
|
||||
.name = "core_pwrdm",
|
||||
.prcm_offs = CORE_MOD,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
|
||||
.pwrsts = PWRSTS_OFF_RET_ON,
|
||||
.dep_bit = OMAP3430_EN_CORE_SHIFT,
|
||||
.banks = 2,
|
||||
.pwrsts_mem_ret = {
|
||||
[0] = PWRSTS_OFF_RET, /* MEM1RETSTATE */
|
||||
[1] = PWRSTS_OFF_RET, /* MEM2RETSTATE */
|
||||
},
|
||||
.pwrsts_mem_on = {
|
||||
[0] = PWRSTS_OFF_RET_ON, /* MEM1ONSTATE */
|
||||
[1] = PWRSTS_OFF_RET_ON, /* MEM2ONSTATE */
|
||||
},
|
||||
};
|
||||
|
||||
/* Another case of bit name collisions between several registers: EN_DSS */
|
||||
static struct powerdomain dss_pwrdm = {
|
||||
.name = "dss_pwrdm",
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
|
||||
.prcm_offs = OMAP3430_DSS_MOD,
|
||||
.dep_bit = OMAP3430_PM_WKDEP_MPU_EN_DSS_SHIFT,
|
||||
.wkdep_srcs = cam_dss_wkdeps,
|
||||
.sleepdep_srcs = dss_per_usbhost_sleepdeps,
|
||||
.pwrsts = PWRSTS_OFF_RET_ON,
|
||||
.pwrsts_logic_ret = PWRDM_POWER_RET,
|
||||
.banks = 1,
|
||||
.pwrsts_mem_ret = {
|
||||
[0] = PWRDM_POWER_RET, /* MEMRETSTATE */
|
||||
},
|
||||
.pwrsts_mem_on = {
|
||||
[0] = PWRDM_POWER_ON, /* MEMONSTATE */
|
||||
},
|
||||
};
|
||||
|
||||
static struct powerdomain sgx_pwrdm = {
|
||||
.name = "sgx_pwrdm",
|
||||
.prcm_offs = OMAP3430ES2_SGX_MOD,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES2),
|
||||
.wkdep_srcs = gfx_sgx_wkdeps,
|
||||
.sleepdep_srcs = cam_gfx_sleepdeps,
|
||||
/* XXX This is accurate for 3430 SGX, but what about GFX? */
|
||||
.pwrsts = PWRSTS_OFF_RET_ON,
|
||||
.pwrsts_logic_ret = PWRDM_POWER_RET,
|
||||
.banks = 1,
|
||||
.pwrsts_mem_ret = {
|
||||
[0] = PWRDM_POWER_RET, /* MEMRETSTATE */
|
||||
},
|
||||
.pwrsts_mem_on = {
|
||||
[0] = PWRDM_POWER_ON, /* MEMONSTATE */
|
||||
},
|
||||
};
|
||||
|
||||
static struct powerdomain cam_pwrdm = {
|
||||
.name = "cam_pwrdm",
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
|
||||
.prcm_offs = OMAP3430_CAM_MOD,
|
||||
.wkdep_srcs = cam_dss_wkdeps,
|
||||
.sleepdep_srcs = cam_gfx_sleepdeps,
|
||||
.pwrsts = PWRSTS_OFF_RET_ON,
|
||||
.pwrsts_logic_ret = PWRDM_POWER_RET,
|
||||
.banks = 1,
|
||||
.pwrsts_mem_ret = {
|
||||
[0] = PWRDM_POWER_RET, /* MEMRETSTATE */
|
||||
},
|
||||
.pwrsts_mem_on = {
|
||||
[0] = PWRDM_POWER_ON, /* MEMONSTATE */
|
||||
},
|
||||
};
|
||||
|
||||
static struct powerdomain per_pwrdm = {
|
||||
.name = "per_pwrdm",
|
||||
.prcm_offs = OMAP3430_PER_MOD,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
|
||||
.dep_bit = OMAP3430_EN_PER_SHIFT,
|
||||
.wkdep_srcs = per_usbhost_wkdeps,
|
||||
.sleepdep_srcs = dss_per_usbhost_sleepdeps,
|
||||
.pwrsts = PWRSTS_OFF_RET_ON,
|
||||
.pwrsts_logic_ret = PWRSTS_OFF_RET,
|
||||
.banks = 1,
|
||||
.pwrsts_mem_ret = {
|
||||
[0] = PWRDM_POWER_RET, /* MEMRETSTATE */
|
||||
},
|
||||
.pwrsts_mem_on = {
|
||||
[0] = PWRDM_POWER_ON, /* MEMONSTATE */
|
||||
},
|
||||
};
|
||||
|
||||
static struct powerdomain emu_pwrdm = {
|
||||
.name = "emu_pwrdm",
|
||||
.prcm_offs = OMAP3430_EMU_MOD,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
|
||||
};
|
||||
|
||||
static struct powerdomain neon_pwrdm = {
|
||||
.name = "neon_pwrdm",
|
||||
.prcm_offs = OMAP3430_NEON_MOD,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
|
||||
.wkdep_srcs = neon_wkdeps,
|
||||
.pwrsts = PWRSTS_OFF_RET_ON,
|
||||
.pwrsts_logic_ret = PWRDM_POWER_RET,
|
||||
};
|
||||
|
||||
static struct powerdomain usbhost_pwrdm = {
|
||||
.name = "usbhost_pwrdm",
|
||||
.prcm_offs = OMAP3430ES2_USBHOST_MOD,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES2),
|
||||
.wkdep_srcs = per_usbhost_wkdeps,
|
||||
.sleepdep_srcs = dss_per_usbhost_sleepdeps,
|
||||
.pwrsts = PWRSTS_OFF_RET_ON,
|
||||
.pwrsts_logic_ret = PWRDM_POWER_RET,
|
||||
.banks = 1,
|
||||
.pwrsts_mem_ret = {
|
||||
[0] = PWRDM_POWER_RET, /* MEMRETSTATE */
|
||||
},
|
||||
.pwrsts_mem_on = {
|
||||
[0] = PWRDM_POWER_ON, /* MEMONSTATE */
|
||||
},
|
||||
};
|
||||
|
||||
#endif /* CONFIG_ARCH_OMAP34XX */
|
||||
|
||||
|
||||
#endif
|
|
@ -312,7 +312,8 @@
|
|||
#define OMAP3430_ST_GPT2 (1 << 3)
|
||||
|
||||
/* CM_SLEEPDEP_PER, PM_WKDEP_IVA2, PM_WKDEP_MPU, PM_WKDEP_PER shared bits */
|
||||
#define OMAP3430_EN_CORE (1 << 0)
|
||||
#define OMAP3430_EN_CORE_SHIFT 0
|
||||
#define OMAP3430_EN_CORE_MASK (1 << 0)
|
||||
|
||||
#endif
|
||||
|
||||
|
|
|
@ -29,8 +29,10 @@
|
|||
#define OMAP24XX_WKUP1_EN (1 << 0)
|
||||
|
||||
/* PM_WKDEP_GFX, PM_WKDEP_MPU, PM_WKDEP_DSP, PM_WKDEP_MDM shared bits */
|
||||
#define OMAP24XX_EN_MPU (1 << 1)
|
||||
#define OMAP24XX_EN_CORE (1 << 0)
|
||||
#define OMAP24XX_EN_MPU_SHIFT 1
|
||||
#define OMAP24XX_EN_MPU_MASK (1 << 1)
|
||||
#define OMAP24XX_EN_CORE_SHIFT 0
|
||||
#define OMAP24XX_EN_CORE_MASK (1 << 0)
|
||||
|
||||
/*
|
||||
* PM_PWSTCTRL_MPU, PM_PWSTCTRL_GFX, PM_PWSTCTRL_DSP, PM_PWSTCTRL_MDM
|
||||
|
@ -140,8 +142,10 @@
|
|||
/* 2430 calls GLOBALWMPU_RST "GLOBALWARM_RST" instead */
|
||||
|
||||
/* PM_WKDEP_MPU specific bits */
|
||||
#define OMAP2430_PM_WKDEP_MPU_EN_MDM (1 << 5)
|
||||
#define OMAP24XX_PM_WKDEP_MPU_EN_DSP (1 << 2)
|
||||
#define OMAP2430_PM_WKDEP_MPU_EN_MDM_SHIFT 5
|
||||
#define OMAP2430_PM_WKDEP_MPU_EN_MDM_MASK (1 << 5)
|
||||
#define OMAP24XX_PM_WKDEP_MPU_EN_DSP_SHIFT 2
|
||||
#define OMAP24XX_PM_WKDEP_MPU_EN_DSP_MASK (1 << 2)
|
||||
|
||||
/* PM_EVGENCTRL_MPU specific bits */
|
||||
|
||||
|
|
|
@ -68,7 +68,8 @@
|
|||
#define OMAP3430_VPINIDLE (1 << 0)
|
||||
|
||||
/* PM_WKDEP_IVA2, PM_WKDEP_MPU shared bits */
|
||||
#define OMAP3430_EN_PER (1 << 7)
|
||||
#define OMAP3430_EN_PER_SHIFT 7
|
||||
#define OMAP3430_EN_PER_MASK (1 << 7)
|
||||
|
||||
/* PM_PWSTCTRL_IVA2, PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE shared bits */
|
||||
#define OMAP3430_MEMORYCHANGE (1 << 3)
|
||||
|
@ -77,7 +78,7 @@
|
|||
#define OMAP3430_LOGICSTATEST (1 << 2)
|
||||
|
||||
/* PM_PREPWSTST_IVA2, PM_PREPWSTST_CORE shared bits */
|
||||
#define OMAP3430_LASTLOGICSTATEENTERED (1 << 2)
|
||||
#define OMAP3430_LASTLOGICSTATEENTERED (1 << 2)
|
||||
|
||||
/*
|
||||
* PM_PREPWSTST_IVA2, PM_PREPWSTST_MPU, PM_PREPWSTST_CORE,
|
||||
|
@ -278,8 +279,10 @@
|
|||
#define OMAP3430_EMULATION_MPU_RST (1 << 11)
|
||||
|
||||
/* PM_WKDEP_MPU specific bits */
|
||||
#define OMAP3430_PM_WKDEP_MPU_EN_DSS (1 << 5)
|
||||
#define OMAP3430_PM_WKDEP_MPU_EN_IVA2 (1 << 2)
|
||||
#define OMAP3430_PM_WKDEP_MPU_EN_DSS_SHIFT 5
|
||||
#define OMAP3430_PM_WKDEP_MPU_EN_DSS_MASK (1 << 5)
|
||||
#define OMAP3430_PM_WKDEP_MPU_EN_IVA2_SHIFT 2
|
||||
#define OMAP3430_PM_WKDEP_MPU_EN_IVA2_MASK (1 << 2)
|
||||
|
||||
/* PM_EVGENCTRL_MPU */
|
||||
#define OMAP3430_OFFLOADMODE_SHIFT 3
|
||||
|
|
|
@ -18,7 +18,7 @@
|
|||
|
||||
#ifndef __ASSEMBLER__
|
||||
#define OMAP_PRM_REGADDR(module, reg) \
|
||||
(void __iomem *)IO_ADDRESS(OMAP2_PRM_BASE + (module) + (reg))
|
||||
IO_ADDRESS(OMAP2_PRM_BASE + (module) + (reg))
|
||||
#else
|
||||
#define OMAP2420_PRM_REGADDR(module, reg) \
|
||||
IO_ADDRESS(OMAP2420_PRM_BASE + (module) + (reg))
|
||||
|
@ -305,7 +305,8 @@ static inline u32 prm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx)
|
|||
* 3430: PM_WKDEP_IVA2, PM_WKDEP_GFX, PM_WKDEP_DSS, PM_WKDEP_CAM,
|
||||
* PM_WKDEP_PER
|
||||
*/
|
||||
#define OMAP_EN_WKUP (1 << 4)
|
||||
#define OMAP_EN_WKUP_SHIFT 4
|
||||
#define OMAP_EN_WKUP_MASK (1 << 4)
|
||||
|
||||
/*
|
||||
* 24XX: PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE, PM_PWSTCTRL_GFX,
|
||||
|
|
|
@ -3,7 +3,7 @@
|
|||
*
|
||||
* OMAP2 serial support.
|
||||
*
|
||||
* Copyright (C) 2005 Nokia Corporation
|
||||
* Copyright (C) 2005-2008 Nokia Corporation
|
||||
* Author: Paul Mundt <paul.mundt@nokia.com>
|
||||
*
|
||||
* Based off of arch/arm/mach-omap/omap1/serial.c
|
||||
|
@ -22,38 +22,34 @@
|
|||
#include <mach/common.h>
|
||||
#include <mach/board.h>
|
||||
|
||||
static struct clk * uart1_ick = NULL;
|
||||
static struct clk * uart1_fck = NULL;
|
||||
static struct clk * uart2_ick = NULL;
|
||||
static struct clk * uart2_fck = NULL;
|
||||
static struct clk * uart3_ick = NULL;
|
||||
static struct clk * uart3_fck = NULL;
|
||||
static struct clk *uart_ick[OMAP_MAX_NR_PORTS];
|
||||
static struct clk *uart_fck[OMAP_MAX_NR_PORTS];
|
||||
|
||||
static struct plat_serial8250_port serial_platform_data[] = {
|
||||
{
|
||||
.membase = (char *)IO_ADDRESS(OMAP_UART1_BASE),
|
||||
.mapbase = (unsigned long)OMAP_UART1_BASE,
|
||||
.membase = IO_ADDRESS(OMAP_UART1_BASE),
|
||||
.mapbase = OMAP_UART1_BASE,
|
||||
.irq = 72,
|
||||
.flags = UPF_BOOT_AUTOCONF,
|
||||
.iotype = UPIO_MEM,
|
||||
.regshift = 2,
|
||||
.uartclk = OMAP16XX_BASE_BAUD * 16,
|
||||
.uartclk = OMAP24XX_BASE_BAUD * 16,
|
||||
}, {
|
||||
.membase = (char *)IO_ADDRESS(OMAP_UART2_BASE),
|
||||
.mapbase = (unsigned long)OMAP_UART2_BASE,
|
||||
.membase = IO_ADDRESS(OMAP_UART2_BASE),
|
||||
.mapbase = OMAP_UART2_BASE,
|
||||
.irq = 73,
|
||||
.flags = UPF_BOOT_AUTOCONF,
|
||||
.iotype = UPIO_MEM,
|
||||
.regshift = 2,
|
||||
.uartclk = OMAP16XX_BASE_BAUD * 16,
|
||||
.uartclk = OMAP24XX_BASE_BAUD * 16,
|
||||
}, {
|
||||
.membase = (char *)IO_ADDRESS(OMAP_UART3_BASE),
|
||||
.mapbase = (unsigned long)OMAP_UART3_BASE,
|
||||
.membase = IO_ADDRESS(OMAP_UART3_BASE),
|
||||
.mapbase = OMAP_UART3_BASE,
|
||||
.irq = 74,
|
||||
.flags = UPF_BOOT_AUTOCONF,
|
||||
.iotype = UPIO_MEM,
|
||||
.regshift = 2,
|
||||
.uartclk = OMAP16XX_BASE_BAUD * 16,
|
||||
.uartclk = OMAP24XX_BASE_BAUD * 16,
|
||||
}, {
|
||||
.flags = 0
|
||||
}
|
||||
|
@ -70,7 +66,7 @@ static inline void serial_write_reg(struct plat_serial8250_port *p, int offset,
|
|||
int value)
|
||||
{
|
||||
offset <<= p->regshift;
|
||||
__raw_writeb(value, (unsigned long)(p->membase + offset));
|
||||
__raw_writeb(value, p->membase + offset);
|
||||
}
|
||||
|
||||
/*
|
||||
|
@ -86,10 +82,27 @@ static inline void __init omap_serial_reset(struct plat_serial8250_port *p)
|
|||
serial_write_reg(p, UART_OMAP_SYSC, (0x02 << 3) | (1 << 2) | (1 << 0));
|
||||
}
|
||||
|
||||
void __init omap_serial_init()
|
||||
void omap_serial_enable_clocks(int enable)
|
||||
{
|
||||
int i;
|
||||
for (i = 0; i < OMAP_MAX_NR_PORTS; i++) {
|
||||
if (uart_ick[i] && uart_fck[i]) {
|
||||
if (enable) {
|
||||
clk_enable(uart_ick[i]);
|
||||
clk_enable(uart_fck[i]);
|
||||
} else {
|
||||
clk_disable(uart_ick[i]);
|
||||
clk_disable(uart_fck[i]);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void __init omap_serial_init(void)
|
||||
{
|
||||
int i;
|
||||
const struct omap_uart_config *info;
|
||||
char name[16];
|
||||
|
||||
/*
|
||||
* Make sure the serial ports are muxed on at this point.
|
||||
|
@ -97,8 +110,7 @@ void __init omap_serial_init()
|
|||
* if not needed.
|
||||
*/
|
||||
|
||||
info = omap_get_config(OMAP_TAG_UART,
|
||||
struct omap_uart_config);
|
||||
info = omap_get_config(OMAP_TAG_UART, struct omap_uart_config);
|
||||
|
||||
if (info == NULL)
|
||||
return;
|
||||
|
@ -107,58 +119,26 @@ void __init omap_serial_init()
|
|||
struct plat_serial8250_port *p = serial_platform_data + i;
|
||||
|
||||
if (!(info->enabled_uarts & (1 << i))) {
|
||||
p->membase = 0;
|
||||
p->membase = NULL;
|
||||
p->mapbase = 0;
|
||||
continue;
|
||||
}
|
||||
|
||||
switch (i) {
|
||||
case 0:
|
||||
uart1_ick = clk_get(NULL, "uart1_ick");
|
||||
if (IS_ERR(uart1_ick))
|
||||
printk("Could not get uart1_ick\n");
|
||||
else {
|
||||
clk_enable(uart1_ick);
|
||||
}
|
||||
sprintf(name, "uart%d_ick", i+1);
|
||||
uart_ick[i] = clk_get(NULL, name);
|
||||
if (IS_ERR(uart_ick[i])) {
|
||||
printk(KERN_ERR "Could not get uart%d_ick\n", i+1);
|
||||
uart_ick[i] = NULL;
|
||||
} else
|
||||
clk_enable(uart_ick[i]);
|
||||
|
||||
uart1_fck = clk_get(NULL, "uart1_fck");
|
||||
if (IS_ERR(uart1_fck))
|
||||
printk("Could not get uart1_fck\n");
|
||||
else {
|
||||
clk_enable(uart1_fck);
|
||||
}
|
||||
break;
|
||||
case 1:
|
||||
uart2_ick = clk_get(NULL, "uart2_ick");
|
||||
if (IS_ERR(uart2_ick))
|
||||
printk("Could not get uart2_ick\n");
|
||||
else {
|
||||
clk_enable(uart2_ick);
|
||||
}
|
||||
|
||||
uart2_fck = clk_get(NULL, "uart2_fck");
|
||||
if (IS_ERR(uart2_fck))
|
||||
printk("Could not get uart2_fck\n");
|
||||
else {
|
||||
clk_enable(uart2_fck);
|
||||
}
|
||||
break;
|
||||
case 2:
|
||||
uart3_ick = clk_get(NULL, "uart3_ick");
|
||||
if (IS_ERR(uart3_ick))
|
||||
printk("Could not get uart3_ick\n");
|
||||
else {
|
||||
clk_enable(uart3_ick);
|
||||
}
|
||||
|
||||
uart3_fck = clk_get(NULL, "uart3_fck");
|
||||
if (IS_ERR(uart3_fck))
|
||||
printk("Could not get uart3_fck\n");
|
||||
else {
|
||||
clk_enable(uart3_fck);
|
||||
}
|
||||
break;
|
||||
}
|
||||
sprintf(name, "uart%d_fck", i+1);
|
||||
uart_fck[i] = clk_get(NULL, name);
|
||||
if (IS_ERR(uart_fck[i])) {
|
||||
printk(KERN_ERR "Could not get uart%d_fck\n", i+1);
|
||||
uart_fck[i] = NULL;
|
||||
} else
|
||||
clk_enable(uart_fck[i]);
|
||||
|
||||
omap_serial_reset(p);
|
||||
}
|
||||
|
|
|
@ -5,6 +5,10 @@
|
|||
* Texas Instruments, <www.ti.com>
|
||||
* Richard Woodruff <r-woodruff2@ti.com>
|
||||
*
|
||||
* (C) Copyright 2006 Nokia Corporation
|
||||
* Fixed idle loop sleep
|
||||
* Igor Stoppa <igor.stoppa@nokia.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
|
@ -26,6 +30,8 @@
|
|||
#include <mach/io.h>
|
||||
#include <mach/pm.h>
|
||||
|
||||
#include <mach/omap24xx.h>
|
||||
|
||||
#include "sdrc.h"
|
||||
|
||||
/* First address of reserved address space? apparently valid for OMAP2 & 3 */
|
||||
|
@ -52,15 +58,14 @@ ENTRY(omap24xx_idle_loop_suspend_sz)
|
|||
.word . - omap24xx_idle_loop_suspend
|
||||
|
||||
/*
|
||||
* omap242x_cpu_suspend() - Forces OMAP into deep sleep state by completing
|
||||
* omap24xx_cpu_suspend() - Forces OMAP into deep sleep state by completing
|
||||
* SDRC shutdown then ARM shutdown. Upon wake MPU is back on so just restore
|
||||
* SDRC.
|
||||
*
|
||||
* Input:
|
||||
* R0 : DLL ctrl value pre-Sleep
|
||||
* R1 : Processor+Revision
|
||||
* 2420: 0x21 = 242xES1, 0x26 = 242xES2.2
|
||||
* 2430: 0x31 = 2430ES1, 0x32 = 2430ES2
|
||||
* R1 : SDRC_DLLA_CTRL
|
||||
* R2 : SDRC_POWER
|
||||
*
|
||||
* The if the DPLL is going to AutoIdle. It seems like the DPLL may be back on
|
||||
* when we get called, but the DLL probably isn't. We will wait a bit more in
|
||||
|
@ -80,15 +85,14 @@ ENTRY(omap24xx_idle_loop_suspend_sz)
|
|||
*/
|
||||
ENTRY(omap24xx_cpu_suspend)
|
||||
stmfd sp!, {r0 - r12, lr} @ save registers on stack
|
||||
mov r3, #0x0 @ clear for mrc call
|
||||
mov r3, #0x0 @ clear for mcr call
|
||||
mcr p15, 0, r3, c7, c10, 4 @ memory barrier, hope SDR/DDR finished
|
||||
nop
|
||||
nop
|
||||
ldr r3, A_SDRC_POWER @ addr of sdrc power
|
||||
ldr r4, [r3] @ value of sdrc power
|
||||
ldr r4, [r2] @ read SDRC_POWER
|
||||
orr r4, r4, #0x40 @ enable self refresh on idle req
|
||||
mov r5, #0x2000 @ set delay (DPLL relock + DLL relock)
|
||||
str r4, [r3] @ make it so
|
||||
str r4, [r2] @ make it so
|
||||
mov r2, #0
|
||||
nop
|
||||
mcr p15, 0, r2, c7, c0, 4 @ wait for interrupt
|
||||
|
@ -97,14 +101,13 @@ loop:
|
|||
subs r5, r5, #0x1 @ awake, wait just a bit
|
||||
bne loop
|
||||
|
||||
/* The DPLL has on before we take the DDR out of self refresh */
|
||||
/* The DPLL has to be on before we take the DDR out of self refresh */
|
||||
bic r4, r4, #0x40 @ now clear self refresh bit.
|
||||
str r4, [r3] @ put vlaue back.
|
||||
str r4, [r2] @ write to SDRC_POWER
|
||||
ldr r4, A_SDRC0 @ make a clock happen
|
||||
ldr r4, [r4]
|
||||
ldr r4, [r4] @ read A_SDRC0
|
||||
nop @ start auto refresh only after clk ok
|
||||
movs r0, r0 @ see if DDR or SDR
|
||||
ldrne r1, A_SDRC_DLLA_CTRL_S @ get addr of DLL ctrl
|
||||
strne r0, [r1] @ rewrite DLLA to force DLL reload
|
||||
addne r1, r1, #0x8 @ move to DLLB
|
||||
strne r0, [r1] @ rewrite DLLB to force DLL reload
|
||||
|
@ -116,13 +119,8 @@ loop2:
|
|||
/* resume*/
|
||||
ldmfd sp!, {r0 - r12, pc} @ restore regs and return
|
||||
|
||||
A_SDRC_POWER:
|
||||
.word OMAP242X_SDRC_REGADDR(SDRC_POWER)
|
||||
A_SDRC0:
|
||||
.word A_SDRC0_V
|
||||
A_SDRC_DLLA_CTRL_S:
|
||||
.word OMAP242X_SDRC_REGADDR(SDRC_DLLA_CTRL)
|
||||
|
||||
ENTRY(omap24xx_cpu_suspend_sz)
|
||||
.word . - omap24xx_cpu_suspend
|
||||
|
179
arch/arm/mach-omap2/sram34xx.S
Normal file
179
arch/arm/mach-omap2/sram34xx.S
Normal file
|
@ -0,0 +1,179 @@
|
|||
/*
|
||||
* linux/arch/arm/mach-omap3/sram.S
|
||||
*
|
||||
* Omap3 specific functions that need to be run in internal SRAM
|
||||
*
|
||||
* (C) Copyright 2007
|
||||
* Texas Instruments Inc.
|
||||
* Rajendra Nayak <rnayak@ti.com>
|
||||
*
|
||||
* (C) Copyright 2004
|
||||
* Texas Instruments, <www.ti.com>
|
||||
* Richard Woodruff <r-woodruff2@ti.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
#include <linux/linkage.h>
|
||||
#include <asm/assembler.h>
|
||||
#include <mach/hardware.h>
|
||||
|
||||
#include <mach/io.h>
|
||||
|
||||
#include "sdrc.h"
|
||||
#include "cm.h"
|
||||
|
||||
.text
|
||||
|
||||
/*
|
||||
* Change frequency of core dpll
|
||||
* r0 = sdrc_rfr_ctrl r1 = sdrc_actim_ctrla r2 = sdrc_actim_ctrlb r3 = M2
|
||||
*/
|
||||
ENTRY(omap3_sram_configure_core_dpll)
|
||||
stmfd sp!, {r1-r12, lr} @ store regs to stack
|
||||
cmp r3, #0x2
|
||||
blne configure_sdrc
|
||||
cmp r3, #0x2
|
||||
blne lock_dll
|
||||
cmp r3, #0x1
|
||||
blne unlock_dll
|
||||
bl sdram_in_selfrefresh @ put the SDRAM in self refresh
|
||||
bl configure_core_dpll
|
||||
bl enable_sdrc
|
||||
cmp r3, #0x1
|
||||
blne wait_dll_unlock
|
||||
cmp r3, #0x2
|
||||
blne wait_dll_lock
|
||||
cmp r3, #0x1
|
||||
blne configure_sdrc
|
||||
mov r0, #0 @ return value
|
||||
ldmfd sp!, {r1-r12, pc} @ restore regs and return
|
||||
unlock_dll:
|
||||
ldr r4, omap3_sdrc_dlla_ctrl
|
||||
ldr r5, [r4]
|
||||
orr r5, r5, #0x4
|
||||
str r5, [r4]
|
||||
bx lr
|
||||
lock_dll:
|
||||
ldr r4, omap3_sdrc_dlla_ctrl
|
||||
ldr r5, [r4]
|
||||
bic r5, r5, #0x4
|
||||
str r5, [r4]
|
||||
bx lr
|
||||
sdram_in_selfrefresh:
|
||||
mov r5, #0x0 @ Move 0 to R5
|
||||
mcr p15, 0, r5, c7, c10, 5 @ memory barrier
|
||||
ldr r4, omap3_sdrc_power @ read the SDRC_POWER register
|
||||
ldr r5, [r4] @ read the contents of SDRC_POWER
|
||||
orr r5, r5, #0x40 @ enable self refresh on idle req
|
||||
str r5, [r4] @ write back to SDRC_POWER register
|
||||
ldr r4, omap3_cm_iclken1_core @ read the CM_ICLKEN1_CORE reg
|
||||
ldr r5, [r4]
|
||||
bic r5, r5, #0x2 @ disable iclk bit for SRDC
|
||||
str r5, [r4]
|
||||
wait_sdrc_idle:
|
||||
ldr r4, omap3_cm_idlest1_core
|
||||
ldr r5, [r4]
|
||||
and r5, r5, #0x2 @ check for SDRC idle
|
||||
cmp r5, #2
|
||||
bne wait_sdrc_idle
|
||||
bx lr
|
||||
configure_core_dpll:
|
||||
ldr r4, omap3_cm_clksel1_pll
|
||||
ldr r5, [r4]
|
||||
ldr r6, core_m2_mask_val @ modify m2 for core dpll
|
||||
and r5, r5, r6
|
||||
orr r5, r5, r3, lsl #0x1B @ r3 contains the M2 val
|
||||
str r5, [r4]
|
||||
mov r5, #0x800 @ wait for the clock to stabilise
|
||||
cmp r3, #2
|
||||
bne wait_clk_stable
|
||||
bx lr
|
||||
wait_clk_stable:
|
||||
subs r5, r5, #1
|
||||
bne wait_clk_stable
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
bx lr
|
||||
enable_sdrc:
|
||||
ldr r4, omap3_cm_iclken1_core
|
||||
ldr r5, [r4]
|
||||
orr r5, r5, #0x2 @ enable iclk bit for SDRC
|
||||
str r5, [r4]
|
||||
wait_sdrc_idle1:
|
||||
ldr r4, omap3_cm_idlest1_core
|
||||
ldr r5, [r4]
|
||||
and r5, r5, #0x2
|
||||
cmp r5, #0
|
||||
bne wait_sdrc_idle1
|
||||
ldr r4, omap3_sdrc_power
|
||||
ldr r5, [r4]
|
||||
bic r5, r5, #0x40
|
||||
str r5, [r4]
|
||||
bx lr
|
||||
wait_dll_lock:
|
||||
ldr r4, omap3_sdrc_dlla_status
|
||||
ldr r5, [r4]
|
||||
and r5, r5, #0x4
|
||||
cmp r5, #0x4
|
||||
bne wait_dll_lock
|
||||
bx lr
|
||||
wait_dll_unlock:
|
||||
ldr r4, omap3_sdrc_dlla_status
|
||||
ldr r5, [r4]
|
||||
and r5, r5, #0x4
|
||||
cmp r5, #0x0
|
||||
bne wait_dll_unlock
|
||||
bx lr
|
||||
configure_sdrc:
|
||||
ldr r4, omap3_sdrc_rfr_ctrl
|
||||
str r0, [r4]
|
||||
ldr r4, omap3_sdrc_actim_ctrla
|
||||
str r1, [r4]
|
||||
ldr r4, omap3_sdrc_actim_ctrlb
|
||||
str r2, [r4]
|
||||
bx lr
|
||||
|
||||
omap3_sdrc_power:
|
||||
.word OMAP34XX_SDRC_REGADDR(SDRC_POWER)
|
||||
omap3_cm_clksel1_pll:
|
||||
.word OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKSEL1)
|
||||
omap3_cm_idlest1_core:
|
||||
.word OMAP34XX_CM_REGADDR(CORE_MOD, CM_IDLEST)
|
||||
omap3_cm_iclken1_core:
|
||||
.word OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1)
|
||||
omap3_sdrc_rfr_ctrl:
|
||||
.word OMAP34XX_SDRC_REGADDR(SDRC_RFR_CTRL_0)
|
||||
omap3_sdrc_actim_ctrla:
|
||||
.word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_A_0)
|
||||
omap3_sdrc_actim_ctrlb:
|
||||
.word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_B_0)
|
||||
omap3_sdrc_dlla_status:
|
||||
.word OMAP34XX_SDRC_REGADDR(SDRC_DLLA_STATUS)
|
||||
omap3_sdrc_dlla_ctrl:
|
||||
.word OMAP34XX_SDRC_REGADDR(SDRC_DLLA_CTRL)
|
||||
core_m2_mask_val:
|
||||
.word 0x07FFFFFF
|
||||
|
||||
ENTRY(omap3_sram_configure_core_dpll_sz)
|
||||
.word . - omap3_sram_configure_core_dpll
|
|
@ -428,7 +428,7 @@ config CPU_32v6K
|
|||
# ARMv7
|
||||
config CPU_V7
|
||||
bool "Support ARM V7 processor"
|
||||
depends on ARCH_INTEGRATOR || MACH_REALVIEW_EB
|
||||
depends on ARCH_INTEGRATOR || MACH_REALVIEW_EB || ARCH_OMAP3
|
||||
select CPU_32v6K
|
||||
select CPU_32v7
|
||||
select CPU_ABRT_EV7
|
||||
|
|
|
@ -15,6 +15,9 @@ config ARCH_OMAP1
|
|||
config ARCH_OMAP2
|
||||
bool "TI OMAP2"
|
||||
|
||||
config ARCH_OMAP3
|
||||
bool "TI OMAP3"
|
||||
|
||||
endchoice
|
||||
|
||||
comment "OMAP Feature Selections"
|
||||
|
@ -29,6 +32,30 @@ config OMAP_DEBUG_LEDS
|
|||
depends on OMAP_DEBUG_DEVICES
|
||||
default y if LEDS || LEDS_OMAP_DEBUG
|
||||
|
||||
config OMAP_DEBUG_POWERDOMAIN
|
||||
bool "Emit debug messages from powerdomain layer"
|
||||
depends on ARCH_OMAP2 || ARCH_OMAP3
|
||||
default n
|
||||
help
|
||||
Say Y here if you want to compile in powerdomain layer
|
||||
debugging messages for OMAP2/3. These messages can
|
||||
provide more detail as to why some powerdomain calls
|
||||
may be failing, and will also emit a descriptive message
|
||||
for every powerdomain register write. However, the
|
||||
extra detail costs some memory.
|
||||
|
||||
config OMAP_DEBUG_CLOCKDOMAIN
|
||||
bool "Emit debug messages from clockdomain layer"
|
||||
depends on ARCH_OMAP2 || ARCH_OMAP3
|
||||
default n
|
||||
help
|
||||
Say Y here if you want to compile in clockdomain layer
|
||||
debugging messages for OMAP2/3. These messages can
|
||||
provide more detail as to why some clockdomain calls
|
||||
may be failing, and will also emit a descriptive message
|
||||
for every clockdomain register write. However, the
|
||||
extra detail costs some memory.
|
||||
|
||||
config OMAP_RESET_CLOCKS
|
||||
bool "Reset unused clocks during boot"
|
||||
depends on ARCH_OMAP
|
||||
|
@ -88,13 +115,13 @@ config OMAP_MPU_TIMER
|
|||
|
||||
config OMAP_32K_TIMER
|
||||
bool "Use 32KHz timer"
|
||||
depends on ARCH_OMAP16XX || ARCH_OMAP24XX
|
||||
depends on ARCH_OMAP16XX || ARCH_OMAP24XX || ARCH_OMAP34XX
|
||||
help
|
||||
Select this option if you want to enable the OMAP 32KHz timer.
|
||||
This timer saves power compared to the OMAP_MPU_TIMER, and has
|
||||
support for no tick during idle. The 32KHz timer provides less
|
||||
intra-tick resolution than OMAP_MPU_TIMER. The 32KHz timer is
|
||||
currently only available for OMAP16XX and 24XX.
|
||||
currently only available for OMAP16XX, 24XX and 34XX.
|
||||
|
||||
endchoice
|
||||
|
||||
|
@ -109,7 +136,7 @@ config OMAP_32K_TIMER_HZ
|
|||
|
||||
config OMAP_DM_TIMER
|
||||
bool "Use dual-mode timer"
|
||||
depends on ARCH_OMAP16XX || ARCH_OMAP24XX
|
||||
depends on ARCH_OMAP16XX || ARCH_OMAP24XX || ARCH_OMAP34XX
|
||||
help
|
||||
Select this option if you want to use OMAP Dual-Mode timers.
|
||||
|
||||
|
|
|
@ -4,7 +4,7 @@
|
|||
|
||||
# Common support
|
||||
obj-y := common.o sram.o clock.o devices.o dma.o mux.o gpio.o \
|
||||
usb.o fb.o
|
||||
usb.o fb.o io.o
|
||||
obj-m :=
|
||||
obj-n :=
|
||||
obj- :=
|
||||
|
|
|
@ -248,6 +248,7 @@ static struct omap_globals *omap2_globals;
|
|||
|
||||
static void __init __omap2_set_globals(void)
|
||||
{
|
||||
omap2_set_globals_tap(omap2_globals);
|
||||
omap2_set_globals_memory(omap2_globals);
|
||||
omap2_set_globals_control(omap2_globals);
|
||||
omap2_set_globals_prcm(omap2_globals);
|
||||
|
@ -258,12 +259,13 @@ static void __init __omap2_set_globals(void)
|
|||
#if defined(CONFIG_ARCH_OMAP2420)
|
||||
|
||||
static struct omap_globals omap242x_globals = {
|
||||
.tap = (__force void __iomem *)OMAP2_IO_ADDRESS(0x48014000),
|
||||
.sdrc = (__force void __iomem *)OMAP2_IO_ADDRESS(OMAP2420_SDRC_BASE),
|
||||
.sms = (__force void __iomem *)OMAP2_IO_ADDRESS(OMAP2420_SMS_BASE),
|
||||
.ctrl = (__force void __iomem *)OMAP2_IO_ADDRESS(OMAP2420_CTRL_BASE),
|
||||
.prm = (__force void __iomem *)OMAP2_IO_ADDRESS(OMAP2420_PRM_BASE),
|
||||
.cm = (__force void __iomem *)OMAP2_IO_ADDRESS(OMAP2420_CM_BASE),
|
||||
.class = OMAP242X_CLASS,
|
||||
.tap = OMAP2_IO_ADDRESS(0x48014000),
|
||||
.sdrc = OMAP2_IO_ADDRESS(OMAP2420_SDRC_BASE),
|
||||
.sms = OMAP2_IO_ADDRESS(OMAP2420_SMS_BASE),
|
||||
.ctrl = OMAP2_IO_ADDRESS(OMAP2420_CTRL_BASE),
|
||||
.prm = OMAP2_IO_ADDRESS(OMAP2420_PRM_BASE),
|
||||
.cm = OMAP2_IO_ADDRESS(OMAP2420_CM_BASE),
|
||||
};
|
||||
|
||||
void __init omap2_set_globals_242x(void)
|
||||
|
@ -276,12 +278,13 @@ void __init omap2_set_globals_242x(void)
|
|||
#if defined(CONFIG_ARCH_OMAP2430)
|
||||
|
||||
static struct omap_globals omap243x_globals = {
|
||||
.tap = (__force void __iomem *)OMAP2_IO_ADDRESS(0x4900a000),
|
||||
.sdrc = (__force void __iomem *)OMAP2_IO_ADDRESS(OMAP243X_SDRC_BASE),
|
||||
.sms = (__force void __iomem *)OMAP2_IO_ADDRESS(OMAP243X_SMS_BASE),
|
||||
.ctrl = (__force void __iomem *)OMAP2_IO_ADDRESS(OMAP243X_CTRL_BASE),
|
||||
.prm = (__force void __iomem *)OMAP2_IO_ADDRESS(OMAP2430_PRM_BASE),
|
||||
.cm = (__force void __iomem *)OMAP2_IO_ADDRESS(OMAP2430_CM_BASE),
|
||||
.class = OMAP243X_CLASS,
|
||||
.tap = OMAP2_IO_ADDRESS(0x4900a000),
|
||||
.sdrc = OMAP2_IO_ADDRESS(OMAP243X_SDRC_BASE),
|
||||
.sms = OMAP2_IO_ADDRESS(OMAP243X_SMS_BASE),
|
||||
.ctrl = OMAP2_IO_ADDRESS(OMAP243X_CTRL_BASE),
|
||||
.prm = OMAP2_IO_ADDRESS(OMAP2430_PRM_BASE),
|
||||
.cm = OMAP2_IO_ADDRESS(OMAP2430_CM_BASE),
|
||||
};
|
||||
|
||||
void __init omap2_set_globals_243x(void)
|
||||
|
@ -294,12 +297,13 @@ void __init omap2_set_globals_243x(void)
|
|||
#if defined(CONFIG_ARCH_OMAP3430)
|
||||
|
||||
static struct omap_globals omap343x_globals = {
|
||||
.tap = (__force void __iomem *)OMAP2_IO_ADDRESS(0x4830A000),
|
||||
.sdrc = (__force void __iomem *)OMAP2_IO_ADDRESS(OMAP343X_SDRC_BASE),
|
||||
.sms = (__force void __iomem *)OMAP2_IO_ADDRESS(OMAP343X_SMS_BASE),
|
||||
.ctrl = (__force void __iomem *)OMAP2_IO_ADDRESS(OMAP343X_CTRL_BASE),
|
||||
.prm = (__force void __iomem *)OMAP2_IO_ADDRESS(OMAP3430_PRM_BASE),
|
||||
.cm = (__force void __iomem *)OMAP2_IO_ADDRESS(OMAP3430_CM_BASE),
|
||||
.class = OMAP343X_CLASS,
|
||||
.tap = OMAP2_IO_ADDRESS(0x4830A000),
|
||||
.sdrc = OMAP2_IO_ADDRESS(OMAP343X_SDRC_BASE),
|
||||
.sms = OMAP2_IO_ADDRESS(OMAP343X_SMS_BASE),
|
||||
.ctrl = OMAP2_IO_ADDRESS(OMAP343X_CTRL_BASE),
|
||||
.prm = OMAP2_IO_ADDRESS(OMAP3430_PRM_BASE),
|
||||
.cm = OMAP2_IO_ADDRESS(OMAP3430_CM_BASE),
|
||||
};
|
||||
|
||||
void __init omap2_set_globals_343x(void)
|
||||
|
|
|
@ -20,17 +20,17 @@
|
|||
#include <asm/mach/map.h>
|
||||
|
||||
#include <mach/tc.h>
|
||||
#include <mach/control.h>
|
||||
#include <mach/board.h>
|
||||
#include <mach/mmc.h>
|
||||
#include <mach/mux.h>
|
||||
#include <mach/gpio.h>
|
||||
#include <mach/menelaus.h>
|
||||
#include <mach/mcbsp.h>
|
||||
#include <mach/dsp_common.h>
|
||||
|
||||
#if defined(CONFIG_OMAP_DSP) || defined(CONFIG_OMAP_DSP_MODULE)
|
||||
|
||||
#include "../plat-omap/dsp/dsp_common.h"
|
||||
|
||||
static struct dsp_platform_data dsp_pdata = {
|
||||
.kdev_list = LIST_HEAD_INIT(dsp_pdata.kdev_list),
|
||||
};
|
||||
|
@ -76,7 +76,7 @@ int dsp_kfunc_device_register(struct dsp_kfunc_device *kdev)
|
|||
{
|
||||
static DEFINE_MUTEX(dsp_pdata_lock);
|
||||
|
||||
mutex_init(&kdev->lock);
|
||||
spin_lock_init(&kdev->lock);
|
||||
|
||||
mutex_lock(&dsp_pdata_lock);
|
||||
list_add_tail(&kdev->entry, &dsp_pdata.kdev_list);
|
||||
|
@ -95,6 +95,10 @@ static inline void omap_init_dsp(void) { }
|
|||
|
||||
static void omap_init_kp(void)
|
||||
{
|
||||
/* 2430 and 34xx keypad is on TWL4030 */
|
||||
if (cpu_is_omap2430() || cpu_is_omap34xx())
|
||||
return;
|
||||
|
||||
if (machine_is_omap_h2() || machine_is_omap_h3()) {
|
||||
omap_cfg_reg(F18_1610_KBC0);
|
||||
omap_cfg_reg(D20_1610_KBC1);
|
||||
|
@ -156,13 +160,6 @@ void omap_mcbsp_register_board_cfg(struct omap_mcbsp_platform_data *config,
|
|||
{
|
||||
int i;
|
||||
|
||||
if (size > OMAP_MAX_MCBSP_COUNT) {
|
||||
printk(KERN_WARNING "Registered too many McBSPs platform_data."
|
||||
" Using maximum (%d) available.\n",
|
||||
OMAP_MAX_MCBSP_COUNT);
|
||||
size = OMAP_MAX_MCBSP_COUNT;
|
||||
}
|
||||
|
||||
omap_mcbsp_devices = kzalloc(size * sizeof(struct platform_device *),
|
||||
GFP_KERNEL);
|
||||
if (!omap_mcbsp_devices) {
|
||||
|
@ -538,10 +535,6 @@ static inline void omap_init_rng(void) {}
|
|||
*/
|
||||
static int __init omap_init_devices(void)
|
||||
{
|
||||
/*
|
||||
* Need to enable relevant once for 2430 SDP
|
||||
*/
|
||||
#ifndef CONFIG_MACH_OMAP_2430SDP
|
||||
/* please keep these calls, and their implementations above,
|
||||
* in alphabetical order so they're easier to sort through.
|
||||
*/
|
||||
|
@ -551,7 +544,6 @@ static int __init omap_init_devices(void)
|
|||
omap_init_uwire();
|
||||
omap_init_wdt();
|
||||
omap_init_rng();
|
||||
#endif
|
||||
return 0;
|
||||
}
|
||||
arch_initcall(omap_init_devices);
|
||||
|
|
|
@ -1233,7 +1233,7 @@ int omap_request_dma_chain(int dev_id, const char *dev_name,
|
|||
/* request and reserve DMA channels for the chain */
|
||||
for (i = 0; i < no_of_chans; i++) {
|
||||
err = omap_request_dma(dev_id, dev_name,
|
||||
callback, 0, &channels[i]);
|
||||
callback, NULL, &channels[i]);
|
||||
if (err < 0) {
|
||||
int j;
|
||||
for (j = 0; j < i; j++)
|
||||
|
@ -2297,13 +2297,13 @@ static int __init omap_init_dma(void)
|
|||
int ch, r;
|
||||
|
||||
if (cpu_class_is_omap1()) {
|
||||
omap_dma_base = (void __iomem *)IO_ADDRESS(OMAP1_DMA_BASE);
|
||||
omap_dma_base = IO_ADDRESS(OMAP1_DMA_BASE);
|
||||
dma_lch_count = OMAP1_LOGICAL_DMA_CH_COUNT;
|
||||
} else if (cpu_is_omap24xx()) {
|
||||
omap_dma_base = (void __iomem *)IO_ADDRESS(OMAP24XX_DMA4_BASE);
|
||||
omap_dma_base = IO_ADDRESS(OMAP24XX_DMA4_BASE);
|
||||
dma_lch_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT;
|
||||
} else if (cpu_is_omap34xx()) {
|
||||
omap_dma_base = (void __iomem *)IO_ADDRESS(OMAP34XX_DMA4_BASE);
|
||||
omap_dma_base = IO_ADDRESS(OMAP34XX_DMA4_BASE);
|
||||
dma_lch_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT;
|
||||
} else {
|
||||
pr_err("DMA init failed for unsupported omap\n");
|
||||
|
|
|
@ -693,7 +693,7 @@ int __init omap_dm_timer_init(void)
|
|||
|
||||
for (i = 0; i < dm_timer_count; i++) {
|
||||
timer = &dm_timers[i];
|
||||
timer->io_base = (void __iomem *)io_p2v(timer->phys_base);
|
||||
timer->io_base = IO_ADDRESS(timer->phys_base);
|
||||
#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
|
||||
if (cpu_class_is_omap2()) {
|
||||
char clk_name[16];
|
||||
|
|
|
@ -28,7 +28,7 @@
|
|||
/*
|
||||
* OMAP1510 GPIO registers
|
||||
*/
|
||||
#define OMAP1510_GPIO_BASE (void __iomem *)0xfffce000
|
||||
#define OMAP1510_GPIO_BASE IO_ADDRESS(0xfffce000)
|
||||
#define OMAP1510_GPIO_DATA_INPUT 0x00
|
||||
#define OMAP1510_GPIO_DATA_OUTPUT 0x04
|
||||
#define OMAP1510_GPIO_DIR_CONTROL 0x08
|
||||
|
@ -42,10 +42,10 @@
|
|||
/*
|
||||
* OMAP1610 specific GPIO registers
|
||||
*/
|
||||
#define OMAP1610_GPIO1_BASE (void __iomem *)0xfffbe400
|
||||
#define OMAP1610_GPIO2_BASE (void __iomem *)0xfffbec00
|
||||
#define OMAP1610_GPIO3_BASE (void __iomem *)0xfffbb400
|
||||
#define OMAP1610_GPIO4_BASE (void __iomem *)0xfffbbc00
|
||||
#define OMAP1610_GPIO1_BASE IO_ADDRESS(0xfffbe400)
|
||||
#define OMAP1610_GPIO2_BASE IO_ADDRESS(0xfffbec00)
|
||||
#define OMAP1610_GPIO3_BASE IO_ADDRESS(0xfffbb400)
|
||||
#define OMAP1610_GPIO4_BASE IO_ADDRESS(0xfffbbc00)
|
||||
#define OMAP1610_GPIO_REVISION 0x0000
|
||||
#define OMAP1610_GPIO_SYSCONFIG 0x0010
|
||||
#define OMAP1610_GPIO_SYSSTATUS 0x0014
|
||||
|
@ -67,12 +67,12 @@
|
|||
/*
|
||||
* OMAP730 specific GPIO registers
|
||||
*/
|
||||
#define OMAP730_GPIO1_BASE (void __iomem *)0xfffbc000
|
||||
#define OMAP730_GPIO2_BASE (void __iomem *)0xfffbc800
|
||||
#define OMAP730_GPIO3_BASE (void __iomem *)0xfffbd000
|
||||
#define OMAP730_GPIO4_BASE (void __iomem *)0xfffbd800
|
||||
#define OMAP730_GPIO5_BASE (void __iomem *)0xfffbe000
|
||||
#define OMAP730_GPIO6_BASE (void __iomem *)0xfffbe800
|
||||
#define OMAP730_GPIO1_BASE IO_ADDRESS(0xfffbc000)
|
||||
#define OMAP730_GPIO2_BASE IO_ADDRESS(0xfffbc800)
|
||||
#define OMAP730_GPIO3_BASE IO_ADDRESS(0xfffbd000)
|
||||
#define OMAP730_GPIO4_BASE IO_ADDRESS(0xfffbd800)
|
||||
#define OMAP730_GPIO5_BASE IO_ADDRESS(0xfffbe000)
|
||||
#define OMAP730_GPIO6_BASE IO_ADDRESS(0xfffbe800)
|
||||
#define OMAP730_GPIO_DATA_INPUT 0x00
|
||||
#define OMAP730_GPIO_DATA_OUTPUT 0x04
|
||||
#define OMAP730_GPIO_DIR_CONTROL 0x08
|
||||
|
@ -83,16 +83,16 @@
|
|||
/*
|
||||
* omap24xx specific GPIO registers
|
||||
*/
|
||||
#define OMAP242X_GPIO1_BASE (void __iomem *)0x48018000
|
||||
#define OMAP242X_GPIO2_BASE (void __iomem *)0x4801a000
|
||||
#define OMAP242X_GPIO3_BASE (void __iomem *)0x4801c000
|
||||
#define OMAP242X_GPIO4_BASE (void __iomem *)0x4801e000
|
||||
#define OMAP242X_GPIO1_BASE IO_ADDRESS(0x48018000)
|
||||
#define OMAP242X_GPIO2_BASE IO_ADDRESS(0x4801a000)
|
||||
#define OMAP242X_GPIO3_BASE IO_ADDRESS(0x4801c000)
|
||||
#define OMAP242X_GPIO4_BASE IO_ADDRESS(0x4801e000)
|
||||
|
||||
#define OMAP243X_GPIO1_BASE (void __iomem *)0x4900C000
|
||||
#define OMAP243X_GPIO2_BASE (void __iomem *)0x4900E000
|
||||
#define OMAP243X_GPIO3_BASE (void __iomem *)0x49010000
|
||||
#define OMAP243X_GPIO4_BASE (void __iomem *)0x49012000
|
||||
#define OMAP243X_GPIO5_BASE (void __iomem *)0x480B6000
|
||||
#define OMAP243X_GPIO1_BASE IO_ADDRESS(0x4900C000)
|
||||
#define OMAP243X_GPIO2_BASE IO_ADDRESS(0x4900E000)
|
||||
#define OMAP243X_GPIO3_BASE IO_ADDRESS(0x49010000)
|
||||
#define OMAP243X_GPIO4_BASE IO_ADDRESS(0x49012000)
|
||||
#define OMAP243X_GPIO5_BASE IO_ADDRESS(0x480B6000)
|
||||
|
||||
#define OMAP24XX_GPIO_REVISION 0x0000
|
||||
#define OMAP24XX_GPIO_SYSCONFIG 0x0010
|
||||
|
@ -122,13 +122,14 @@
|
|||
* omap34xx specific GPIO registers
|
||||
*/
|
||||
|
||||
#define OMAP34XX_GPIO1_BASE (void __iomem *)0x48310000
|
||||
#define OMAP34XX_GPIO2_BASE (void __iomem *)0x49050000
|
||||
#define OMAP34XX_GPIO3_BASE (void __iomem *)0x49052000
|
||||
#define OMAP34XX_GPIO4_BASE (void __iomem *)0x49054000
|
||||
#define OMAP34XX_GPIO5_BASE (void __iomem *)0x49056000
|
||||
#define OMAP34XX_GPIO6_BASE (void __iomem *)0x49058000
|
||||
#define OMAP34XX_GPIO1_BASE IO_ADDRESS(0x48310000)
|
||||
#define OMAP34XX_GPIO2_BASE IO_ADDRESS(0x49050000)
|
||||
#define OMAP34XX_GPIO3_BASE IO_ADDRESS(0x49052000)
|
||||
#define OMAP34XX_GPIO4_BASE IO_ADDRESS(0x49054000)
|
||||
#define OMAP34XX_GPIO5_BASE IO_ADDRESS(0x49056000)
|
||||
#define OMAP34XX_GPIO6_BASE IO_ADDRESS(0x49058000)
|
||||
|
||||
#define OMAP_MPUIO_VBASE IO_ADDRESS(OMAP_MPUIO_BASE)
|
||||
|
||||
struct gpio_bank {
|
||||
void __iomem *base;
|
||||
|
@ -160,7 +161,7 @@ struct gpio_bank {
|
|||
|
||||
#ifdef CONFIG_ARCH_OMAP16XX
|
||||
static struct gpio_bank gpio_bank_1610[5] = {
|
||||
{ OMAP_MPUIO_BASE, INT_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO},
|
||||
{ OMAP_MPUIO_VBASE, INT_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO},
|
||||
{ OMAP1610_GPIO1_BASE, INT_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_1610 },
|
||||
{ OMAP1610_GPIO2_BASE, INT_1610_GPIO_BANK2, IH_GPIO_BASE + 16, METHOD_GPIO_1610 },
|
||||
{ OMAP1610_GPIO3_BASE, INT_1610_GPIO_BANK3, IH_GPIO_BASE + 32, METHOD_GPIO_1610 },
|
||||
|
@ -170,14 +171,14 @@ static struct gpio_bank gpio_bank_1610[5] = {
|
|||
|
||||
#ifdef CONFIG_ARCH_OMAP15XX
|
||||
static struct gpio_bank gpio_bank_1510[2] = {
|
||||
{ OMAP_MPUIO_BASE, INT_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO },
|
||||
{ OMAP_MPUIO_VBASE, INT_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO },
|
||||
{ OMAP1510_GPIO_BASE, INT_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_1510 }
|
||||
};
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_ARCH_OMAP730
|
||||
static struct gpio_bank gpio_bank_730[7] = {
|
||||
{ OMAP_MPUIO_BASE, INT_730_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO },
|
||||
{ OMAP_MPUIO_VBASE, INT_730_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO },
|
||||
{ OMAP730_GPIO1_BASE, INT_730_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_730 },
|
||||
{ OMAP730_GPIO2_BASE, INT_730_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_730 },
|
||||
{ OMAP730_GPIO3_BASE, INT_730_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_730 },
|
||||
|
@ -1389,7 +1390,7 @@ static int __init _omap_gpio_init(void)
|
|||
|
||||
gpio_bank_count = 5;
|
||||
gpio_bank = gpio_bank_1610;
|
||||
rev = omap_readw(gpio_bank[1].base + OMAP1610_GPIO_REVISION);
|
||||
rev = __raw_readw(gpio_bank[1].base + OMAP1610_GPIO_REVISION);
|
||||
printk(KERN_INFO "OMAP GPIO hardware version %d.%d\n",
|
||||
(rev >> 4) & 0x0f, rev & 0x0f);
|
||||
}
|
||||
|
@ -1408,7 +1409,7 @@ static int __init _omap_gpio_init(void)
|
|||
|
||||
gpio_bank_count = 4;
|
||||
gpio_bank = gpio_bank_242x;
|
||||
rev = omap_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
|
||||
rev = __raw_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
|
||||
printk(KERN_INFO "OMAP242x GPIO hardware version %d.%d\n",
|
||||
(rev >> 4) & 0x0f, rev & 0x0f);
|
||||
}
|
||||
|
@ -1417,7 +1418,7 @@ static int __init _omap_gpio_init(void)
|
|||
|
||||
gpio_bank_count = 5;
|
||||
gpio_bank = gpio_bank_243x;
|
||||
rev = omap_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
|
||||
rev = __raw_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
|
||||
printk(KERN_INFO "OMAP243x GPIO hardware version %d.%d\n",
|
||||
(rev >> 4) & 0x0f, rev & 0x0f);
|
||||
}
|
||||
|
@ -1428,7 +1429,7 @@ static int __init _omap_gpio_init(void)
|
|||
|
||||
gpio_bank_count = OMAP34XX_NR_GPIOS;
|
||||
gpio_bank = gpio_bank_34xx;
|
||||
rev = omap_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
|
||||
rev = __raw_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
|
||||
printk(KERN_INFO "OMAP34xx GPIO hardware version %d.%d\n",
|
||||
(rev >> 4) & 0x0f, rev & 0x0f);
|
||||
}
|
||||
|
@ -1437,10 +1438,9 @@ static int __init _omap_gpio_init(void)
|
|||
int j, gpio_count = 16;
|
||||
|
||||
bank = &gpio_bank[i];
|
||||
bank->base = IO_ADDRESS(bank->base);
|
||||
spin_lock_init(&bank->lock);
|
||||
if (bank_is_mpuio(bank))
|
||||
omap_writew(0xFFFF, OMAP_MPUIO_BASE + OMAP_MPUIO_GPIO_MASKIT);
|
||||
__raw_writew(0xffff, bank->base + OMAP_MPUIO_GPIO_MASKIT);
|
||||
if (cpu_is_omap15xx() && bank->method == METHOD_GPIO_1510) {
|
||||
__raw_writew(0xffff, bank->base + OMAP1510_GPIO_INT_MASK);
|
||||
__raw_writew(0x0000, bank->base + OMAP1510_GPIO_INT_STATUS);
|
||||
|
|
|
@ -30,10 +30,12 @@
|
|||
#define __ASM_ARCH_OMAP_2430SDP_H
|
||||
|
||||
/* Placeholder for 2430SDP specific defines */
|
||||
#define OMAP24XX_ETHR_START 0x08000300
|
||||
#define OMAP24XX_ETHR_START 0x08000300
|
||||
#define OMAP24XX_ETHR_GPIO_IRQ 149
|
||||
#define SDP2430_CS0_BASE 0x04000000
|
||||
|
||||
#define TWL4030_IRQNUM INT_24XX_SYS_NIRQ
|
||||
/* Function prototypes */
|
||||
extern void sdp2430_flash_init(void);
|
||||
extern void sdp2430_usb_init(void);
|
||||
|
||||
#endif /* __ASM_ARCH_OMAP_2430SDP_H */
|
||||
|
|
|
@ -31,6 +31,12 @@
|
|||
|
||||
extern void apollon_mmc_init(void);
|
||||
|
||||
static inline int apollon_plus(void)
|
||||
{
|
||||
/* The apollon plus has IDCODE revision 5 */
|
||||
return system_rev & 0xc0;
|
||||
}
|
||||
|
||||
/* Placeholder for APOLLON specific defines */
|
||||
#define APOLLON_ETHR_GPIO_IRQ 74
|
||||
|
||||
|
|
|
@ -1,7 +1,7 @@
|
|||
/*
|
||||
* arch/arm/plat-omap/include/mach/board-h4.h
|
||||
*
|
||||
* Hardware definitions for TI OMAP1610 H4 board.
|
||||
* Hardware definitions for TI OMAP2420 H4 board.
|
||||
*
|
||||
* Initial creation by Dirk Behme <dirk.behme@de.bosch.com>
|
||||
*
|
||||
|
@ -29,6 +29,9 @@
|
|||
#ifndef __ASM_ARCH_OMAP_H4_H
|
||||
#define __ASM_ARCH_OMAP_H4_H
|
||||
|
||||
/* MMC Prototypes */
|
||||
extern void h4_mmc_init(void);
|
||||
|
||||
/* Placeholder for H4 specific defines */
|
||||
#define OMAP24XX_ETHR_GPIO_IRQ 92
|
||||
#endif /* __ASM_ARCH_OMAP_H4_H */
|
||||
|
|
36
arch/arm/plat-omap/include/mach/board-ldp.h
Normal file
36
arch/arm/plat-omap/include/mach/board-ldp.h
Normal file
|
@ -0,0 +1,36 @@
|
|||
/*
|
||||
* arch/arm/plat-omap/include/mach/board-ldp.h
|
||||
*
|
||||
* Hardware definitions for TI OMAP3 LDP.
|
||||
*
|
||||
* Copyright (C) 2008 Texas Instruments Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
|
||||
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
|
||||
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
|
||||
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
|
||||
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 675 Mass Ave, Cambridge, MA 02139, USA.
|
||||
*/
|
||||
|
||||
#ifndef __ASM_ARCH_OMAP_LDP_H
|
||||
#define __ASM_ARCH_OMAP_LDP_H
|
||||
|
||||
extern void twl4030_bci_battery_init(void);
|
||||
|
||||
#define TWL4030_IRQNUM INT_34XX_SYS_NIRQ
|
||||
|
||||
#endif /* __ASM_ARCH_OMAP_LDP_H */
|
33
arch/arm/plat-omap/include/mach/board-omap3beagle.h
Normal file
33
arch/arm/plat-omap/include/mach/board-omap3beagle.h
Normal file
|
@ -0,0 +1,33 @@
|
|||
/*
|
||||
* arch/arm/plat-omap/include/mach/board-omap3beagle.h
|
||||
*
|
||||
* Hardware definitions for TI OMAP3 BEAGLE.
|
||||
*
|
||||
* Initial creation by Syed Mohammed Khasim <khasim@ti.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
|
||||
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
|
||||
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
|
||||
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
|
||||
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 675 Mass Ave, Cambridge, MA 02139, USA.
|
||||
*/
|
||||
|
||||
#ifndef __ASM_ARCH_OMAP3_BEAGLE_H
|
||||
#define __ASM_ARCH_OMAP3_BEAGLE_H
|
||||
|
||||
#endif /* __ASM_ARCH_OMAP3_BEAGLE_H */
|
||||
|
26
arch/arm/plat-omap/include/mach/board-overo.h
Normal file
26
arch/arm/plat-omap/include/mach/board-overo.h
Normal file
|
@ -0,0 +1,26 @@
|
|||
/*
|
||||
* board-overo.h (Gumstix Overo)
|
||||
*
|
||||
* Initial code: Steve Sakoman <steve@sakoman.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 675 Mass Ave, Cambridge, MA 02139, USA.
|
||||
*/
|
||||
|
||||
#ifndef __ASM_ARCH_OVERO_H
|
||||
#define __ASM_ARCH_OVERO_H
|
||||
|
||||
#define OVERO_GPIO_BT_XGATE 15
|
||||
#define OVERO_GPIO_W2W_NRESET 16
|
||||
#define OVERO_GPIO_BT_NRESET 164
|
||||
#define OVERO_GPIO_USBH_CPEN 168
|
||||
#define OVERO_GPIO_USBH_NRESET 183
|
||||
|
||||
#endif /* ____ASM_ARCH_OVERO_H */
|
||||
|
|
@ -45,6 +45,8 @@ struct omap_mmc_conf {
|
|||
unsigned cover:1;
|
||||
/* 4 wire signaling is optional, and is only used for SD/SDIO */
|
||||
unsigned wire4:1;
|
||||
/* use the internal clock */
|
||||
unsigned internal_clock:1;
|
||||
s16 power_pin;
|
||||
s16 switch_pin;
|
||||
s16 wp_pin;
|
||||
|
|
|
@ -15,6 +15,7 @@
|
|||
|
||||
struct module;
|
||||
struct clk;
|
||||
struct clockdomain;
|
||||
|
||||
#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
|
||||
|
||||
|
@ -79,6 +80,8 @@ struct clk {
|
|||
u32 clksel_mask;
|
||||
const struct clksel *clksel;
|
||||
struct dpll_data *dpll_data;
|
||||
const char *clkdm_name;
|
||||
struct clockdomain *clkdm;
|
||||
#else
|
||||
__u8 rate_offset;
|
||||
__u8 src_offset;
|
||||
|
|
106
arch/arm/plat-omap/include/mach/clockdomain.h
Normal file
106
arch/arm/plat-omap/include/mach/clockdomain.h
Normal file
|
@ -0,0 +1,106 @@
|
|||
/*
|
||||
* linux/include/asm-arm/arch-omap/clockdomain.h
|
||||
*
|
||||
* OMAP2/3 clockdomain framework functions
|
||||
*
|
||||
* Copyright (C) 2008 Texas Instruments, Inc.
|
||||
* Copyright (C) 2008 Nokia Corporation
|
||||
*
|
||||
* Written by Paul Walmsley
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef __ASM_ARM_ARCH_OMAP_CLOCKDOMAIN_H
|
||||
#define __ASM_ARM_ARCH_OMAP_CLOCKDOMAIN_H
|
||||
|
||||
#include <mach/powerdomain.h>
|
||||
#include <mach/clock.h>
|
||||
#include <mach/cpu.h>
|
||||
|
||||
/* Clockdomain capability flags */
|
||||
#define CLKDM_CAN_FORCE_SLEEP (1 << 0)
|
||||
#define CLKDM_CAN_FORCE_WAKEUP (1 << 1)
|
||||
#define CLKDM_CAN_ENABLE_AUTO (1 << 2)
|
||||
#define CLKDM_CAN_DISABLE_AUTO (1 << 3)
|
||||
|
||||
#define CLKDM_CAN_HWSUP (CLKDM_CAN_ENABLE_AUTO | CLKDM_CAN_DISABLE_AUTO)
|
||||
#define CLKDM_CAN_SWSUP (CLKDM_CAN_FORCE_SLEEP | CLKDM_CAN_FORCE_WAKEUP)
|
||||
#define CLKDM_CAN_HWSUP_SWSUP (CLKDM_CAN_SWSUP | CLKDM_CAN_HWSUP)
|
||||
|
||||
/* OMAP24XX CM_CLKSTCTRL_*.AUTOSTATE_* register bit values */
|
||||
#define OMAP24XX_CLKSTCTRL_DISABLE_AUTO 0x0
|
||||
#define OMAP24XX_CLKSTCTRL_ENABLE_AUTO 0x1
|
||||
|
||||
/* OMAP3XXX CM_CLKSTCTRL_*.CLKTRCTRL_* register bit values */
|
||||
#define OMAP34XX_CLKSTCTRL_DISABLE_AUTO 0x0
|
||||
#define OMAP34XX_CLKSTCTRL_FORCE_SLEEP 0x1
|
||||
#define OMAP34XX_CLKSTCTRL_FORCE_WAKEUP 0x2
|
||||
#define OMAP34XX_CLKSTCTRL_ENABLE_AUTO 0x3
|
||||
|
||||
/*
|
||||
* struct clkdm_pwrdm_autodep - a powerdomain that should have wkdeps
|
||||
* and sleepdeps added when a powerdomain should stay active in hwsup mode;
|
||||
* and conversely, removed when the powerdomain should be allowed to go
|
||||
* inactive in hwsup mode.
|
||||
*/
|
||||
struct clkdm_pwrdm_autodep {
|
||||
|
||||
/* Name of the powerdomain to add a wkdep/sleepdep on */
|
||||
const char *pwrdm_name;
|
||||
|
||||
/* Powerdomain pointer (looked up at clkdm_init() time) */
|
||||
struct powerdomain *pwrdm;
|
||||
|
||||
/* OMAP chip types that this clockdomain dep is valid on */
|
||||
const struct omap_chip_id omap_chip;
|
||||
|
||||
};
|
||||
|
||||
struct clockdomain {
|
||||
|
||||
/* Clockdomain name */
|
||||
const char *name;
|
||||
|
||||
/* Powerdomain enclosing this clockdomain */
|
||||
const char *pwrdm_name;
|
||||
|
||||
/* CLKTRCTRL/AUTOSTATE field mask in CM_CLKSTCTRL reg */
|
||||
const u16 clktrctrl_mask;
|
||||
|
||||
/* Clockdomain capability flags */
|
||||
const u8 flags;
|
||||
|
||||
/* OMAP chip types that this clockdomain is valid on */
|
||||
const struct omap_chip_id omap_chip;
|
||||
|
||||
/* Usecount tracking */
|
||||
atomic_t usecount;
|
||||
|
||||
/* Powerdomain pointer assigned at clkdm_register() */
|
||||
struct powerdomain *pwrdm;
|
||||
|
||||
struct list_head node;
|
||||
|
||||
};
|
||||
|
||||
void clkdm_init(struct clockdomain **clkdms, struct clkdm_pwrdm_autodep *autodeps);
|
||||
int clkdm_register(struct clockdomain *clkdm);
|
||||
int clkdm_unregister(struct clockdomain *clkdm);
|
||||
struct clockdomain *clkdm_lookup(const char *name);
|
||||
|
||||
int clkdm_for_each(int (*fn)(struct clockdomain *clkdm));
|
||||
struct powerdomain *clkdm_get_pwrdm(struct clockdomain *clkdm);
|
||||
|
||||
void omap2_clkdm_allow_idle(struct clockdomain *clkdm);
|
||||
void omap2_clkdm_deny_idle(struct clockdomain *clkdm);
|
||||
|
||||
int omap2_clkdm_wakeup(struct clockdomain *clkdm);
|
||||
int omap2_clkdm_sleep(struct clockdomain *clkdm);
|
||||
|
||||
int omap2_clkdm_clk_enable(struct clockdomain *clkdm, struct clk *clk);
|
||||
int omap2_clkdm_clk_disable(struct clockdomain *clkdm, struct clk *clk);
|
||||
|
||||
#endif
|
|
@ -34,6 +34,7 @@ struct sys_timer;
|
|||
extern void omap_map_common_io(void);
|
||||
extern struct sys_timer omap_timer;
|
||||
extern void omap_serial_init(void);
|
||||
extern void omap_serial_enable_clocks(int enable);
|
||||
#ifdef CONFIG_I2C_OMAP
|
||||
extern int omap_register_i2c_bus(int bus_id, u32 clkrate,
|
||||
struct i2c_board_info const *info,
|
||||
|
@ -49,6 +50,7 @@ static inline int omap_register_i2c_bus(int bus_id, u32 clkrate,
|
|||
|
||||
/* IO bases for various OMAP processors */
|
||||
struct omap_globals {
|
||||
u32 class; /* OMAP class to detect */
|
||||
void __iomem *tap; /* Control module ID code */
|
||||
void __iomem *sdrc; /* SDRAM Controller */
|
||||
void __iomem *sms; /* SDRAM Memory Scheduler */
|
||||
|
@ -62,6 +64,7 @@ void omap2_set_globals_243x(void);
|
|||
void omap2_set_globals_343x(void);
|
||||
|
||||
/* These get called from omap2_set_globals_xxxx(), do not call these */
|
||||
void omap2_set_globals_tap(struct omap_globals *);
|
||||
void omap2_set_globals_memory(struct omap_globals *);
|
||||
void omap2_set_globals_control(struct omap_globals *);
|
||||
void omap2_set_globals_prcm(struct omap_globals *);
|
||||
|
|
|
@ -1,13 +1,10 @@
|
|||
#ifndef __ASM_ARCH_CONTROL_H
|
||||
#define __ASM_ARCH_CONTROL_H
|
||||
|
||||
/*
|
||||
* arch/arm/plat-omap/include/mach/control.h
|
||||
*
|
||||
* OMAP2/3 System Control Module definitions
|
||||
*
|
||||
* Copyright (C) 2007 Texas Instruments, Inc.
|
||||
* Copyright (C) 2007 Nokia Corporation
|
||||
* Copyright (C) 2007-2008 Texas Instruments, Inc.
|
||||
* Copyright (C) 2007-2008 Nokia Corporation
|
||||
*
|
||||
* Written by Paul Walmsley
|
||||
*
|
||||
|
@ -16,14 +13,23 @@
|
|||
* the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef __ASM_ARCH_CONTROL_H
|
||||
#define __ASM_ARCH_CONTROL_H
|
||||
|
||||
#include <mach/io.h>
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
#define OMAP242X_CTRL_REGADDR(reg) \
|
||||
(void __iomem *)IO_ADDRESS(OMAP242X_CTRL_BASE + (reg))
|
||||
IO_ADDRESS(OMAP242X_CTRL_BASE + (reg))
|
||||
#define OMAP243X_CTRL_REGADDR(reg) \
|
||||
(void __iomem *)IO_ADDRESS(OMAP243X_CTRL_BASE + (reg))
|
||||
IO_ADDRESS(OMAP243X_CTRL_BASE + (reg))
|
||||
#define OMAP343X_CTRL_REGADDR(reg) \
|
||||
(void __iomem *)IO_ADDRESS(OMAP343X_CTRL_BASE + (reg))
|
||||
IO_ADDRESS(OMAP343X_CTRL_BASE + (reg))
|
||||
#else
|
||||
#define OMAP242X_CTRL_REGADDR(reg) IO_ADDRESS(OMAP242X_CTRL_BASE + (reg))
|
||||
#define OMAP243X_CTRL_REGADDR(reg) IO_ADDRESS(OMAP243X_CTRL_BASE + (reg))
|
||||
#define OMAP343X_CTRL_REGADDR(reg) IO_ADDRESS(OMAP343X_CTRL_BASE + (reg))
|
||||
#endif /* __ASSEMBLY__ */
|
||||
|
||||
/*
|
||||
* As elsewhere, the "OMAP2_" prefix indicates that the macro is valid for
|
||||
|
@ -134,6 +140,7 @@
|
|||
#define OMAP343X_CONTROL_TEST_KEY_13 (OMAP2_CONTROL_GENERAL + 0x00fc)
|
||||
#define OMAP343X_CONTROL_IVA2_BOOTADDR (OMAP2_CONTROL_GENERAL + 0x0190)
|
||||
#define OMAP343X_CONTROL_IVA2_BOOTMOD (OMAP2_CONTROL_GENERAL + 0x0194)
|
||||
#define OMAP343X_CONTROL_TEMP_SENSOR (OMAP2_CONTROL_GENERAL + 0x02b4)
|
||||
|
||||
/*
|
||||
* REVISIT: This list of registers is not comprehensive - there are more
|
||||
|
|
|
@ -346,9 +346,14 @@ IS_OMAP_TYPE(3430, 0x3430)
|
|||
get_sil_revision(system_rev)
|
||||
|
||||
/* Various silicon macros defined here */
|
||||
#define OMAP242X_CLASS 0x24200000
|
||||
#define OMAP2420_REV_ES1_0 0x24200000
|
||||
#define OMAP2420_REV_ES2_0 0x24201000
|
||||
|
||||
#define OMAP243X_CLASS 0x24300000
|
||||
#define OMAP2430_REV_ES1_0 0x24300000
|
||||
|
||||
#define OMAP343X_CLASS 0x34300000
|
||||
#define OMAP3430_REV_ES1_0 0x34300000
|
||||
#define OMAP3430_REV_ES2_0 0x34301000
|
||||
#define OMAP3430_REV_ES2_1 0x34302000
|
||||
|
|
|
@ -35,6 +35,18 @@
|
|||
#ifdef CONFIG_OMAP_LL_DEBUG_UART3
|
||||
add \rx, \rx, #0x00004000 @ UART 3
|
||||
#endif
|
||||
|
||||
#elif CONFIG_ARCH_OMAP3
|
||||
moveq \rx, #0x48000000 @ physical base address
|
||||
movne \rx, #0xd8000000 @ virtual base
|
||||
orr \rx, \rx, #0x0006a000
|
||||
#ifdef CONFIG_OMAP_LL_DEBUG_UART2
|
||||
add \rx, \rx, #0x00002000 @ UART 2
|
||||
#endif
|
||||
#ifdef CONFIG_OMAP_LL_DEBUG_UART3
|
||||
add \rx, \rx, #0x00fb0000 @ UART 3
|
||||
add \rx, \rx, #0x00006000
|
||||
#endif
|
||||
#endif
|
||||
.endm
|
||||
|
||||
|
|
|
@ -55,9 +55,17 @@
|
|||
1510:
|
||||
.endm
|
||||
|
||||
#elif defined(CONFIG_ARCH_OMAP24XX)
|
||||
#endif
|
||||
#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
|
||||
|
||||
#if defined(CONFIG_ARCH_OMAP24XX)
|
||||
#include <mach/omap24xx.h>
|
||||
#endif
|
||||
#if defined(CONFIG_ARCH_OMAP34XX)
|
||||
#include <mach/omap34xx.h>
|
||||
#endif
|
||||
|
||||
#define INTCPS_SIR_IRQ_OFFSET 0x0040 /* Active interrupt number */
|
||||
|
||||
.macro disable_fiq
|
||||
.endm
|
||||
|
@ -79,7 +87,7 @@
|
|||
ldr \irqnr, [\base, #0xd8] /* IRQ pending reg 3 */
|
||||
cmp \irqnr, #0x0
|
||||
2222:
|
||||
ldrne \irqnr, [\base, #IRQ_SIR_IRQ]
|
||||
ldrne \irqnr, [\base, #INTCPS_SIR_IRQ_OFFSET]
|
||||
|
||||
.endm
|
||||
|
||||
|
|
|
@ -34,9 +34,9 @@ extern void omap1510_fpga_init_irq(void);
|
|||
* ---------------------------------------------------------------------------
|
||||
*/
|
||||
/* maps in the FPGA registers and the ETHR registers */
|
||||
#define H2P2_DBG_FPGA_BASE 0xE8000000 /* VA */
|
||||
#define H2P2_DBG_FPGA_SIZE SZ_4K /* SIZE */
|
||||
#define H2P2_DBG_FPGA_START 0x04000000 /* PA */
|
||||
#define H2P2_DBG_FPGA_BASE IOMEM(0xE8000000) /* VA */
|
||||
#define H2P2_DBG_FPGA_SIZE SZ_4K /* SIZE */
|
||||
#define H2P2_DBG_FPGA_START 0x04000000 /* PA */
|
||||
|
||||
#define H2P2_DBG_FPGA_ETHR_START (H2P2_DBG_FPGA_START + 0x300)
|
||||
#define H2P2_DBG_FPGA_FPGA_REV (H2P2_DBG_FPGA_BASE + 0x10) /* FPGA Revision */
|
||||
|
@ -85,9 +85,9 @@ struct h2p2_dbg_fpga {
|
|||
* OMAP-1510 FPGA
|
||||
* ---------------------------------------------------------------------------
|
||||
*/
|
||||
#define OMAP1510_FPGA_BASE 0xE8000000 /* Virtual */
|
||||
#define OMAP1510_FPGA_SIZE SZ_4K
|
||||
#define OMAP1510_FPGA_START 0x08000000 /* Physical */
|
||||
#define OMAP1510_FPGA_BASE IOMEM(0xE8000000) /* VA */
|
||||
#define OMAP1510_FPGA_SIZE SZ_4K
|
||||
#define OMAP1510_FPGA_START 0x08000000 /* PA */
|
||||
|
||||
/* Revision */
|
||||
#define OMAP1510_FPGA_REV_LOW (OMAP1510_FPGA_BASE + 0x0)
|
||||
|
|
|
@ -29,7 +29,7 @@
|
|||
#include <linux/io.h>
|
||||
#include <mach/irqs.h>
|
||||
|
||||
#define OMAP_MPUIO_BASE (void __iomem *)0xfffb5000
|
||||
#define OMAP_MPUIO_BASE 0xfffb5000
|
||||
|
||||
#ifdef CONFIG_ARCH_OMAP730
|
||||
#define OMAP_MPUIO_INPUT_LATCH 0x00
|
||||
|
@ -76,6 +76,8 @@ extern void omap_free_gpio(int gpio);
|
|||
extern void omap_set_gpio_direction(int gpio, int is_input);
|
||||
extern void omap_set_gpio_dataout(int gpio, int enable);
|
||||
extern int omap_get_gpio_datain(int gpio);
|
||||
extern void omap2_gpio_prepare_for_retention(void);
|
||||
extern void omap2_gpio_resume_after_retention(void);
|
||||
extern void omap_set_gpio_debounce(int gpio, int enable);
|
||||
extern void omap_set_gpio_debounce_time(int gpio, int enable);
|
||||
|
||||
|
|
|
@ -11,6 +11,9 @@
|
|||
#ifndef __OMAP2_GPMC_H
|
||||
#define __OMAP2_GPMC_H
|
||||
|
||||
/* Maximum Number of Chip Selects */
|
||||
#define GPMC_CS_NUM 8
|
||||
|
||||
#define GPMC_CS_CONFIG1 0x00
|
||||
#define GPMC_CS_CONFIG2 0x04
|
||||
#define GPMC_CS_CONFIG3 0x08
|
||||
|
@ -22,6 +25,9 @@
|
|||
#define GPMC_CS_NAND_ADDRESS 0x20
|
||||
#define GPMC_CS_NAND_DATA 0x24
|
||||
|
||||
#define GPMC_CONFIG 0x50
|
||||
#define GPMC_STATUS 0x54
|
||||
|
||||
#define GPMC_CONFIG1_WRAPBURST_SUPP (1 << 31)
|
||||
#define GPMC_CONFIG1_READMULTIPLE_SUPP (1 << 30)
|
||||
#define GPMC_CONFIG1_READTYPE_ASYNC (0 << 29)
|
||||
|
@ -78,9 +84,14 @@ struct gpmc_timings {
|
|||
u16 access; /* Start-cycle to first data valid delay */
|
||||
u16 rd_cycle; /* Total read cycle time */
|
||||
u16 wr_cycle; /* Total write cycle time */
|
||||
|
||||
/* The following are only on OMAP3430 */
|
||||
u16 wr_access; /* WRACCESSTIME */
|
||||
u16 wr_data_mux_bus; /* WRDATAONADMUXBUS */
|
||||
};
|
||||
|
||||
extern unsigned int gpmc_ns_to_ticks(unsigned int time_ns);
|
||||
extern unsigned int gpmc_ticks_to_ns(unsigned int ticks);
|
||||
extern unsigned int gpmc_round_ns_to_ticks(unsigned int time_ns);
|
||||
extern unsigned long gpmc_get_fclk_period(void);
|
||||
|
||||
|
@ -92,5 +103,6 @@ extern int gpmc_cs_request(int cs, unsigned long size, unsigned long *base);
|
|||
extern void gpmc_cs_free(int cs);
|
||||
extern int gpmc_cs_set_reserved(int cs, int reserved);
|
||||
extern int gpmc_cs_reserved(int cs);
|
||||
extern void gpmc_init(void);
|
||||
|
||||
#endif
|
||||
|
|
|
@ -89,7 +89,7 @@
|
|||
#define DPLL_CTL (0xfffecf00)
|
||||
|
||||
/* DSP clock control. Must use __raw_readw() and __raw_writew() with these */
|
||||
#define DSP_CONFIG_REG_BASE (0xe1008000)
|
||||
#define DSP_CONFIG_REG_BASE IOMEM(0xe1008000)
|
||||
#define DSP_CKCTL (DSP_CONFIG_REG_BASE + 0x0)
|
||||
#define DSP_IDLECT1 (DSP_CONFIG_REG_BASE + 0x4)
|
||||
#define DSP_IDLECT2 (DSP_CONFIG_REG_BASE + 0x8)
|
||||
|
@ -282,8 +282,8 @@
|
|||
|
||||
#include "omap730.h"
|
||||
#include "omap1510.h"
|
||||
#include "omap24xx.h"
|
||||
#include "omap16xx.h"
|
||||
#include "omap24xx.h"
|
||||
#include "omap34xx.h"
|
||||
|
||||
#ifndef __ASSEMBLER__
|
||||
|
@ -322,6 +322,14 @@
|
|||
#include "board-2430sdp.h"
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_MACH_OMAP3_BEAGLE
|
||||
#include "board-omap3beagle.h"
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_MACH_OMAP_LDP
|
||||
#include "board-ldp.h"
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_MACH_OMAP_APOLLON
|
||||
#include "board-apollon.h"
|
||||
#endif
|
||||
|
|
|
@ -55,14 +55,13 @@
|
|||
|
||||
#if defined(CONFIG_ARCH_OMAP1)
|
||||
|
||||
#define IO_PHYS 0xFFFB0000
|
||||
#define IO_OFFSET 0x01000000 /* Virtual IO = 0xfefb0000 */
|
||||
#define IO_SIZE 0x40000
|
||||
#define IO_VIRT (IO_PHYS - IO_OFFSET)
|
||||
#define IO_ADDRESS(pa) ((pa) - IO_OFFSET)
|
||||
#define OMAP1_IO_ADDRESS(pa) ((pa) - IO_OFFSET)
|
||||
#define io_p2v(pa) ((pa) - IO_OFFSET)
|
||||
#define io_v2p(va) ((va) + IO_OFFSET)
|
||||
#define IO_PHYS 0xFFFB0000
|
||||
#define IO_OFFSET 0x01000000 /* Virtual IO = 0xfefb0000 */
|
||||
#define IO_SIZE 0x40000
|
||||
#define IO_VIRT (IO_PHYS - IO_OFFSET)
|
||||
#define __IO_ADDRESS(pa) ((pa) - IO_OFFSET)
|
||||
#define __OMAP1_IO_ADDRESS(pa) ((pa) - IO_OFFSET)
|
||||
#define io_v2p(va) ((va) + IO_OFFSET)
|
||||
|
||||
#elif defined(CONFIG_ARCH_OMAP2)
|
||||
|
||||
|
@ -74,7 +73,6 @@
|
|||
#define L4_24XX_VIRT 0xd8000000
|
||||
#define L4_24XX_SIZE SZ_1M /* 1MB of 128MB used, want 1MB sect */
|
||||
|
||||
#ifdef CONFIG_ARCH_OMAP2430
|
||||
#define L4_WK_243X_PHYS L4_WK_243X_BASE /* 0x49000000 */
|
||||
#define L4_WK_243X_VIRT 0xd9000000
|
||||
#define L4_WK_243X_SIZE SZ_1M
|
||||
|
@ -88,13 +86,10 @@
|
|||
#define OMAP243X_SMS_VIRT 0xFC000000
|
||||
#define OMAP243X_SMS_SIZE SZ_1M
|
||||
|
||||
#endif
|
||||
|
||||
#define IO_OFFSET 0x90000000
|
||||
#define IO_ADDRESS(pa) ((pa) + IO_OFFSET) /* Works for L3 and L4 */
|
||||
#define OMAP2_IO_ADDRESS(pa) ((pa) + IO_OFFSET) /* Works for L3 and L4 */
|
||||
#define io_p2v(pa) ((pa) + IO_OFFSET) /* Works for L3 and L4 */
|
||||
#define io_v2p(va) ((va) - IO_OFFSET) /* Works for L3 and L4 */
|
||||
#define IO_OFFSET 0x90000000
|
||||
#define __IO_ADDRESS(pa) ((pa) + IO_OFFSET) /* Works for L3 and L4 */
|
||||
#define __OMAP2_IO_ADDRESS(pa) ((pa) + IO_OFFSET) /* Works for L3 and L4 */
|
||||
#define io_v2p(va) ((va) - IO_OFFSET) /* Works for L3 and L4 */
|
||||
|
||||
/* DSP */
|
||||
#define DSP_MEM_24XX_PHYS OMAP2420_DSP_MEM_BASE /* 0x58000000 */
|
||||
|
@ -149,9 +144,8 @@
|
|||
|
||||
|
||||
#define IO_OFFSET 0x90000000
|
||||
#define IO_ADDRESS(pa) ((pa) + IO_OFFSET)/* Works for L3 and L4 */
|
||||
#define OMAP2_IO_ADDRESS(pa) ((pa) + IO_OFFSET)/* Works for L3 and L4 */
|
||||
#define io_p2v(pa) ((pa) + IO_OFFSET)/* Works for L3 and L4 */
|
||||
#define __IO_ADDRESS(pa) ((pa) + IO_OFFSET)/* Works for L3 and L4 */
|
||||
#define __OMAP2_IO_ADDRESS(pa) ((pa) + IO_OFFSET)/* Works for L3 and L4 */
|
||||
#define io_v2p(va) ((va) - IO_OFFSET)/* Works for L3 and L4 */
|
||||
|
||||
/* DSP */
|
||||
|
@ -167,7 +161,14 @@
|
|||
|
||||
#endif
|
||||
|
||||
#ifndef __ASSEMBLER__
|
||||
#define IO_ADDRESS(pa) IOMEM(__IO_ADDRESS(pa))
|
||||
#define OMAP1_IO_ADDRESS(pa) IOMEM(__OMAP1_IO_ADDRESS(pa))
|
||||
#define OMAP2_IO_ADDRESS(pa) IOMEM(__OMAP2_IO_ADDRESS(pa))
|
||||
|
||||
#ifdef __ASSEMBLER__
|
||||
#define IOMEM(x) x
|
||||
#else
|
||||
#define IOMEM(x) ((void __force __iomem *)(x))
|
||||
|
||||
/*
|
||||
* Functions to access the OMAP IO region
|
||||
|
@ -178,13 +179,13 @@
|
|||
* - DO NOT use hardcoded virtual addresses to allow changing the
|
||||
* IO address space again if needed
|
||||
*/
|
||||
#define omap_readb(a) (*(volatile unsigned char *)IO_ADDRESS(a))
|
||||
#define omap_readw(a) (*(volatile unsigned short *)IO_ADDRESS(a))
|
||||
#define omap_readl(a) (*(volatile unsigned int *)IO_ADDRESS(a))
|
||||
#define omap_readb(a) __raw_readb(IO_ADDRESS(a))
|
||||
#define omap_readw(a) __raw_readw(IO_ADDRESS(a))
|
||||
#define omap_readl(a) __raw_readl(IO_ADDRESS(a))
|
||||
|
||||
#define omap_writeb(v,a) (*(volatile unsigned char *)IO_ADDRESS(a) = (v))
|
||||
#define omap_writew(v,a) (*(volatile unsigned short *)IO_ADDRESS(a) = (v))
|
||||
#define omap_writel(v,a) (*(volatile unsigned int *)IO_ADDRESS(a) = (v))
|
||||
#define omap_writeb(v,a) __raw_writeb(v, IO_ADDRESS(a))
|
||||
#define omap_writew(v,a) __raw_writew(v, IO_ADDRESS(a))
|
||||
#define omap_writel(v,a) __raw_writel(v, IO_ADDRESS(a))
|
||||
|
||||
extern void omap1_map_common_io(void);
|
||||
extern void omap1_init_common_hw(void);
|
||||
|
@ -192,6 +193,12 @@ extern void omap1_init_common_hw(void);
|
|||
extern void omap2_map_common_io(void);
|
||||
extern void omap2_init_common_hw(void);
|
||||
|
||||
#define __arch_ioremap(p,s,t) omap_ioremap(p,s,t)
|
||||
#define __arch_iounmap(v) omap_iounmap(v)
|
||||
|
||||
void __iomem *omap_ioremap(unsigned long phys, size_t size, unsigned int type);
|
||||
void omap_iounmap(volatile void __iomem *addr);
|
||||
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
|
@ -125,6 +125,7 @@
|
|||
#define INT_UART2 (15 + IH2_BASE)
|
||||
#define INT_BT_MCSI1TX (16 + IH2_BASE)
|
||||
#define INT_BT_MCSI1RX (17 + IH2_BASE)
|
||||
#define INT_SOSSI_MATCH (19 + IH2_BASE)
|
||||
#define INT_USB_W2FC (20 + IH2_BASE)
|
||||
#define INT_1WIRE (21 + IH2_BASE)
|
||||
#define INT_OS_TIMER (22 + IH2_BASE)
|
||||
|
@ -176,6 +177,7 @@
|
|||
#define INT_1610_DMA_CH14 (61 + IH2_BASE)
|
||||
#define INT_1610_DMA_CH15 (62 + IH2_BASE)
|
||||
#define INT_1610_NAND (63 + IH2_BASE)
|
||||
#define INT_1610_SHA1MD5 (91 + IH2_BASE)
|
||||
|
||||
/*
|
||||
* OMAP-730 specific IRQ numbers for interrupt handler 2
|
||||
|
@ -263,12 +265,18 @@
|
|||
#define INT_24XX_GPTIMER10 46
|
||||
#define INT_24XX_GPTIMER11 47
|
||||
#define INT_24XX_GPTIMER12 48
|
||||
#define INT_24XX_SHA1MD5 51
|
||||
#define INT_24XX_MCBSP4_IRQ_TX 54
|
||||
#define INT_24XX_MCBSP4_IRQ_RX 55
|
||||
#define INT_24XX_I2C1_IRQ 56
|
||||
#define INT_24XX_I2C2_IRQ 57
|
||||
#define INT_24XX_HDQ_IRQ 58
|
||||
#define INT_24XX_MCBSP1_IRQ_TX 59
|
||||
#define INT_24XX_MCBSP1_IRQ_RX 60
|
||||
#define INT_24XX_MCBSP2_IRQ_TX 62
|
||||
#define INT_24XX_MCBSP2_IRQ_RX 63
|
||||
#define INT_24XX_SPI1_IRQ 65
|
||||
#define INT_24XX_SPI2_IRQ 66
|
||||
#define INT_24XX_UART1_IRQ 72
|
||||
#define INT_24XX_UART2_IRQ 73
|
||||
#define INT_24XX_UART3_IRQ 74
|
||||
|
@ -278,7 +286,58 @@
|
|||
#define INT_24XX_USB_IRQ_HGEN 78
|
||||
#define INT_24XX_USB_IRQ_HSOF 79
|
||||
#define INT_24XX_USB_IRQ_OTG 80
|
||||
#define INT_24XX_MCBSP5_IRQ_TX 81
|
||||
#define INT_24XX_MCBSP5_IRQ_RX 82
|
||||
#define INT_24XX_MMC_IRQ 83
|
||||
#define INT_24XX_MMC2_IRQ 86
|
||||
#define INT_24XX_MCBSP3_IRQ_TX 89
|
||||
#define INT_24XX_MCBSP3_IRQ_RX 90
|
||||
#define INT_24XX_SPI3_IRQ 91
|
||||
|
||||
#define INT_243X_MCBSP2_IRQ 16
|
||||
#define INT_243X_MCBSP3_IRQ 17
|
||||
#define INT_243X_MCBSP4_IRQ 18
|
||||
#define INT_243X_MCBSP5_IRQ 19
|
||||
#define INT_243X_MCBSP1_IRQ 64
|
||||
#define INT_243X_HS_USB_MC 92
|
||||
#define INT_243X_HS_USB_DMA 93
|
||||
#define INT_243X_CARKIT_IRQ 94
|
||||
|
||||
#define INT_34XX_BENCH_MPU_EMUL 3
|
||||
#define INT_34XX_ST_MCBSP2_IRQ 4
|
||||
#define INT_34XX_ST_MCBSP3_IRQ 5
|
||||
#define INT_34XX_SSM_ABORT_IRQ 6
|
||||
#define INT_34XX_SYS_NIRQ 7
|
||||
#define INT_34XX_D2D_FW_IRQ 8
|
||||
#define INT_34XX_PRCM_MPU_IRQ 11
|
||||
#define INT_34XX_MCBSP1_IRQ 16
|
||||
#define INT_34XX_MCBSP2_IRQ 17
|
||||
#define INT_34XX_MCBSP3_IRQ 22
|
||||
#define INT_34XX_MCBSP4_IRQ 23
|
||||
#define INT_34XX_CAM_IRQ 24
|
||||
#define INT_34XX_MCBSP5_IRQ 27
|
||||
#define INT_34XX_GPIO_BANK1 29
|
||||
#define INT_34XX_GPIO_BANK2 30
|
||||
#define INT_34XX_GPIO_BANK3 31
|
||||
#define INT_34XX_GPIO_BANK4 32
|
||||
#define INT_34XX_GPIO_BANK5 33
|
||||
#define INT_34XX_GPIO_BANK6 34
|
||||
#define INT_34XX_USIM_IRQ 35
|
||||
#define INT_34XX_WDT3_IRQ 36
|
||||
#define INT_34XX_SPI4_IRQ 48
|
||||
#define INT_34XX_SHA1MD52_IRQ 49
|
||||
#define INT_34XX_FPKA_READY_IRQ 50
|
||||
#define INT_34XX_SHA1MD51_IRQ 51
|
||||
#define INT_34XX_RNG_IRQ 52
|
||||
#define INT_34XX_I2C3_IRQ 61
|
||||
#define INT_34XX_FPKA_ERROR_IRQ 64
|
||||
#define INT_34XX_PBIAS_IRQ 75
|
||||
#define INT_34XX_OHCI_IRQ 76
|
||||
#define INT_34XX_EHCI_IRQ 77
|
||||
#define INT_34XX_TLL_IRQ 78
|
||||
#define INT_34XX_PARTHASH_IRQ 79
|
||||
#define INT_34XX_MMC3_IRQ 94
|
||||
#define INT_34XX_GPT12_IRQ 95
|
||||
|
||||
#define INT_34XX_BENCH_MPU_EMUL 3
|
||||
|
||||
|
|
|
@ -43,9 +43,15 @@
|
|||
|
||||
#define OMAP24XX_MCBSP1_BASE 0x48074000
|
||||
#define OMAP24XX_MCBSP2_BASE 0x48076000
|
||||
#define OMAP2430_MCBSP3_BASE 0x4808c000
|
||||
#define OMAP2430_MCBSP4_BASE 0x4808e000
|
||||
#define OMAP2430_MCBSP5_BASE 0x48096000
|
||||
|
||||
#define OMAP34XX_MCBSP1_BASE 0x48074000
|
||||
#define OMAP34XX_MCBSP2_BASE 0x49022000
|
||||
#define OMAP34XX_MCBSP3_BASE 0x49024000
|
||||
#define OMAP34XX_MCBSP4_BASE 0x49026000
|
||||
#define OMAP34XX_MCBSP5_BASE 0x48096000
|
||||
|
||||
#if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP730)
|
||||
|
||||
|
@ -81,9 +87,6 @@
|
|||
#define OMAP_MCBSP_REG_XCERG 0x3A
|
||||
#define OMAP_MCBSP_REG_XCERH 0x3C
|
||||
|
||||
#define OMAP_MAX_MCBSP_COUNT 3
|
||||
#define MAX_MCBSP_CLOCKS 3
|
||||
|
||||
#define AUDIO_MCBSP_DATAWRITE (OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DXR1)
|
||||
#define AUDIO_MCBSP_DATAREAD (OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DRR1)
|
||||
|
||||
|
@ -91,12 +94,14 @@
|
|||
#define AUDIO_DMA_TX OMAP_DMA_MCBSP1_TX
|
||||
#define AUDIO_DMA_RX OMAP_DMA_MCBSP1_RX
|
||||
|
||||
#elif defined(CONFIG_ARCH_OMAP24XX)
|
||||
#elif defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
|
||||
|
||||
#define OMAP_MCBSP_REG_DRR2 0x00
|
||||
#define OMAP_MCBSP_REG_DRR1 0x04
|
||||
#define OMAP_MCBSP_REG_DXR2 0x08
|
||||
#define OMAP_MCBSP_REG_DXR1 0x0C
|
||||
#define OMAP_MCBSP_REG_DRR 0x00
|
||||
#define OMAP_MCBSP_REG_DXR 0x08
|
||||
#define OMAP_MCBSP_REG_SPCR2 0x10
|
||||
#define OMAP_MCBSP_REG_SPCR1 0x14
|
||||
#define OMAP_MCBSP_REG_RCR2 0x18
|
||||
|
@ -124,9 +129,9 @@
|
|||
#define OMAP_MCBSP_REG_RCERH 0x70
|
||||
#define OMAP_MCBSP_REG_XCERG 0x74
|
||||
#define OMAP_MCBSP_REG_XCERH 0x78
|
||||
|
||||
#define OMAP_MAX_MCBSP_COUNT 2
|
||||
#define MAX_MCBSP_CLOCKS 2
|
||||
#define OMAP_MCBSP_REG_SYSCON 0x8C
|
||||
#define OMAP_MCBSP_REG_XCCR 0xAC
|
||||
#define OMAP_MCBSP_REG_RCCR 0xB0
|
||||
|
||||
#define AUDIO_MCBSP_DATAWRITE (OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR1)
|
||||
#define AUDIO_MCBSP_DATAREAD (OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR1)
|
||||
|
@ -137,10 +142,6 @@
|
|||
|
||||
#endif
|
||||
|
||||
#define OMAP_MCBSP_READ(base, reg) __raw_readw((base) + OMAP_MCBSP_REG_##reg)
|
||||
#define OMAP_MCBSP_WRITE(base, reg, val) __raw_writew((val), (base) + OMAP_MCBSP_REG_##reg)
|
||||
|
||||
|
||||
/************************** McBSP SPCR1 bit definitions ***********************/
|
||||
#define RRST 0x0001
|
||||
#define RRDY 0x0002
|
||||
|
@ -151,6 +152,7 @@
|
|||
#define DXENA 0x0080
|
||||
#define CLKSTP(value) ((value)<<11) /* bits 11:12 */
|
||||
#define RJUST(value) ((value)<<13) /* bits 13:14 */
|
||||
#define ALB 0x8000
|
||||
#define DLB 0x8000
|
||||
|
||||
/************************** McBSP SPCR2 bit definitions ***********************/
|
||||
|
@ -228,6 +230,17 @@
|
|||
#define XPABLK(value) ((value)<<5) /* Bits 5:6 */
|
||||
#define XPBBLK(value) ((value)<<7) /* Bits 7:8 */
|
||||
|
||||
/*********************** McBSP XCCR bit definitions *************************/
|
||||
#define DILB 0x0020
|
||||
#define XDMAEN 0x0008
|
||||
#define XDISABLE 0x0001
|
||||
|
||||
/********************** McBSP RCCR bit definitions *************************/
|
||||
#define RDMAEN 0x0008
|
||||
#define RDISABLE 0x0001
|
||||
|
||||
/********************** McBSP SYSCONFIG bit definitions ********************/
|
||||
#define SOFTRST 0x0002
|
||||
|
||||
/* we don't do multichannel for now */
|
||||
struct omap_mcbsp_reg_cfg {
|
||||
|
@ -260,6 +273,8 @@ typedef enum {
|
|||
OMAP_MCBSP1 = 0,
|
||||
OMAP_MCBSP2,
|
||||
OMAP_MCBSP3,
|
||||
OMAP_MCBSP4,
|
||||
OMAP_MCBSP5
|
||||
} omap_mcbsp_id;
|
||||
|
||||
typedef int __bitwise omap_mcbsp_io_type_t;
|
||||
|
@ -311,12 +326,10 @@ struct omap_mcbsp_spi_cfg {
|
|||
struct omap_mcbsp_ops {
|
||||
void (*request)(unsigned int);
|
||||
void (*free)(unsigned int);
|
||||
int (*check)(unsigned int);
|
||||
};
|
||||
|
||||
struct omap_mcbsp_platform_data {
|
||||
unsigned long phys_base;
|
||||
u32 virt_base;
|
||||
u8 dma_rx_sync, dma_tx_sync;
|
||||
u16 rx_irq, tx_irq;
|
||||
struct omap_mcbsp_ops *ops;
|
||||
|
@ -326,7 +339,7 @@ struct omap_mcbsp_platform_data {
|
|||
struct omap_mcbsp {
|
||||
struct device *dev;
|
||||
unsigned long phys_base;
|
||||
u32 io_base;
|
||||
void __iomem *io_base;
|
||||
u8 id;
|
||||
u8 free;
|
||||
omap_mcbsp_word_length rx_word_length;
|
||||
|
@ -354,6 +367,8 @@ struct omap_mcbsp {
|
|||
struct omap_mcbsp_platform_data *pdata;
|
||||
struct clk *clk;
|
||||
};
|
||||
extern struct omap_mcbsp **mcbsp_ptr;
|
||||
extern int omap_mcbsp_count;
|
||||
|
||||
int omap_mcbsp_init(void);
|
||||
void omap_mcbsp_register_board_cfg(struct omap_mcbsp_platform_data *config,
|
||||
|
@ -378,5 +393,6 @@ void omap_mcbsp_set_spi_mode(unsigned int id, const struct omap_mcbsp_spi_cfg *
|
|||
/* Polled read/write functions */
|
||||
int omap_mcbsp_pollread(unsigned int id, u16 * buf);
|
||||
int omap_mcbsp_pollwrite(unsigned int id, u16 buf);
|
||||
int omap_mcbsp_set_io_type(unsigned int id, omap_mcbsp_io_type_t io_type);
|
||||
|
||||
#endif
|
||||
|
|
|
@ -38,7 +38,7 @@
|
|||
*/
|
||||
#if defined(CONFIG_ARCH_OMAP1)
|
||||
#define PHYS_OFFSET UL(0x10000000)
|
||||
#elif defined(CONFIG_ARCH_OMAP2)
|
||||
#elif defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
|
||||
#define PHYS_OFFSET UL(0x80000000)
|
||||
#endif
|
||||
|
||||
|
|
|
@ -125,20 +125,64 @@
|
|||
.pu_pd_val = pull_mode, \
|
||||
},
|
||||
|
||||
/* 24xx/34xx mux bit defines */
|
||||
#define OMAP2_PULL_ENA (1 << 3)
|
||||
#define OMAP2_PULL_UP (1 << 4)
|
||||
#define OMAP2_ALTELECTRICALSEL (1 << 5)
|
||||
|
||||
#define PULL_DISABLED 0
|
||||
#define PULL_ENABLED 1
|
||||
/* 34xx specific mux bit defines */
|
||||
#define OMAP3_INPUT_EN (1 << 8)
|
||||
#define OMAP3_OFF_EN (1 << 9)
|
||||
#define OMAP3_OFFOUT_EN (1 << 10)
|
||||
#define OMAP3_OFFOUT_VAL (1 << 11)
|
||||
#define OMAP3_OFF_PULL_EN (1 << 12)
|
||||
#define OMAP3_OFF_PULL_UP (1 << 13)
|
||||
#define OMAP3_WAKEUP_EN (1 << 14)
|
||||
|
||||
#define PULL_DOWN 0
|
||||
#define PULL_UP 1
|
||||
/* 34xx mux mode options for each pin. See TRM for options */
|
||||
#define OMAP34XX_MUX_MODE0 0
|
||||
#define OMAP34XX_MUX_MODE1 1
|
||||
#define OMAP34XX_MUX_MODE2 2
|
||||
#define OMAP34XX_MUX_MODE3 3
|
||||
#define OMAP34XX_MUX_MODE4 4
|
||||
#define OMAP34XX_MUX_MODE5 5
|
||||
#define OMAP34XX_MUX_MODE6 6
|
||||
#define OMAP34XX_MUX_MODE7 7
|
||||
|
||||
/* 34xx active pin states */
|
||||
#define OMAP34XX_PIN_OUTPUT 0
|
||||
#define OMAP34XX_PIN_INPUT OMAP3_INPUT_EN
|
||||
#define OMAP34XX_PIN_INPUT_PULLUP (OMAP2_PULL_ENA | OMAP3_INPUT_EN \
|
||||
| OMAP2_PULL_UP)
|
||||
#define OMAP34XX_PIN_INPUT_PULLDOWN (OMAP2_PULL_ENA | OMAP3_INPUT_EN)
|
||||
|
||||
/* 34xx off mode states */
|
||||
#define OMAP34XX_PIN_OFF_NONE 0
|
||||
#define OMAP34XX_PIN_OFF_OUTPUT_HIGH (OMAP3_OFF_EN | OMAP3_OFFOUT_EN \
|
||||
| OMAP3_OFFOUT_VAL)
|
||||
#define OMAP34XX_PIN_OFF_OUTPUT_LOW (OMAP3_OFF_EN | OMAP3_OFFOUT_EN)
|
||||
#define OMAP34XX_PIN_OFF_INPUT_PULLUP (OMAP3_OFF_EN | OMAP3_OFF_PULL_EN \
|
||||
| OMAP3_OFF_PULL_UP)
|
||||
#define OMAP34XX_PIN_OFF_INPUT_PULLDOWN (OMAP3_OFF_EN | OMAP3_OFF_PULL_EN)
|
||||
#define OMAP34XX_PIN_OFF_WAKEUPENABLE OMAP3_WAKEUP_EN
|
||||
|
||||
#define MUX_CFG_34XX(desc, reg_offset, mux_value) { \
|
||||
.name = desc, \
|
||||
.debug = 0, \
|
||||
.mux_reg = reg_offset, \
|
||||
.mux_val = mux_value \
|
||||
},
|
||||
|
||||
struct pin_config {
|
||||
char *name;
|
||||
unsigned char busy;
|
||||
unsigned char debug;
|
||||
char *name;
|
||||
const unsigned int mux_reg;
|
||||
unsigned char debug;
|
||||
|
||||
const char *mux_reg_name;
|
||||
const unsigned int mux_reg;
|
||||
#if defined(CONFIG_ARCH_OMAP34XX)
|
||||
u16 mux_val; /* Wake-up, off mode, pull, mux mode */
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_ARCH_OMAP1) || defined(CONFIG_ARCH_OMAP24XX)
|
||||
const unsigned char mask_offset;
|
||||
const unsigned char mask;
|
||||
|
||||
|
@ -150,6 +194,12 @@ struct pin_config {
|
|||
const char *pu_pd_name;
|
||||
const unsigned int pu_pd_reg;
|
||||
const unsigned char pu_pd_val;
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_OMAP_MUX_DEBUG) || defined(CONFIG_OMAP_MUX_WARNINGS)
|
||||
const char *mux_reg_name;
|
||||
#endif
|
||||
|
||||
};
|
||||
|
||||
enum omap730_index {
|
||||
|
@ -593,6 +643,114 @@ enum omap24xx_index {
|
|||
|
||||
};
|
||||
|
||||
enum omap34xx_index {
|
||||
/* 34xx I2C */
|
||||
K21_34XX_I2C1_SCL,
|
||||
J21_34XX_I2C1_SDA,
|
||||
AF15_34XX_I2C2_SCL,
|
||||
AE15_34XX_I2C2_SDA,
|
||||
AF14_34XX_I2C3_SCL,
|
||||
AG14_34XX_I2C3_SDA,
|
||||
AD26_34XX_I2C4_SCL,
|
||||
AE26_34XX_I2C4_SDA,
|
||||
|
||||
/* PHY - HSUSB: 12-pin ULPI PHY: Port 1*/
|
||||
Y8_3430_USB1HS_PHY_CLK,
|
||||
Y9_3430_USB1HS_PHY_STP,
|
||||
AA14_3430_USB1HS_PHY_DIR,
|
||||
AA11_3430_USB1HS_PHY_NXT,
|
||||
W13_3430_USB1HS_PHY_DATA0,
|
||||
W12_3430_USB1HS_PHY_DATA1,
|
||||
W11_3430_USB1HS_PHY_DATA2,
|
||||
Y11_3430_USB1HS_PHY_DATA3,
|
||||
W9_3430_USB1HS_PHY_DATA4,
|
||||
Y12_3430_USB1HS_PHY_DATA5,
|
||||
W8_3430_USB1HS_PHY_DATA6,
|
||||
Y13_3430_USB1HS_PHY_DATA7,
|
||||
|
||||
/* PHY - HSUSB: 12-pin ULPI PHY: Port 2*/
|
||||
AA8_3430_USB2HS_PHY_CLK,
|
||||
AA10_3430_USB2HS_PHY_STP,
|
||||
AA9_3430_USB2HS_PHY_DIR,
|
||||
AB11_3430_USB2HS_PHY_NXT,
|
||||
AB10_3430_USB2HS_PHY_DATA0,
|
||||
AB9_3430_USB2HS_PHY_DATA1,
|
||||
W3_3430_USB2HS_PHY_DATA2,
|
||||
T4_3430_USB2HS_PHY_DATA3,
|
||||
T3_3430_USB2HS_PHY_DATA4,
|
||||
R3_3430_USB2HS_PHY_DATA5,
|
||||
R4_3430_USB2HS_PHY_DATA6,
|
||||
T2_3430_USB2HS_PHY_DATA7,
|
||||
|
||||
|
||||
/* TLL - HSUSB: 12-pin TLL Port 1*/
|
||||
Y8_3430_USB1HS_TLL_CLK,
|
||||
Y9_3430_USB1HS_TLL_STP,
|
||||
AA14_3430_USB1HS_TLL_DIR,
|
||||
AA11_3430_USB1HS_TLL_NXT,
|
||||
W13_3430_USB1HS_TLL_DATA0,
|
||||
W12_3430_USB1HS_TLL_DATA1,
|
||||
W11_3430_USB1HS_TLL_DATA2,
|
||||
Y11_3430_USB1HS_TLL_DATA3,
|
||||
W9_3430_USB1HS_TLL_DATA4,
|
||||
Y12_3430_USB1HS_TLL_DATA5,
|
||||
W8_3430_USB1HS_TLL_DATA6,
|
||||
Y13_3430_USB1HS_TLL_DATA7,
|
||||
|
||||
/* TLL - HSUSB: 12-pin TLL Port 2*/
|
||||
AA8_3430_USB2HS_TLL_CLK,
|
||||
AA10_3430_USB2HS_TLL_STP,
|
||||
AA9_3430_USB2HS_TLL_DIR,
|
||||
AB11_3430_USB2HS_TLL_NXT,
|
||||
AB10_3430_USB2HS_TLL_DATA0,
|
||||
AB9_3430_USB2HS_TLL_DATA1,
|
||||
W3_3430_USB2HS_TLL_DATA2,
|
||||
T4_3430_USB2HS_TLL_DATA3,
|
||||
T3_3430_USB2HS_TLL_DATA4,
|
||||
R3_3430_USB2HS_TLL_DATA5,
|
||||
R4_3430_USB2HS_TLL_DATA6,
|
||||
T2_3430_USB2HS_TLL_DATA7,
|
||||
|
||||
/* TLL - HSUSB: 12-pin TLL Port 3*/
|
||||
AA6_3430_USB3HS_TLL_CLK,
|
||||
AB3_3430_USB3HS_TLL_STP,
|
||||
AA3_3430_USB3HS_TLL_DIR,
|
||||
Y3_3430_USB3HS_TLL_NXT,
|
||||
AA5_3430_USB3HS_TLL_DATA0,
|
||||
Y4_3430_USB3HS_TLL_DATA1,
|
||||
Y5_3430_USB3HS_TLL_DATA2,
|
||||
W5_3430_USB3HS_TLL_DATA3,
|
||||
AB12_3430_USB3HS_TLL_DATA4,
|
||||
AB13_3430_USB3HS_TLL_DATA5,
|
||||
AA13_3430_USB3HS_TLL_DATA6,
|
||||
AA12_3430_USB3HS_TLL_DATA7,
|
||||
|
||||
/* PHY FSUSB: FS Serial for Port 1 (multiple PHY modes supported) */
|
||||
AF10_3430_USB1FS_PHY_MM1_RXDP,
|
||||
AG9_3430_USB1FS_PHY_MM1_RXDM,
|
||||
W13_3430_USB1FS_PHY_MM1_RXRCV,
|
||||
W12_3430_USB1FS_PHY_MM1_TXSE0,
|
||||
W11_3430_USB1FS_PHY_MM1_TXDAT,
|
||||
Y11_3430_USB1FS_PHY_MM1_TXEN_N,
|
||||
|
||||
/* PHY FSUSB: FS Serial for Port 2 (multiple PHY modes supported) */
|
||||
AF7_3430_USB2FS_PHY_MM2_RXDP,
|
||||
AH7_3430_USB2FS_PHY_MM2_RXDM,
|
||||
AB10_3430_USB2FS_PHY_MM2_RXRCV,
|
||||
AB9_3430_USB2FS_PHY_MM2_TXSE0,
|
||||
W3_3430_USB2FS_PHY_MM2_TXDAT,
|
||||
T4_3430_USB2FS_PHY_MM2_TXEN_N,
|
||||
|
||||
/* PHY FSUSB: FS Serial for Port 3 (multiple PHY modes supported) */
|
||||
AH3_3430_USB3FS_PHY_MM3_RXDP,
|
||||
AE3_3430_USB3FS_PHY_MM3_RXDM,
|
||||
AD1_3430_USB3FS_PHY_MM3_RXRCV,
|
||||
AE1_3430_USB3FS_PHY_MM3_TXSE0,
|
||||
AD2_3430_USB3FS_PHY_MM3_TXDAT,
|
||||
AC1_3430_USB3FS_PHY_MM3_TXEN_N,
|
||||
|
||||
};
|
||||
|
||||
struct omap_mux_cfg {
|
||||
struct pin_config *pins;
|
||||
unsigned long size;
|
||||
|
|
|
@ -44,5 +44,7 @@
|
|||
#define OMAP1510_DSPREG_SIZE SZ_128K
|
||||
#define OMAP1510_DSPREG_START 0xE1000000
|
||||
|
||||
#define OMAP1510_DSP_MMU_BASE (0xfffed200)
|
||||
|
||||
#endif /* __ASM_ARCH_OMAP15XX_H */
|
||||
|
||||
|
|
|
@ -44,6 +44,11 @@
|
|||
#define OMAP16XX_DSPREG_SIZE SZ_128K
|
||||
#define OMAP16XX_DSPREG_START 0xE1000000
|
||||
|
||||
#define OMAP16XX_SEC_BASE 0xFFFE4000
|
||||
#define OMAP16XX_SEC_DES (OMAP16XX_SEC_BASE + 0x0000)
|
||||
#define OMAP16XX_SEC_SHA1MD5 (OMAP16XX_SEC_BASE + 0x0800)
|
||||
#define OMAP16XX_SEC_RNG (OMAP16XX_SEC_BASE + 0x1000)
|
||||
|
||||
/*
|
||||
* ---------------------------------------------------------------------------
|
||||
* Interrupts
|
||||
|
@ -190,7 +195,7 @@
|
|||
#define WSPR_DISABLE_0 (0x0000aaaa)
|
||||
#define WSPR_DISABLE_1 (0x00005555)
|
||||
|
||||
/* Mailbox */
|
||||
#define OMAP16XX_DSP_MMU_BASE (0xfffed200)
|
||||
#define OMAP16XX_MAILBOX_BASE (0xfffcf000)
|
||||
|
||||
#endif /* __ASM_ARCH_OMAP16XX_H */
|
||||
|
|
|
@ -39,7 +39,6 @@
|
|||
/* interrupt controller */
|
||||
#define OMAP24XX_IC_BASE (L4_24XX_BASE + 0xfe000)
|
||||
#define OMAP24XX_IVA_INTC_BASE 0x40000000
|
||||
#define IRQ_SIR_IRQ 0x0040
|
||||
|
||||
#define OMAP2420_CTRL_BASE L4_24XX_BASE
|
||||
#define OMAP2420_32KSYNCT_BASE (L4_24XX_BASE + 0x4000)
|
||||
|
@ -48,6 +47,7 @@
|
|||
#define OMAP2420_PRM_BASE OMAP2420_CM_BASE
|
||||
#define OMAP2420_SDRC_BASE (L3_24XX_BASE + 0x9000)
|
||||
#define OMAP2420_SMS_BASE 0x68008000
|
||||
#define OMAP2420_GPMC_BASE 0x6800a000
|
||||
|
||||
#define OMAP2430_32KSYNCT_BASE (L4_WK_243X_BASE + 0x20000)
|
||||
#define OMAP2430_PRCM_BASE (L4_WK_243X_BASE + 0x6000)
|
||||
|
|
|
@ -62,6 +62,7 @@
|
|||
#define OMAPFB_CAPS_WINDOW_PIXEL_DOUBLE 0x00010000
|
||||
#define OMAPFB_CAPS_WINDOW_SCALE 0x00020000
|
||||
#define OMAPFB_CAPS_WINDOW_OVERLAY 0x00040000
|
||||
#define OMAPFB_CAPS_WINDOW_ROTATE 0x00080000
|
||||
#define OMAPFB_CAPS_SET_BACKLIGHT 0x01000000
|
||||
|
||||
/* Values from DSP must map to lower 16-bits */
|
||||
|
@ -305,6 +306,7 @@ struct lcd_ctrl {
|
|||
int screen_width,
|
||||
int pos_x, int pos_y, int width,
|
||||
int height, int color_mode);
|
||||
int (*set_rotate) (int angle);
|
||||
int (*setup_mem) (int plane, size_t size,
|
||||
int mem_type, unsigned long *paddr);
|
||||
int (*mmap) (struct fb_info *info,
|
||||
|
@ -374,6 +376,7 @@ extern struct lcd_ctrl omap1_lcd_ctrl;
|
|||
extern struct lcd_ctrl omap2_disp_ctrl;
|
||||
#endif
|
||||
|
||||
extern void omapfb_reserve_sdram(void);
|
||||
extern void omapfb_register_panel(struct lcd_panel *panel);
|
||||
extern void omapfb_write_first_pixel(struct omapfb_device *fbdev, u16 pixval);
|
||||
extern void omapfb_notify_clients(struct omapfb_device *fbdev,
|
||||
|
|
|
@ -39,11 +39,11 @@
|
|||
* Register and offset definitions to be used in PM assembler code
|
||||
* ----------------------------------------------------------------------------
|
||||
*/
|
||||
#define CLKGEN_REG_ASM_BASE io_p2v(0xfffece00)
|
||||
#define CLKGEN_REG_ASM_BASE IO_ADDRESS(0xfffece00)
|
||||
#define ARM_IDLECT1_ASM_OFFSET 0x04
|
||||
#define ARM_IDLECT2_ASM_OFFSET 0x08
|
||||
|
||||
#define TCMIF_ASM_BASE io_p2v(0xfffecc00)
|
||||
#define TCMIF_ASM_BASE IO_ADDRESS(0xfffecc00)
|
||||
#define EMIFS_CONFIG_ASM_OFFSET 0x0c
|
||||
#define EMIFF_SDRAM_CONFIG_ASM_OFFSET 0x20
|
||||
|
||||
|
@ -135,7 +135,8 @@ extern void omap_pm_suspend(void);
|
|||
extern void omap730_cpu_suspend(unsigned short, unsigned short);
|
||||
extern void omap1510_cpu_suspend(unsigned short, unsigned short);
|
||||
extern void omap1610_cpu_suspend(unsigned short, unsigned short);
|
||||
extern void omap24xx_cpu_suspend(u32 dll_ctrl, u32 cpu_revision);
|
||||
extern void omap24xx_cpu_suspend(u32 dll_ctrl, void __iomem *sdrc_dlla_ctrl,
|
||||
void __iomem *sdrc_power);
|
||||
extern void omap730_idle_loop_suspend(void);
|
||||
extern void omap1510_idle_loop_suspend(void);
|
||||
extern void omap1610_idle_loop_suspend(void);
|
||||
|
|
166
arch/arm/plat-omap/include/mach/powerdomain.h
Normal file
166
arch/arm/plat-omap/include/mach/powerdomain.h
Normal file
|
@ -0,0 +1,166 @@
|
|||
/*
|
||||
* OMAP2/3 powerdomain control
|
||||
*
|
||||
* Copyright (C) 2007-8 Texas Instruments, Inc.
|
||||
* Copyright (C) 2007-8 Nokia Corporation
|
||||
*
|
||||
* Written by Paul Walmsley
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef ASM_ARM_ARCH_OMAP_POWERDOMAIN
|
||||
#define ASM_ARM_ARCH_OMAP_POWERDOMAIN
|
||||
|
||||
#include <linux/types.h>
|
||||
#include <linux/list.h>
|
||||
|
||||
#include <asm/atomic.h>
|
||||
|
||||
#include <mach/cpu.h>
|
||||
|
||||
|
||||
/* Powerdomain basic power states */
|
||||
#define PWRDM_POWER_OFF 0x0
|
||||
#define PWRDM_POWER_RET 0x1
|
||||
#define PWRDM_POWER_INACTIVE 0x2
|
||||
#define PWRDM_POWER_ON 0x3
|
||||
|
||||
/* Powerdomain allowable state bitfields */
|
||||
#define PWRSTS_OFF_ON ((1 << PWRDM_POWER_OFF) | \
|
||||
(1 << PWRDM_POWER_ON))
|
||||
|
||||
#define PWRSTS_OFF_RET ((1 << PWRDM_POWER_OFF) | \
|
||||
(1 << PWRDM_POWER_RET))
|
||||
|
||||
#define PWRSTS_OFF_RET_ON (PWRSTS_OFF_RET | (1 << PWRDM_POWER_ON))
|
||||
|
||||
|
||||
/* Powerdomain flags */
|
||||
#define PWRDM_HAS_HDWR_SAR (1 << 0) /* hardware save-and-restore support */
|
||||
|
||||
|
||||
/*
|
||||
* Number of memory banks that are power-controllable. On OMAP3430, the
|
||||
* maximum is 4.
|
||||
*/
|
||||
#define PWRDM_MAX_MEM_BANKS 4
|
||||
|
||||
/*
|
||||
* Maximum number of clockdomains that can be associated with a powerdomain.
|
||||
* CORE powerdomain is probably the worst case.
|
||||
*/
|
||||
#define PWRDM_MAX_CLKDMS 3
|
||||
|
||||
/* XXX A completely arbitrary number. What is reasonable here? */
|
||||
#define PWRDM_TRANSITION_BAILOUT 100000
|
||||
|
||||
struct clockdomain;
|
||||
struct powerdomain;
|
||||
|
||||
/* Encodes dependencies between powerdomains - statically defined */
|
||||
struct pwrdm_dep {
|
||||
|
||||
/* Powerdomain name */
|
||||
const char *pwrdm_name;
|
||||
|
||||
/* Powerdomain pointer - resolved by the powerdomain code */
|
||||
struct powerdomain *pwrdm;
|
||||
|
||||
/* Flags to mark OMAP chip restrictions, etc. */
|
||||
const struct omap_chip_id omap_chip;
|
||||
|
||||
};
|
||||
|
||||
struct powerdomain {
|
||||
|
||||
/* Powerdomain name */
|
||||
const char *name;
|
||||
|
||||
/* the address offset from CM_BASE/PRM_BASE */
|
||||
const s16 prcm_offs;
|
||||
|
||||
/* Used to represent the OMAP chip types containing this pwrdm */
|
||||
const struct omap_chip_id omap_chip;
|
||||
|
||||
/* Bit shift of this powerdomain's PM_WKDEP/CM_SLEEPDEP bit */
|
||||
const u8 dep_bit;
|
||||
|
||||
/* Powerdomains that can be told to wake this powerdomain up */
|
||||
struct pwrdm_dep *wkdep_srcs;
|
||||
|
||||
/* Powerdomains that can be told to keep this pwrdm from inactivity */
|
||||
struct pwrdm_dep *sleepdep_srcs;
|
||||
|
||||
/* Possible powerdomain power states */
|
||||
const u8 pwrsts;
|
||||
|
||||
/* Possible logic power states when pwrdm in RETENTION */
|
||||
const u8 pwrsts_logic_ret;
|
||||
|
||||
/* Powerdomain flags */
|
||||
const u8 flags;
|
||||
|
||||
/* Number of software-controllable memory banks in this powerdomain */
|
||||
const u8 banks;
|
||||
|
||||
/* Possible memory bank pwrstates when pwrdm in RETENTION */
|
||||
const u8 pwrsts_mem_ret[PWRDM_MAX_MEM_BANKS];
|
||||
|
||||
/* Possible memory bank pwrstates when pwrdm is ON */
|
||||
const u8 pwrsts_mem_on[PWRDM_MAX_MEM_BANKS];
|
||||
|
||||
/* Clockdomains in this powerdomain */
|
||||
struct clockdomain *pwrdm_clkdms[PWRDM_MAX_CLKDMS];
|
||||
|
||||
struct list_head node;
|
||||
|
||||
};
|
||||
|
||||
|
||||
void pwrdm_init(struct powerdomain **pwrdm_list);
|
||||
|
||||
int pwrdm_register(struct powerdomain *pwrdm);
|
||||
int pwrdm_unregister(struct powerdomain *pwrdm);
|
||||
struct powerdomain *pwrdm_lookup(const char *name);
|
||||
|
||||
int pwrdm_for_each(int (*fn)(struct powerdomain *pwrdm));
|
||||
|
||||
int pwrdm_add_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm);
|
||||
int pwrdm_del_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm);
|
||||
int pwrdm_for_each_clkdm(struct powerdomain *pwrdm,
|
||||
int (*fn)(struct powerdomain *pwrdm,
|
||||
struct clockdomain *clkdm));
|
||||
|
||||
int pwrdm_add_wkdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2);
|
||||
int pwrdm_del_wkdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2);
|
||||
int pwrdm_read_wkdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2);
|
||||
int pwrdm_add_sleepdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2);
|
||||
int pwrdm_del_sleepdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2);
|
||||
int pwrdm_read_sleepdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2);
|
||||
|
||||
int pwrdm_get_mem_bank_count(struct powerdomain *pwrdm);
|
||||
|
||||
int pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst);
|
||||
int pwrdm_read_next_pwrst(struct powerdomain *pwrdm);
|
||||
int pwrdm_read_prev_pwrst(struct powerdomain *pwrdm);
|
||||
int pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm);
|
||||
|
||||
int pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst);
|
||||
int pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank, u8 pwrst);
|
||||
int pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank, u8 pwrst);
|
||||
|
||||
int pwrdm_read_logic_pwrst(struct powerdomain *pwrdm);
|
||||
int pwrdm_read_prev_logic_pwrst(struct powerdomain *pwrdm);
|
||||
int pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank);
|
||||
int pwrdm_read_prev_mem_pwrst(struct powerdomain *pwrdm, u8 bank);
|
||||
|
||||
int pwrdm_enable_hdwr_sar(struct powerdomain *pwrdm);
|
||||
int pwrdm_disable_hdwr_sar(struct powerdomain *pwrdm);
|
||||
bool pwrdm_has_hdwr_sar(struct powerdomain *pwrdm);
|
||||
|
||||
int pwrdm_wait_transition(struct powerdomain *pwrdm);
|
||||
|
||||
#endif
|
|
@ -25,6 +25,8 @@
|
|||
#define SDRC_DLLB_STATUS 0x06C
|
||||
#define SDRC_POWER 0x070
|
||||
#define SDRC_MR_0 0x084
|
||||
#define SDRC_ACTIM_CTRL_A_0 0x09c
|
||||
#define SDRC_ACTIM_CTRL_B_0 0x0a0
|
||||
#define SDRC_RFR_CTRL_0 0x0a4
|
||||
|
||||
/*
|
||||
|
@ -63,9 +65,9 @@
|
|||
*/
|
||||
|
||||
|
||||
#define OMAP242X_SMS_REGADDR(reg) (void __iomem *)IO_ADDRESS(OMAP2420_SMS_BASE + reg)
|
||||
#define OMAP243X_SMS_REGADDR(reg) (void __iomem *)IO_ADDRESS(OMAP243X_SMS_BASE + reg)
|
||||
#define OMAP343X_SMS_REGADDR(reg) (void __iomem *)IO_ADDRESS(OMAP343X_SMS_BASE + reg)
|
||||
#define OMAP242X_SMS_REGADDR(reg) IO_ADDRESS(OMAP2420_SMS_BASE + reg)
|
||||
#define OMAP243X_SMS_REGADDR(reg) IO_ADDRESS(OMAP243X_SMS_BASE + reg)
|
||||
#define OMAP343X_SMS_REGADDR(reg) IO_ADDRESS(OMAP343X_SMS_BASE + reg)
|
||||
|
||||
/* SMS register offsets - read/write with sms_{read,write}_reg() */
|
||||
|
||||
|
|
|
@ -20,18 +20,24 @@
|
|||
#define OMAP_UART1_BASE 0x4806a000
|
||||
#define OMAP_UART2_BASE 0x4806c000
|
||||
#define OMAP_UART3_BASE 0x4806e000
|
||||
#elif defined(CONFIG_ARCH_OMAP3)
|
||||
/* OMAP3 serial ports */
|
||||
#define OMAP_UART1_BASE 0x4806a000
|
||||
#define OMAP_UART2_BASE 0x4806c000
|
||||
#define OMAP_UART3_BASE 0x49020000
|
||||
#endif
|
||||
|
||||
#define OMAP_MAX_NR_PORTS 3
|
||||
#define OMAP1510_BASE_BAUD (12000000/16)
|
||||
#define OMAP16XX_BASE_BAUD (48000000/16)
|
||||
#define OMAP24XX_BASE_BAUD (48000000/16)
|
||||
|
||||
#define is_omap_port(p) ({int __ret = 0; \
|
||||
if (p == IO_ADDRESS(OMAP_UART1_BASE) || \
|
||||
p == IO_ADDRESS(OMAP_UART2_BASE) || \
|
||||
p == IO_ADDRESS(OMAP_UART3_BASE)) \
|
||||
__ret = 1; \
|
||||
__ret; \
|
||||
#define is_omap_port(pt) ({int __ret = 0; \
|
||||
if ((pt)->port.mapbase == OMAP_UART1_BASE || \
|
||||
(pt)->port.mapbase == OMAP_UART2_BASE || \
|
||||
(pt)->port.mapbase == OMAP_UART3_BASE) \
|
||||
__ret = 1; \
|
||||
__ret; \
|
||||
})
|
||||
|
||||
#endif
|
||||
|
|
|
@ -21,6 +21,10 @@ extern void omap2_sram_reprogram_sdrc(u32 perf_level, u32 dll_val,
|
|||
u32 mem_type);
|
||||
extern u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass);
|
||||
|
||||
extern u32 omap3_configure_core_dpll(u32 sdrc_rfr_ctrl,
|
||||
u32 sdrc_actim_ctrla,
|
||||
u32 sdrc_actim_ctrlb, u32 m2);
|
||||
|
||||
/* Do not use these */
|
||||
extern void omap1_sram_reprogram_clock(u32 ckctl, u32 dpllctl);
|
||||
extern unsigned long omap1_sram_reprogram_clock_sz;
|
||||
|
@ -53,4 +57,10 @@ extern void omap243x_sram_reprogram_sdrc(u32 perf_level, u32 dll_val,
|
|||
u32 mem_type);
|
||||
extern unsigned long omap243x_sram_reprogram_sdrc_sz;
|
||||
|
||||
|
||||
extern u32 omap3_sram_configure_core_dpll(u32 sdrc_rfr_ctrl,
|
||||
u32 sdrc_actim_ctrla,
|
||||
u32 sdrc_actim_ctrlb, u32 m2);
|
||||
extern unsigned long omap3_sram_configure_core_dpll_sz;
|
||||
|
||||
#endif
|
||||
|
|
|
@ -40,7 +40,7 @@ static inline void omap1_arch_reset(char mode)
|
|||
|
||||
static inline void arch_reset(char mode)
|
||||
{
|
||||
if (!cpu_is_omap24xx())
|
||||
if (!cpu_class_is_omap2())
|
||||
omap1_arch_reset(mode);
|
||||
else
|
||||
omap_prcm_arch_reset(mode);
|
||||
|
|
107
arch/arm/plat-omap/io.c
Normal file
107
arch/arm/plat-omap/io.c
Normal file
|
@ -0,0 +1,107 @@
|
|||
#include <linux/module.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/mm.h>
|
||||
|
||||
#include <mach/omap730.h>
|
||||
#include <mach/omap1510.h>
|
||||
#include <mach/omap16xx.h>
|
||||
#include <mach/omap24xx.h>
|
||||
#include <mach/omap34xx.h>
|
||||
|
||||
#define BETWEEN(p,st,sz) ((p) >= (st) && (p) < ((st) + (sz)))
|
||||
#define XLATE(p,pst,vst) ((void __iomem *)((p) - (pst) + (vst)))
|
||||
|
||||
/*
|
||||
* Intercept ioremap() requests for addresses in our fixed mapping regions.
|
||||
*/
|
||||
void __iomem *omap_ioremap(unsigned long p, size_t size, unsigned int type)
|
||||
{
|
||||
#ifdef CONFIG_ARCH_OMAP1
|
||||
if (cpu_class_is_omap1()) {
|
||||
if (BETWEEN(p, IO_PHYS, IO_SIZE))
|
||||
return XLATE(p, IO_PHYS, IO_VIRT);
|
||||
}
|
||||
if (cpu_is_omap730()) {
|
||||
if (BETWEEN(p, OMAP730_DSP_BASE, OMAP730_DSP_SIZE))
|
||||
return XLATE(p, OMAP730_DSP_BASE, OMAP730_DSP_START);
|
||||
|
||||
if (BETWEEN(p, OMAP730_DSPREG_BASE, OMAP730_DSPREG_SIZE))
|
||||
return XLATE(p, OMAP730_DSPREG_BASE,
|
||||
OMAP730_DSPREG_START);
|
||||
}
|
||||
if (cpu_is_omap15xx()) {
|
||||
if (BETWEEN(p, OMAP1510_DSP_BASE, OMAP1510_DSP_SIZE))
|
||||
return XLATE(p, OMAP1510_DSP_BASE, OMAP1510_DSP_START);
|
||||
|
||||
if (BETWEEN(p, OMAP1510_DSPREG_BASE, OMAP1510_DSPREG_SIZE))
|
||||
return XLATE(p, OMAP1510_DSPREG_BASE,
|
||||
OMAP1510_DSPREG_START);
|
||||
}
|
||||
if (cpu_is_omap16xx()) {
|
||||
if (BETWEEN(p, OMAP16XX_DSP_BASE, OMAP16XX_DSP_SIZE))
|
||||
return XLATE(p, OMAP16XX_DSP_BASE, OMAP16XX_DSP_START);
|
||||
|
||||
if (BETWEEN(p, OMAP16XX_DSPREG_BASE, OMAP16XX_DSPREG_SIZE))
|
||||
return XLATE(p, OMAP16XX_DSPREG_BASE,
|
||||
OMAP16XX_DSPREG_START);
|
||||
}
|
||||
#endif
|
||||
#ifdef CONFIG_ARCH_OMAP2
|
||||
if (cpu_is_omap24xx()) {
|
||||
if (BETWEEN(p, L3_24XX_PHYS, L3_24XX_SIZE))
|
||||
return XLATE(p, L3_24XX_PHYS, L3_24XX_VIRT);
|
||||
if (BETWEEN(p, L4_24XX_PHYS, L4_24XX_SIZE))
|
||||
return XLATE(p, L4_24XX_PHYS, L4_24XX_VIRT);
|
||||
}
|
||||
if (cpu_is_omap2420()) {
|
||||
if (BETWEEN(p, DSP_MEM_24XX_PHYS, DSP_MEM_24XX_SIZE))
|
||||
return XLATE(p, DSP_MEM_24XX_PHYS, DSP_MEM_24XX_VIRT);
|
||||
if (BETWEEN(p, DSP_IPI_24XX_PHYS, DSP_IPI_24XX_SIZE))
|
||||
return XLATE(p, DSP_IPI_24XX_PHYS, DSP_IPI_24XX_SIZE);
|
||||
if (BETWEEN(p, DSP_MMU_24XX_PHYS, DSP_MMU_24XX_SIZE))
|
||||
return XLATE(p, DSP_MMU_24XX_PHYS, DSP_MMU_24XX_VIRT);
|
||||
}
|
||||
if (cpu_is_omap2430()) {
|
||||
if (BETWEEN(p, L4_WK_243X_PHYS, L4_WK_243X_SIZE))
|
||||
return XLATE(p, L4_WK_243X_PHYS, L4_WK_243X_VIRT);
|
||||
if (BETWEEN(p, OMAP243X_GPMC_PHYS, OMAP243X_GPMC_SIZE))
|
||||
return XLATE(p, OMAP243X_GPMC_PHYS, OMAP243X_GPMC_VIRT);
|
||||
if (BETWEEN(p, OMAP243X_SDRC_PHYS, OMAP243X_SDRC_SIZE))
|
||||
return XLATE(p, OMAP243X_SDRC_PHYS, OMAP243X_SDRC_VIRT);
|
||||
if (BETWEEN(p, OMAP243X_SMS_PHYS, OMAP243X_SMS_SIZE))
|
||||
return XLATE(p, OMAP243X_SMS_PHYS, OMAP243X_SMS_VIRT);
|
||||
}
|
||||
#endif
|
||||
#ifdef CONFIG_ARCH_OMAP3
|
||||
if (cpu_is_omap34xx()) {
|
||||
if (BETWEEN(p, L3_34XX_PHYS, L3_34XX_SIZE))
|
||||
return XLATE(p, L3_34XX_PHYS, L3_34XX_VIRT);
|
||||
if (BETWEEN(p, L4_34XX_PHYS, L4_34XX_SIZE))
|
||||
return XLATE(p, L4_34XX_PHYS, L4_34XX_VIRT);
|
||||
if (BETWEEN(p, L4_WK_34XX_PHYS, L4_WK_34XX_SIZE))
|
||||
return XLATE(p, L4_WK_34XX_PHYS, L4_WK_34XX_VIRT);
|
||||
if (BETWEEN(p, OMAP34XX_GPMC_PHYS, OMAP34XX_GPMC_SIZE))
|
||||
return XLATE(p, OMAP34XX_GPMC_PHYS, OMAP34XX_GPMC_VIRT);
|
||||
if (BETWEEN(p, OMAP343X_SMS_PHYS, OMAP343X_SMS_SIZE))
|
||||
return XLATE(p, OMAP343X_SMS_PHYS, OMAP343X_SMS_VIRT);
|
||||
if (BETWEEN(p, OMAP343X_SDRC_PHYS, OMAP343X_SDRC_SIZE))
|
||||
return XLATE(p, OMAP343X_SDRC_PHYS, OMAP343X_SDRC_VIRT);
|
||||
if (BETWEEN(p, L4_PER_34XX_PHYS, L4_PER_34XX_SIZE))
|
||||
return XLATE(p, L4_PER_34XX_PHYS, L4_PER_34XX_VIRT);
|
||||
if (BETWEEN(p, L4_EMU_34XX_PHYS, L4_EMU_34XX_SIZE))
|
||||
return XLATE(p, L4_EMU_34XX_PHYS, L4_EMU_34XX_VIRT);
|
||||
}
|
||||
#endif
|
||||
|
||||
return __arm_ioremap(p, size, type);
|
||||
}
|
||||
EXPORT_SYMBOL(omap_ioremap);
|
||||
|
||||
void omap_iounmap(volatile void __iomem *addr)
|
||||
{
|
||||
unsigned long virt = (unsigned long)addr;
|
||||
|
||||
if (virt >= VMALLOC_START && virt < VMALLOC_END)
|
||||
__iounmap(addr);
|
||||
}
|
||||
EXPORT_SYMBOL(omap_iounmap);
|
|
@ -27,43 +27,65 @@
|
|||
#include <mach/dma.h>
|
||||
#include <mach/mcbsp.h>
|
||||
|
||||
static struct omap_mcbsp mcbsp[OMAP_MAX_MCBSP_COUNT];
|
||||
struct omap_mcbsp **mcbsp_ptr;
|
||||
int omap_mcbsp_count;
|
||||
|
||||
#define omap_mcbsp_check_valid_id(id) (mcbsp[id].pdata && \
|
||||
mcbsp[id].pdata->ops && \
|
||||
mcbsp[id].pdata->ops->check && \
|
||||
(mcbsp[id].pdata->ops->check(id) == 0))
|
||||
void omap_mcbsp_write(void __iomem *io_base, u16 reg, u32 val)
|
||||
{
|
||||
if (cpu_class_is_omap1() || cpu_is_omap2420())
|
||||
__raw_writew((u16)val, io_base + reg);
|
||||
else
|
||||
__raw_writel(val, io_base + reg);
|
||||
}
|
||||
|
||||
int omap_mcbsp_read(void __iomem *io_base, u16 reg)
|
||||
{
|
||||
if (cpu_class_is_omap1() || cpu_is_omap2420())
|
||||
return __raw_readw(io_base + reg);
|
||||
else
|
||||
return __raw_readl(io_base + reg);
|
||||
}
|
||||
|
||||
#define OMAP_MCBSP_READ(base, reg) \
|
||||
omap_mcbsp_read(base, OMAP_MCBSP_REG_##reg)
|
||||
#define OMAP_MCBSP_WRITE(base, reg, val) \
|
||||
omap_mcbsp_write(base, OMAP_MCBSP_REG_##reg, val)
|
||||
|
||||
#define omap_mcbsp_check_valid_id(id) (id < omap_mcbsp_count)
|
||||
#define id_to_mcbsp_ptr(id) mcbsp_ptr[id];
|
||||
|
||||
static void omap_mcbsp_dump_reg(u8 id)
|
||||
{
|
||||
dev_dbg(mcbsp[id].dev, "**** McBSP%d regs ****\n", mcbsp[id].id);
|
||||
dev_dbg(mcbsp[id].dev, "DRR2: 0x%04x\n",
|
||||
OMAP_MCBSP_READ(mcbsp[id].io_base, DRR2));
|
||||
dev_dbg(mcbsp[id].dev, "DRR1: 0x%04x\n",
|
||||
OMAP_MCBSP_READ(mcbsp[id].io_base, DRR1));
|
||||
dev_dbg(mcbsp[id].dev, "DXR2: 0x%04x\n",
|
||||
OMAP_MCBSP_READ(mcbsp[id].io_base, DXR2));
|
||||
dev_dbg(mcbsp[id].dev, "DXR1: 0x%04x\n",
|
||||
OMAP_MCBSP_READ(mcbsp[id].io_base, DXR1));
|
||||
dev_dbg(mcbsp[id].dev, "SPCR2: 0x%04x\n",
|
||||
OMAP_MCBSP_READ(mcbsp[id].io_base, SPCR2));
|
||||
dev_dbg(mcbsp[id].dev, "SPCR1: 0x%04x\n",
|
||||
OMAP_MCBSP_READ(mcbsp[id].io_base, SPCR1));
|
||||
dev_dbg(mcbsp[id].dev, "RCR2: 0x%04x\n",
|
||||
OMAP_MCBSP_READ(mcbsp[id].io_base, RCR2));
|
||||
dev_dbg(mcbsp[id].dev, "RCR1: 0x%04x\n",
|
||||
OMAP_MCBSP_READ(mcbsp[id].io_base, RCR1));
|
||||
dev_dbg(mcbsp[id].dev, "XCR2: 0x%04x\n",
|
||||
OMAP_MCBSP_READ(mcbsp[id].io_base, XCR2));
|
||||
dev_dbg(mcbsp[id].dev, "XCR1: 0x%04x\n",
|
||||
OMAP_MCBSP_READ(mcbsp[id].io_base, XCR1));
|
||||
dev_dbg(mcbsp[id].dev, "SRGR2: 0x%04x\n",
|
||||
OMAP_MCBSP_READ(mcbsp[id].io_base, SRGR2));
|
||||
dev_dbg(mcbsp[id].dev, "SRGR1: 0x%04x\n",
|
||||
OMAP_MCBSP_READ(mcbsp[id].io_base, SRGR1));
|
||||
dev_dbg(mcbsp[id].dev, "PCR0: 0x%04x\n",
|
||||
OMAP_MCBSP_READ(mcbsp[id].io_base, PCR0));
|
||||
dev_dbg(mcbsp[id].dev, "***********************\n");
|
||||
struct omap_mcbsp *mcbsp = id_to_mcbsp_ptr(id);
|
||||
|
||||
dev_dbg(mcbsp->dev, "**** McBSP%d regs ****\n", mcbsp->id);
|
||||
dev_dbg(mcbsp->dev, "DRR2: 0x%04x\n",
|
||||
OMAP_MCBSP_READ(mcbsp->io_base, DRR2));
|
||||
dev_dbg(mcbsp->dev, "DRR1: 0x%04x\n",
|
||||
OMAP_MCBSP_READ(mcbsp->io_base, DRR1));
|
||||
dev_dbg(mcbsp->dev, "DXR2: 0x%04x\n",
|
||||
OMAP_MCBSP_READ(mcbsp->io_base, DXR2));
|
||||
dev_dbg(mcbsp->dev, "DXR1: 0x%04x\n",
|
||||
OMAP_MCBSP_READ(mcbsp->io_base, DXR1));
|
||||
dev_dbg(mcbsp->dev, "SPCR2: 0x%04x\n",
|
||||
OMAP_MCBSP_READ(mcbsp->io_base, SPCR2));
|
||||
dev_dbg(mcbsp->dev, "SPCR1: 0x%04x\n",
|
||||
OMAP_MCBSP_READ(mcbsp->io_base, SPCR1));
|
||||
dev_dbg(mcbsp->dev, "RCR2: 0x%04x\n",
|
||||
OMAP_MCBSP_READ(mcbsp->io_base, RCR2));
|
||||
dev_dbg(mcbsp->dev, "RCR1: 0x%04x\n",
|
||||
OMAP_MCBSP_READ(mcbsp->io_base, RCR1));
|
||||
dev_dbg(mcbsp->dev, "XCR2: 0x%04x\n",
|
||||
OMAP_MCBSP_READ(mcbsp->io_base, XCR2));
|
||||
dev_dbg(mcbsp->dev, "XCR1: 0x%04x\n",
|
||||
OMAP_MCBSP_READ(mcbsp->io_base, XCR1));
|
||||
dev_dbg(mcbsp->dev, "SRGR2: 0x%04x\n",
|
||||
OMAP_MCBSP_READ(mcbsp->io_base, SRGR2));
|
||||
dev_dbg(mcbsp->dev, "SRGR1: 0x%04x\n",
|
||||
OMAP_MCBSP_READ(mcbsp->io_base, SRGR1));
|
||||
dev_dbg(mcbsp->dev, "PCR0: 0x%04x\n",
|
||||
OMAP_MCBSP_READ(mcbsp->io_base, PCR0));
|
||||
dev_dbg(mcbsp->dev, "***********************\n");
|
||||
}
|
||||
|
||||
static irqreturn_t omap_mcbsp_tx_irq_handler(int irq, void *dev_id)
|
||||
|
@ -126,16 +148,18 @@ static void omap_mcbsp_rx_dma_callback(int lch, u16 ch_status, void *data)
|
|||
*/
|
||||
void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg *config)
|
||||
{
|
||||
u32 io_base;
|
||||
struct omap_mcbsp *mcbsp;
|
||||
void __iomem *io_base;
|
||||
|
||||
if (!omap_mcbsp_check_valid_id(id)) {
|
||||
printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
|
||||
return;
|
||||
}
|
||||
mcbsp = id_to_mcbsp_ptr(id);
|
||||
|
||||
io_base = mcbsp[id].io_base;
|
||||
dev_dbg(mcbsp[id].dev, "Configuring McBSP%d io_base: 0x%8x\n",
|
||||
mcbsp[id].id, io_base);
|
||||
io_base = mcbsp->io_base;
|
||||
dev_dbg(mcbsp->dev, "Configuring McBSP%d phys_base: 0x%08lx\n",
|
||||
mcbsp->id, mcbsp->phys_base);
|
||||
|
||||
/* We write the given config */
|
||||
OMAP_MCBSP_WRITE(io_base, SPCR2, config->spcr2);
|
||||
|
@ -158,23 +182,26 @@ EXPORT_SYMBOL(omap_mcbsp_config);
|
|||
*/
|
||||
int omap_mcbsp_set_io_type(unsigned int id, omap_mcbsp_io_type_t io_type)
|
||||
{
|
||||
struct omap_mcbsp *mcbsp;
|
||||
|
||||
if (!omap_mcbsp_check_valid_id(id)) {
|
||||
printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
|
||||
return -ENODEV;
|
||||
}
|
||||
mcbsp = id_to_mcbsp_ptr(id);
|
||||
|
||||
spin_lock(&mcbsp[id].lock);
|
||||
spin_lock(&mcbsp->lock);
|
||||
|
||||
if (!mcbsp[id].free) {
|
||||
dev_err(mcbsp[id].dev, "McBSP%d is currently in use\n",
|
||||
mcbsp[id].id);
|
||||
spin_unlock(&mcbsp[id].lock);
|
||||
if (!mcbsp->free) {
|
||||
dev_err(mcbsp->dev, "McBSP%d is currently in use\n",
|
||||
mcbsp->id);
|
||||
spin_unlock(&mcbsp->lock);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
mcbsp[id].io_type = io_type;
|
||||
mcbsp->io_type = io_type;
|
||||
|
||||
spin_unlock(&mcbsp[id].lock);
|
||||
spin_unlock(&mcbsp->lock);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
@ -182,53 +209,60 @@ EXPORT_SYMBOL(omap_mcbsp_set_io_type);
|
|||
|
||||
int omap_mcbsp_request(unsigned int id)
|
||||
{
|
||||
struct omap_mcbsp *mcbsp;
|
||||
int err;
|
||||
|
||||
if (!omap_mcbsp_check_valid_id(id)) {
|
||||
printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
|
||||
return -ENODEV;
|
||||
}
|
||||
mcbsp = id_to_mcbsp_ptr(id);
|
||||
|
||||
if (mcbsp[id].pdata->ops->request)
|
||||
mcbsp[id].pdata->ops->request(id);
|
||||
if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->request)
|
||||
mcbsp->pdata->ops->request(id);
|
||||
|
||||
clk_enable(mcbsp[id].clk);
|
||||
clk_enable(mcbsp->clk);
|
||||
|
||||
spin_lock(&mcbsp[id].lock);
|
||||
if (!mcbsp[id].free) {
|
||||
dev_err(mcbsp[id].dev, "McBSP%d is currently in use\n",
|
||||
mcbsp[id].id);
|
||||
spin_unlock(&mcbsp[id].lock);
|
||||
spin_lock(&mcbsp->lock);
|
||||
if (!mcbsp->free) {
|
||||
dev_err(mcbsp->dev, "McBSP%d is currently in use\n",
|
||||
mcbsp->id);
|
||||
spin_unlock(&mcbsp->lock);
|
||||
return -1;
|
||||
}
|
||||
|
||||
mcbsp[id].free = 0;
|
||||
spin_unlock(&mcbsp[id].lock);
|
||||
mcbsp->free = 0;
|
||||
spin_unlock(&mcbsp->lock);
|
||||
|
||||
if (mcbsp[id].io_type == OMAP_MCBSP_IRQ_IO) {
|
||||
/*
|
||||
* Make sure that transmitter, receiver and sample-rate generator are
|
||||
* not running before activating IRQs.
|
||||
*/
|
||||
OMAP_MCBSP_WRITE(mcbsp->io_base, SPCR1, 0);
|
||||
OMAP_MCBSP_WRITE(mcbsp->io_base, SPCR2, 0);
|
||||
|
||||
if (mcbsp->io_type == OMAP_MCBSP_IRQ_IO) {
|
||||
/* We need to get IRQs here */
|
||||
err = request_irq(mcbsp[id].tx_irq, omap_mcbsp_tx_irq_handler,
|
||||
0, "McBSP", (void *) (&mcbsp[id]));
|
||||
init_completion(&mcbsp->tx_irq_completion);
|
||||
err = request_irq(mcbsp->tx_irq, omap_mcbsp_tx_irq_handler,
|
||||
0, "McBSP", (void *)mcbsp);
|
||||
if (err != 0) {
|
||||
dev_err(mcbsp[id].dev, "Unable to request TX IRQ %d "
|
||||
"for McBSP%d\n", mcbsp[id].tx_irq,
|
||||
mcbsp[id].id);
|
||||
dev_err(mcbsp->dev, "Unable to request TX IRQ %d "
|
||||
"for McBSP%d\n", mcbsp->tx_irq,
|
||||
mcbsp->id);
|
||||
return err;
|
||||
}
|
||||
|
||||
init_completion(&(mcbsp[id].tx_irq_completion));
|
||||
|
||||
err = request_irq(mcbsp[id].rx_irq, omap_mcbsp_rx_irq_handler,
|
||||
0, "McBSP", (void *) (&mcbsp[id]));
|
||||
init_completion(&mcbsp->rx_irq_completion);
|
||||
err = request_irq(mcbsp->rx_irq, omap_mcbsp_rx_irq_handler,
|
||||
0, "McBSP", (void *)mcbsp);
|
||||
if (err != 0) {
|
||||
dev_err(mcbsp[id].dev, "Unable to request RX IRQ %d "
|
||||
"for McBSP%d\n", mcbsp[id].rx_irq,
|
||||
mcbsp[id].id);
|
||||
free_irq(mcbsp[id].tx_irq, (void *) (&mcbsp[id]));
|
||||
dev_err(mcbsp->dev, "Unable to request RX IRQ %d "
|
||||
"for McBSP%d\n", mcbsp->rx_irq,
|
||||
mcbsp->id);
|
||||
free_irq(mcbsp->tx_irq, (void *)mcbsp);
|
||||
return err;
|
||||
}
|
||||
|
||||
init_completion(&(mcbsp[id].rx_irq_completion));
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
@ -237,31 +271,34 @@ EXPORT_SYMBOL(omap_mcbsp_request);
|
|||
|
||||
void omap_mcbsp_free(unsigned int id)
|
||||
{
|
||||
struct omap_mcbsp *mcbsp;
|
||||
|
||||
if (!omap_mcbsp_check_valid_id(id)) {
|
||||
printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
|
||||
return;
|
||||
}
|
||||
mcbsp = id_to_mcbsp_ptr(id);
|
||||
|
||||
if (mcbsp[id].pdata->ops->free)
|
||||
mcbsp[id].pdata->ops->free(id);
|
||||
if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->free)
|
||||
mcbsp->pdata->ops->free(id);
|
||||
|
||||
clk_disable(mcbsp[id].clk);
|
||||
clk_disable(mcbsp->clk);
|
||||
|
||||
spin_lock(&mcbsp[id].lock);
|
||||
if (mcbsp[id].free) {
|
||||
dev_err(mcbsp[id].dev, "McBSP%d was not reserved\n",
|
||||
mcbsp[id].id);
|
||||
spin_unlock(&mcbsp[id].lock);
|
||||
spin_lock(&mcbsp->lock);
|
||||
if (mcbsp->free) {
|
||||
dev_err(mcbsp->dev, "McBSP%d was not reserved\n",
|
||||
mcbsp->id);
|
||||
spin_unlock(&mcbsp->lock);
|
||||
return;
|
||||
}
|
||||
|
||||
mcbsp[id].free = 1;
|
||||
spin_unlock(&mcbsp[id].lock);
|
||||
mcbsp->free = 1;
|
||||
spin_unlock(&mcbsp->lock);
|
||||
|
||||
if (mcbsp[id].io_type == OMAP_MCBSP_IRQ_IO) {
|
||||
if (mcbsp->io_type == OMAP_MCBSP_IRQ_IO) {
|
||||
/* Free IRQs */
|
||||
free_irq(mcbsp[id].rx_irq, (void *) (&mcbsp[id]));
|
||||
free_irq(mcbsp[id].tx_irq, (void *) (&mcbsp[id]));
|
||||
free_irq(mcbsp->rx_irq, (void *)mcbsp);
|
||||
free_irq(mcbsp->tx_irq, (void *)mcbsp);
|
||||
}
|
||||
}
|
||||
EXPORT_SYMBOL(omap_mcbsp_free);
|
||||
|
@ -273,18 +310,19 @@ EXPORT_SYMBOL(omap_mcbsp_free);
|
|||
*/
|
||||
void omap_mcbsp_start(unsigned int id)
|
||||
{
|
||||
u32 io_base;
|
||||
struct omap_mcbsp *mcbsp;
|
||||
void __iomem *io_base;
|
||||
u16 w;
|
||||
|
||||
if (!omap_mcbsp_check_valid_id(id)) {
|
||||
printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
|
||||
return;
|
||||
}
|
||||
mcbsp = id_to_mcbsp_ptr(id);
|
||||
io_base = mcbsp->io_base;
|
||||
|
||||
io_base = mcbsp[id].io_base;
|
||||
|
||||
mcbsp[id].rx_word_length = (OMAP_MCBSP_READ(io_base, RCR1) >> 5) & 0x7;
|
||||
mcbsp[id].tx_word_length = (OMAP_MCBSP_READ(io_base, XCR1) >> 5) & 0x7;
|
||||
mcbsp->rx_word_length = (OMAP_MCBSP_READ(io_base, RCR1) >> 5) & 0x7;
|
||||
mcbsp->tx_word_length = (OMAP_MCBSP_READ(io_base, XCR1) >> 5) & 0x7;
|
||||
|
||||
/* Start the sample generator */
|
||||
w = OMAP_MCBSP_READ(io_base, SPCR2);
|
||||
|
@ -310,7 +348,8 @@ EXPORT_SYMBOL(omap_mcbsp_start);
|
|||
|
||||
void omap_mcbsp_stop(unsigned int id)
|
||||
{
|
||||
u32 io_base;
|
||||
struct omap_mcbsp *mcbsp;
|
||||
void __iomem *io_base;
|
||||
u16 w;
|
||||
|
||||
if (!omap_mcbsp_check_valid_id(id)) {
|
||||
|
@ -318,7 +357,8 @@ void omap_mcbsp_stop(unsigned int id)
|
|||
return;
|
||||
}
|
||||
|
||||
io_base = mcbsp[id].io_base;
|
||||
mcbsp = id_to_mcbsp_ptr(id);
|
||||
io_base = mcbsp->io_base;
|
||||
|
||||
/* Reset transmitter */
|
||||
w = OMAP_MCBSP_READ(io_base, SPCR2);
|
||||
|
@ -337,14 +377,17 @@ EXPORT_SYMBOL(omap_mcbsp_stop);
|
|||
/* polled mcbsp i/o operations */
|
||||
int omap_mcbsp_pollwrite(unsigned int id, u16 buf)
|
||||
{
|
||||
u32 base;
|
||||
struct omap_mcbsp *mcbsp;
|
||||
void __iomem *base;
|
||||
|
||||
if (!omap_mcbsp_check_valid_id(id)) {
|
||||
printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
base = mcbsp[id].io_base;
|
||||
mcbsp = id_to_mcbsp_ptr(id);
|
||||
base = mcbsp->io_base;
|
||||
|
||||
writew(buf, base + OMAP_MCBSP_REG_DXR1);
|
||||
/* if frame sync error - clear the error */
|
||||
if (readw(base + OMAP_MCBSP_REG_SPCR2) & XSYNC_ERR) {
|
||||
|
@ -366,8 +409,8 @@ int omap_mcbsp_pollwrite(unsigned int id, u16 buf)
|
|||
(XRST),
|
||||
base + OMAP_MCBSP_REG_SPCR2);
|
||||
udelay(10);
|
||||
dev_err(mcbsp[id].dev, "Could not write to"
|
||||
" McBSP%d Register\n", mcbsp[id].id);
|
||||
dev_err(mcbsp->dev, "Could not write to"
|
||||
" McBSP%d Register\n", mcbsp->id);
|
||||
return -2;
|
||||
}
|
||||
}
|
||||
|
@ -379,14 +422,16 @@ EXPORT_SYMBOL(omap_mcbsp_pollwrite);
|
|||
|
||||
int omap_mcbsp_pollread(unsigned int id, u16 *buf)
|
||||
{
|
||||
u32 base;
|
||||
struct omap_mcbsp *mcbsp;
|
||||
void __iomem *base;
|
||||
|
||||
if (!omap_mcbsp_check_valid_id(id)) {
|
||||
printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
|
||||
return -ENODEV;
|
||||
}
|
||||
mcbsp = id_to_mcbsp_ptr(id);
|
||||
|
||||
base = mcbsp[id].io_base;
|
||||
base = mcbsp->io_base;
|
||||
/* if frame sync error - clear the error */
|
||||
if (readw(base + OMAP_MCBSP_REG_SPCR1) & RSYNC_ERR) {
|
||||
/* clear error */
|
||||
|
@ -407,8 +452,8 @@ int omap_mcbsp_pollread(unsigned int id, u16 *buf)
|
|||
(RRST),
|
||||
base + OMAP_MCBSP_REG_SPCR1);
|
||||
udelay(10);
|
||||
dev_err(mcbsp[id].dev, "Could not read from"
|
||||
" McBSP%d Register\n", mcbsp[id].id);
|
||||
dev_err(mcbsp->dev, "Could not read from"
|
||||
" McBSP%d Register\n", mcbsp->id);
|
||||
return -2;
|
||||
}
|
||||
}
|
||||
|
@ -424,7 +469,8 @@ EXPORT_SYMBOL(omap_mcbsp_pollread);
|
|||
*/
|
||||
void omap_mcbsp_xmit_word(unsigned int id, u32 word)
|
||||
{
|
||||
u32 io_base;
|
||||
struct omap_mcbsp *mcbsp;
|
||||
void __iomem *io_base;
|
||||
omap_mcbsp_word_length word_length;
|
||||
|
||||
if (!omap_mcbsp_check_valid_id(id)) {
|
||||
|
@ -432,10 +478,11 @@ void omap_mcbsp_xmit_word(unsigned int id, u32 word)
|
|||
return;
|
||||
}
|
||||
|
||||
io_base = mcbsp[id].io_base;
|
||||
word_length = mcbsp[id].tx_word_length;
|
||||
mcbsp = id_to_mcbsp_ptr(id);
|
||||
io_base = mcbsp->io_base;
|
||||
word_length = mcbsp->tx_word_length;
|
||||
|
||||
wait_for_completion(&(mcbsp[id].tx_irq_completion));
|
||||
wait_for_completion(&mcbsp->tx_irq_completion);
|
||||
|
||||
if (word_length > OMAP_MCBSP_WORD_16)
|
||||
OMAP_MCBSP_WRITE(io_base, DXR2, word >> 16);
|
||||
|
@ -445,7 +492,8 @@ EXPORT_SYMBOL(omap_mcbsp_xmit_word);
|
|||
|
||||
u32 omap_mcbsp_recv_word(unsigned int id)
|
||||
{
|
||||
u32 io_base;
|
||||
struct omap_mcbsp *mcbsp;
|
||||
void __iomem *io_base;
|
||||
u16 word_lsb, word_msb = 0;
|
||||
omap_mcbsp_word_length word_length;
|
||||
|
||||
|
@ -453,11 +501,12 @@ u32 omap_mcbsp_recv_word(unsigned int id)
|
|||
printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
|
||||
return -ENODEV;
|
||||
}
|
||||
mcbsp = id_to_mcbsp_ptr(id);
|
||||
|
||||
word_length = mcbsp[id].rx_word_length;
|
||||
io_base = mcbsp[id].io_base;
|
||||
word_length = mcbsp->rx_word_length;
|
||||
io_base = mcbsp->io_base;
|
||||
|
||||
wait_for_completion(&(mcbsp[id].rx_irq_completion));
|
||||
wait_for_completion(&mcbsp->rx_irq_completion);
|
||||
|
||||
if (word_length > OMAP_MCBSP_WORD_16)
|
||||
word_msb = OMAP_MCBSP_READ(io_base, DRR2);
|
||||
|
@ -469,7 +518,8 @@ EXPORT_SYMBOL(omap_mcbsp_recv_word);
|
|||
|
||||
int omap_mcbsp_spi_master_xmit_word_poll(unsigned int id, u32 word)
|
||||
{
|
||||
u32 io_base;
|
||||
struct omap_mcbsp *mcbsp;
|
||||
void __iomem *io_base;
|
||||
omap_mcbsp_word_length tx_word_length;
|
||||
omap_mcbsp_word_length rx_word_length;
|
||||
u16 spcr2, spcr1, attempts = 0, word_lsb, word_msb = 0;
|
||||
|
@ -478,10 +528,10 @@ int omap_mcbsp_spi_master_xmit_word_poll(unsigned int id, u32 word)
|
|||
printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
io_base = mcbsp[id].io_base;
|
||||
tx_word_length = mcbsp[id].tx_word_length;
|
||||
rx_word_length = mcbsp[id].rx_word_length;
|
||||
mcbsp = id_to_mcbsp_ptr(id);
|
||||
io_base = mcbsp->io_base;
|
||||
tx_word_length = mcbsp->tx_word_length;
|
||||
rx_word_length = mcbsp->rx_word_length;
|
||||
|
||||
if (tx_word_length != rx_word_length)
|
||||
return -EINVAL;
|
||||
|
@ -496,8 +546,8 @@ int omap_mcbsp_spi_master_xmit_word_poll(unsigned int id, u32 word)
|
|||
udelay(10);
|
||||
OMAP_MCBSP_WRITE(io_base, SPCR2, spcr2 | XRST);
|
||||
udelay(10);
|
||||
dev_err(mcbsp[id].dev, "McBSP%d transmitter not "
|
||||
"ready\n", mcbsp[id].id);
|
||||
dev_err(mcbsp->dev, "McBSP%d transmitter not "
|
||||
"ready\n", mcbsp->id);
|
||||
return -EAGAIN;
|
||||
}
|
||||
}
|
||||
|
@ -517,8 +567,8 @@ int omap_mcbsp_spi_master_xmit_word_poll(unsigned int id, u32 word)
|
|||
udelay(10);
|
||||
OMAP_MCBSP_WRITE(io_base, SPCR1, spcr1 | RRST);
|
||||
udelay(10);
|
||||
dev_err(mcbsp[id].dev, "McBSP%d receiver not "
|
||||
"ready\n", mcbsp[id].id);
|
||||
dev_err(mcbsp->dev, "McBSP%d receiver not "
|
||||
"ready\n", mcbsp->id);
|
||||
return -EAGAIN;
|
||||
}
|
||||
}
|
||||
|
@ -534,7 +584,9 @@ EXPORT_SYMBOL(omap_mcbsp_spi_master_xmit_word_poll);
|
|||
|
||||
int omap_mcbsp_spi_master_recv_word_poll(unsigned int id, u32 *word)
|
||||
{
|
||||
u32 io_base, clock_word = 0;
|
||||
struct omap_mcbsp *mcbsp;
|
||||
u32 clock_word = 0;
|
||||
void __iomem *io_base;
|
||||
omap_mcbsp_word_length tx_word_length;
|
||||
omap_mcbsp_word_length rx_word_length;
|
||||
u16 spcr2, spcr1, attempts = 0, word_lsb, word_msb = 0;
|
||||
|
@ -544,9 +596,11 @@ int omap_mcbsp_spi_master_recv_word_poll(unsigned int id, u32 *word)
|
|||
return -ENODEV;
|
||||
}
|
||||
|
||||
io_base = mcbsp[id].io_base;
|
||||
tx_word_length = mcbsp[id].tx_word_length;
|
||||
rx_word_length = mcbsp[id].rx_word_length;
|
||||
mcbsp = id_to_mcbsp_ptr(id);
|
||||
io_base = mcbsp->io_base;
|
||||
|
||||
tx_word_length = mcbsp->tx_word_length;
|
||||
rx_word_length = mcbsp->rx_word_length;
|
||||
|
||||
if (tx_word_length != rx_word_length)
|
||||
return -EINVAL;
|
||||
|
@ -561,8 +615,8 @@ int omap_mcbsp_spi_master_recv_word_poll(unsigned int id, u32 *word)
|
|||
udelay(10);
|
||||
OMAP_MCBSP_WRITE(io_base, SPCR2, spcr2 | XRST);
|
||||
udelay(10);
|
||||
dev_err(mcbsp[id].dev, "McBSP%d transmitter not "
|
||||
"ready\n", mcbsp[id].id);
|
||||
dev_err(mcbsp->dev, "McBSP%d transmitter not "
|
||||
"ready\n", mcbsp->id);
|
||||
return -EAGAIN;
|
||||
}
|
||||
}
|
||||
|
@ -582,8 +636,8 @@ int omap_mcbsp_spi_master_recv_word_poll(unsigned int id, u32 *word)
|
|||
udelay(10);
|
||||
OMAP_MCBSP_WRITE(io_base, SPCR1, spcr1 | RRST);
|
||||
udelay(10);
|
||||
dev_err(mcbsp[id].dev, "McBSP%d receiver not "
|
||||
"ready\n", mcbsp[id].id);
|
||||
dev_err(mcbsp->dev, "McBSP%d receiver not "
|
||||
"ready\n", mcbsp->id);
|
||||
return -EAGAIN;
|
||||
}
|
||||
}
|
||||
|
@ -609,6 +663,7 @@ EXPORT_SYMBOL(omap_mcbsp_spi_master_recv_word_poll);
|
|||
int omap_mcbsp_xmit_buffer(unsigned int id, dma_addr_t buffer,
|
||||
unsigned int length)
|
||||
{
|
||||
struct omap_mcbsp *mcbsp;
|
||||
int dma_tx_ch;
|
||||
int src_port = 0;
|
||||
int dest_port = 0;
|
||||
|
@ -618,50 +673,51 @@ int omap_mcbsp_xmit_buffer(unsigned int id, dma_addr_t buffer,
|
|||
printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
|
||||
return -ENODEV;
|
||||
}
|
||||
mcbsp = id_to_mcbsp_ptr(id);
|
||||
|
||||
if (omap_request_dma(mcbsp[id].dma_tx_sync, "McBSP TX",
|
||||
if (omap_request_dma(mcbsp->dma_tx_sync, "McBSP TX",
|
||||
omap_mcbsp_tx_dma_callback,
|
||||
&mcbsp[id],
|
||||
mcbsp,
|
||||
&dma_tx_ch)) {
|
||||
dev_err(mcbsp[id].dev, " Unable to request DMA channel for "
|
||||
dev_err(mcbsp->dev, " Unable to request DMA channel for "
|
||||
"McBSP%d TX. Trying IRQ based TX\n",
|
||||
mcbsp[id].id);
|
||||
mcbsp->id);
|
||||
return -EAGAIN;
|
||||
}
|
||||
mcbsp[id].dma_tx_lch = dma_tx_ch;
|
||||
mcbsp->dma_tx_lch = dma_tx_ch;
|
||||
|
||||
dev_err(mcbsp[id].dev, "McBSP%d TX DMA on channel %d\n", mcbsp[id].id,
|
||||
dev_err(mcbsp->dev, "McBSP%d TX DMA on channel %d\n", mcbsp->id,
|
||||
dma_tx_ch);
|
||||
|
||||
init_completion(&(mcbsp[id].tx_dma_completion));
|
||||
init_completion(&mcbsp->tx_dma_completion);
|
||||
|
||||
if (cpu_class_is_omap1()) {
|
||||
src_port = OMAP_DMA_PORT_TIPB;
|
||||
dest_port = OMAP_DMA_PORT_EMIFF;
|
||||
}
|
||||
if (cpu_class_is_omap2())
|
||||
sync_dev = mcbsp[id].dma_tx_sync;
|
||||
sync_dev = mcbsp->dma_tx_sync;
|
||||
|
||||
omap_set_dma_transfer_params(mcbsp[id].dma_tx_lch,
|
||||
omap_set_dma_transfer_params(mcbsp->dma_tx_lch,
|
||||
OMAP_DMA_DATA_TYPE_S16,
|
||||
length >> 1, 1,
|
||||
OMAP_DMA_SYNC_ELEMENT,
|
||||
sync_dev, 0);
|
||||
|
||||
omap_set_dma_dest_params(mcbsp[id].dma_tx_lch,
|
||||
omap_set_dma_dest_params(mcbsp->dma_tx_lch,
|
||||
src_port,
|
||||
OMAP_DMA_AMODE_CONSTANT,
|
||||
mcbsp[id].phys_base + OMAP_MCBSP_REG_DXR1,
|
||||
mcbsp->phys_base + OMAP_MCBSP_REG_DXR1,
|
||||
0, 0);
|
||||
|
||||
omap_set_dma_src_params(mcbsp[id].dma_tx_lch,
|
||||
omap_set_dma_src_params(mcbsp->dma_tx_lch,
|
||||
dest_port,
|
||||
OMAP_DMA_AMODE_POST_INC,
|
||||
buffer,
|
||||
0, 0);
|
||||
|
||||
omap_start_dma(mcbsp[id].dma_tx_lch);
|
||||
wait_for_completion(&(mcbsp[id].tx_dma_completion));
|
||||
omap_start_dma(mcbsp->dma_tx_lch);
|
||||
wait_for_completion(&mcbsp->tx_dma_completion);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
@ -670,6 +726,7 @@ EXPORT_SYMBOL(omap_mcbsp_xmit_buffer);
|
|||
int omap_mcbsp_recv_buffer(unsigned int id, dma_addr_t buffer,
|
||||
unsigned int length)
|
||||
{
|
||||
struct omap_mcbsp *mcbsp;
|
||||
int dma_rx_ch;
|
||||
int src_port = 0;
|
||||
int dest_port = 0;
|
||||
|
@ -679,50 +736,51 @@ int omap_mcbsp_recv_buffer(unsigned int id, dma_addr_t buffer,
|
|||
printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
|
||||
return -ENODEV;
|
||||
}
|
||||
mcbsp = id_to_mcbsp_ptr(id);
|
||||
|
||||
if (omap_request_dma(mcbsp[id].dma_rx_sync, "McBSP RX",
|
||||
if (omap_request_dma(mcbsp->dma_rx_sync, "McBSP RX",
|
||||
omap_mcbsp_rx_dma_callback,
|
||||
&mcbsp[id],
|
||||
mcbsp,
|
||||
&dma_rx_ch)) {
|
||||
dev_err(mcbsp[id].dev, "Unable to request DMA channel for "
|
||||
dev_err(mcbsp->dev, "Unable to request DMA channel for "
|
||||
"McBSP%d RX. Trying IRQ based RX\n",
|
||||
mcbsp[id].id);
|
||||
mcbsp->id);
|
||||
return -EAGAIN;
|
||||
}
|
||||
mcbsp[id].dma_rx_lch = dma_rx_ch;
|
||||
mcbsp->dma_rx_lch = dma_rx_ch;
|
||||
|
||||
dev_err(mcbsp[id].dev, "McBSP%d RX DMA on channel %d\n", mcbsp[id].id,
|
||||
dev_err(mcbsp->dev, "McBSP%d RX DMA on channel %d\n", mcbsp->id,
|
||||
dma_rx_ch);
|
||||
|
||||
init_completion(&(mcbsp[id].rx_dma_completion));
|
||||
init_completion(&mcbsp->rx_dma_completion);
|
||||
|
||||
if (cpu_class_is_omap1()) {
|
||||
src_port = OMAP_DMA_PORT_TIPB;
|
||||
dest_port = OMAP_DMA_PORT_EMIFF;
|
||||
}
|
||||
if (cpu_class_is_omap2())
|
||||
sync_dev = mcbsp[id].dma_rx_sync;
|
||||
sync_dev = mcbsp->dma_rx_sync;
|
||||
|
||||
omap_set_dma_transfer_params(mcbsp[id].dma_rx_lch,
|
||||
omap_set_dma_transfer_params(mcbsp->dma_rx_lch,
|
||||
OMAP_DMA_DATA_TYPE_S16,
|
||||
length >> 1, 1,
|
||||
OMAP_DMA_SYNC_ELEMENT,
|
||||
sync_dev, 0);
|
||||
|
||||
omap_set_dma_src_params(mcbsp[id].dma_rx_lch,
|
||||
omap_set_dma_src_params(mcbsp->dma_rx_lch,
|
||||
src_port,
|
||||
OMAP_DMA_AMODE_CONSTANT,
|
||||
mcbsp[id].phys_base + OMAP_MCBSP_REG_DRR1,
|
||||
mcbsp->phys_base + OMAP_MCBSP_REG_DRR1,
|
||||
0, 0);
|
||||
|
||||
omap_set_dma_dest_params(mcbsp[id].dma_rx_lch,
|
||||
omap_set_dma_dest_params(mcbsp->dma_rx_lch,
|
||||
dest_port,
|
||||
OMAP_DMA_AMODE_POST_INC,
|
||||
buffer,
|
||||
0, 0);
|
||||
|
||||
omap_start_dma(mcbsp[id].dma_rx_lch);
|
||||
wait_for_completion(&(mcbsp[id].rx_dma_completion));
|
||||
omap_start_dma(mcbsp->dma_rx_lch);
|
||||
wait_for_completion(&mcbsp->rx_dma_completion);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
@ -737,12 +795,14 @@ EXPORT_SYMBOL(omap_mcbsp_recv_buffer);
|
|||
void omap_mcbsp_set_spi_mode(unsigned int id,
|
||||
const struct omap_mcbsp_spi_cfg *spi_cfg)
|
||||
{
|
||||
struct omap_mcbsp *mcbsp;
|
||||
struct omap_mcbsp_reg_cfg mcbsp_cfg;
|
||||
|
||||
if (!omap_mcbsp_check_valid_id(id)) {
|
||||
printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
|
||||
return;
|
||||
}
|
||||
mcbsp = id_to_mcbsp_ptr(id);
|
||||
|
||||
memset(&mcbsp_cfg, 0, sizeof(struct omap_mcbsp_reg_cfg));
|
||||
|
||||
|
@ -803,9 +863,10 @@ EXPORT_SYMBOL(omap_mcbsp_set_spi_mode);
|
|||
* McBSP1 and McBSP3 are directly mapped on 1610 and 1510.
|
||||
* 730 has only 2 McBSP, and both of them are MPU peripherals.
|
||||
*/
|
||||
static int __init omap_mcbsp_probe(struct platform_device *pdev)
|
||||
static int __devinit omap_mcbsp_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct omap_mcbsp_platform_data *pdata = pdev->dev.platform_data;
|
||||
struct omap_mcbsp *mcbsp;
|
||||
int id = pdev->id - 1;
|
||||
int ret = 0;
|
||||
|
||||
|
@ -818,47 +879,63 @@ static int __init omap_mcbsp_probe(struct platform_device *pdev)
|
|||
|
||||
dev_dbg(&pdev->dev, "Initializing OMAP McBSP (%d).\n", pdev->id);
|
||||
|
||||
if (id >= OMAP_MAX_MCBSP_COUNT) {
|
||||
if (id >= omap_mcbsp_count) {
|
||||
dev_err(&pdev->dev, "Invalid McBSP device id (%d)\n", id);
|
||||
ret = -EINVAL;
|
||||
goto exit;
|
||||
}
|
||||
|
||||
spin_lock_init(&mcbsp[id].lock);
|
||||
mcbsp[id].id = id + 1;
|
||||
mcbsp[id].free = 1;
|
||||
mcbsp[id].dma_tx_lch = -1;
|
||||
mcbsp[id].dma_rx_lch = -1;
|
||||
|
||||
mcbsp[id].phys_base = pdata->phys_base;
|
||||
mcbsp[id].io_base = pdata->virt_base;
|
||||
/* Default I/O is IRQ based */
|
||||
mcbsp[id].io_type = OMAP_MCBSP_IRQ_IO;
|
||||
mcbsp[id].tx_irq = pdata->tx_irq;
|
||||
mcbsp[id].rx_irq = pdata->rx_irq;
|
||||
mcbsp[id].dma_rx_sync = pdata->dma_rx_sync;
|
||||
mcbsp[id].dma_tx_sync = pdata->dma_tx_sync;
|
||||
|
||||
if (pdata->clk_name)
|
||||
mcbsp[id].clk = clk_get(&pdev->dev, pdata->clk_name);
|
||||
if (IS_ERR(mcbsp[id].clk)) {
|
||||
mcbsp[id].free = 0;
|
||||
dev_err(&pdev->dev,
|
||||
"Invalid clock configuration for McBSP%d.\n",
|
||||
mcbsp[id].id);
|
||||
ret = -EINVAL;
|
||||
mcbsp = kzalloc(sizeof(struct omap_mcbsp), GFP_KERNEL);
|
||||
if (!mcbsp) {
|
||||
ret = -ENOMEM;
|
||||
goto exit;
|
||||
}
|
||||
mcbsp_ptr[id] = mcbsp;
|
||||
|
||||
mcbsp[id].pdata = pdata;
|
||||
mcbsp[id].dev = &pdev->dev;
|
||||
platform_set_drvdata(pdev, &mcbsp[id]);
|
||||
spin_lock_init(&mcbsp->lock);
|
||||
mcbsp->id = id + 1;
|
||||
mcbsp->free = 1;
|
||||
mcbsp->dma_tx_lch = -1;
|
||||
mcbsp->dma_rx_lch = -1;
|
||||
|
||||
mcbsp->phys_base = pdata->phys_base;
|
||||
mcbsp->io_base = ioremap(pdata->phys_base, SZ_4K);
|
||||
if (!mcbsp->io_base) {
|
||||
ret = -ENOMEM;
|
||||
goto err_ioremap;
|
||||
}
|
||||
|
||||
/* Default I/O is IRQ based */
|
||||
mcbsp->io_type = OMAP_MCBSP_IRQ_IO;
|
||||
mcbsp->tx_irq = pdata->tx_irq;
|
||||
mcbsp->rx_irq = pdata->rx_irq;
|
||||
mcbsp->dma_rx_sync = pdata->dma_rx_sync;
|
||||
mcbsp->dma_tx_sync = pdata->dma_tx_sync;
|
||||
|
||||
if (pdata->clk_name)
|
||||
mcbsp->clk = clk_get(&pdev->dev, pdata->clk_name);
|
||||
if (IS_ERR(mcbsp->clk)) {
|
||||
dev_err(&pdev->dev,
|
||||
"Invalid clock configuration for McBSP%d.\n",
|
||||
mcbsp->id);
|
||||
ret = PTR_ERR(mcbsp->clk);
|
||||
goto err_clk;
|
||||
}
|
||||
|
||||
mcbsp->pdata = pdata;
|
||||
mcbsp->dev = &pdev->dev;
|
||||
platform_set_drvdata(pdev, mcbsp);
|
||||
return 0;
|
||||
|
||||
err_clk:
|
||||
iounmap(mcbsp->io_base);
|
||||
err_ioremap:
|
||||
mcbsp->free = 0;
|
||||
exit:
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int omap_mcbsp_remove(struct platform_device *pdev)
|
||||
static int __devexit omap_mcbsp_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct omap_mcbsp *mcbsp = platform_get_drvdata(pdev);
|
||||
|
||||
|
@ -872,6 +949,8 @@ static int omap_mcbsp_remove(struct platform_device *pdev)
|
|||
clk_disable(mcbsp->clk);
|
||||
clk_put(mcbsp->clk);
|
||||
|
||||
iounmap(mcbsp->io_base);
|
||||
|
||||
mcbsp->clk = NULL;
|
||||
mcbsp->free = 0;
|
||||
mcbsp->dev = NULL;
|
||||
|
@ -882,7 +961,7 @@ static int omap_mcbsp_remove(struct platform_device *pdev)
|
|||
|
||||
static struct platform_driver omap_mcbsp_driver = {
|
||||
.probe = omap_mcbsp_probe,
|
||||
.remove = omap_mcbsp_remove,
|
||||
.remove = __devexit_p(omap_mcbsp_remove),
|
||||
.driver = {
|
||||
.name = "omap-mcbsp",
|
||||
},
|
||||
|
|
|
@ -271,7 +271,7 @@ int __init omap1_sram_init(void)
|
|||
#define omap1_sram_init() do {} while (0)
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
|
||||
#if defined(CONFIG_ARCH_OMAP2)
|
||||
|
||||
static void (*_omap2_sram_ddr_init)(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
|
||||
u32 base_cs, u32 force_unlock);
|
||||
|
@ -352,23 +352,19 @@ static inline int omap243x_sram_init(void)
|
|||
|
||||
#ifdef CONFIG_ARCH_OMAP3
|
||||
|
||||
static u32 (*_omap2_sram_reprogram_gpmc)(u32 perf_level);
|
||||
u32 omap2_sram_reprogram_gpmc(u32 perf_level)
|
||||
static u32 (*_omap3_sram_configure_core_dpll)(u32 sdrc_rfr_ctrl,
|
||||
u32 sdrc_actim_ctrla,
|
||||
u32 sdrc_actim_ctrlb,
|
||||
u32 m2);
|
||||
u32 omap3_configure_core_dpll(u32 sdrc_rfr_ctrl, u32 sdrc_actim_ctrla,
|
||||
u32 sdrc_actim_ctrlb, u32 m2)
|
||||
{
|
||||
if (!_omap2_sram_reprogram_gpmc)
|
||||
if (!_omap3_sram_configure_core_dpll)
|
||||
omap_sram_error();
|
||||
|
||||
return _omap2_sram_reprogram_gpmc(perf_level);
|
||||
}
|
||||
|
||||
static u32 (*_omap2_sram_configure_core_dpll)(u32 m, u32 n,
|
||||
u32 freqsel, u32 m2);
|
||||
u32 omap2_sram_configure_core_dpll(u32 m, u32 n, u32 freqsel, u32 m2)
|
||||
{
|
||||
if (!_omap2_sram_configure_core_dpll)
|
||||
omap_sram_error();
|
||||
|
||||
return _omap2_sram_configure_core_dpll(m, n, freqsel, m2);
|
||||
return _omap3_sram_configure_core_dpll(sdrc_rfr_ctrl,
|
||||
sdrc_actim_ctrla,
|
||||
sdrc_actim_ctrlb, m2);
|
||||
}
|
||||
|
||||
/* REVISIT: Should this be same as omap34xx_sram_init() after off-idle? */
|
||||
|
@ -376,31 +372,16 @@ void restore_sram_functions(void)
|
|||
{
|
||||
omap_sram_ceil = omap_sram_base + omap_sram_size;
|
||||
|
||||
_omap2_sram_reprogram_gpmc = omap_sram_push(omap34xx_sram_reprogram_gpmc,
|
||||
omap34xx_sram_reprogram_gpmc_sz);
|
||||
|
||||
_omap2_sram_configure_core_dpll =
|
||||
omap_sram_push(omap34xx_sram_configure_core_dpll,
|
||||
omap34xx_sram_configure_core_dpll_sz);
|
||||
_omap3_sram_configure_core_dpll =
|
||||
omap_sram_push(omap3_sram_configure_core_dpll,
|
||||
omap3_sram_configure_core_dpll_sz);
|
||||
}
|
||||
|
||||
int __init omap34xx_sram_init(void)
|
||||
{
|
||||
_omap2_sram_ddr_init = omap_sram_push(omap34xx_sram_ddr_init,
|
||||
omap34xx_sram_ddr_init_sz);
|
||||
|
||||
_omap2_sram_reprogram_sdrc = omap_sram_push(omap34xx_sram_reprogram_sdrc,
|
||||
omap34xx_sram_reprogram_sdrc_sz);
|
||||
|
||||
_omap2_set_prcm = omap_sram_push(omap34xx_sram_set_prcm,
|
||||
omap34xx_sram_set_prcm_sz);
|
||||
|
||||
_omap2_sram_reprogram_gpmc = omap_sram_push(omap34xx_sram_reprogram_gpmc,
|
||||
omap34xx_sram_reprogram_gpmc_sz);
|
||||
|
||||
_omap2_sram_configure_core_dpll =
|
||||
omap_sram_push(omap34xx_sram_configure_core_dpll,
|
||||
omap34xx_sram_configure_core_dpll_sz);
|
||||
_omap3_sram_configure_core_dpll =
|
||||
omap_sram_push(omap3_sram_configure_core_dpll,
|
||||
omap3_sram_configure_core_dpll_sz);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
|
@ -118,18 +118,21 @@ static int __init omap_rng_probe(struct platform_device *pdev)
|
|||
|
||||
mem = request_mem_region(res->start, res->end - res->start + 1,
|
||||
pdev->name);
|
||||
if (mem == NULL)
|
||||
return -EBUSY;
|
||||
if (mem == NULL) {
|
||||
ret = -EBUSY;
|
||||
goto err_region;
|
||||
}
|
||||
|
||||
dev_set_drvdata(&pdev->dev, mem);
|
||||
rng_base = (u32 __force __iomem *)io_p2v(res->start);
|
||||
rng_base = ioremap(res->start, res->end - res->start + 1);
|
||||
if (!rng_base) {
|
||||
ret = -ENOMEM;
|
||||
goto err_ioremap;
|
||||
}
|
||||
|
||||
ret = hwrng_register(&omap_rng_ops);
|
||||
if (ret) {
|
||||
release_resource(mem);
|
||||
rng_base = NULL;
|
||||
return ret;
|
||||
}
|
||||
if (ret)
|
||||
goto err_register;
|
||||
|
||||
dev_info(&pdev->dev, "OMAP Random Number Generator ver. %02x\n",
|
||||
omap_rng_read_reg(RNG_REV_REG));
|
||||
|
@ -138,6 +141,18 @@ static int __init omap_rng_probe(struct platform_device *pdev)
|
|||
rng_dev = pdev;
|
||||
|
||||
return 0;
|
||||
|
||||
err_register:
|
||||
iounmap(rng_base);
|
||||
rng_base = NULL;
|
||||
err_ioremap:
|
||||
release_resource(mem);
|
||||
err_region:
|
||||
if (cpu_is_omap24xx()) {
|
||||
clk_disable(rng_ick);
|
||||
clk_put(rng_ick);
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int __exit omap_rng_remove(struct platform_device *pdev)
|
||||
|
@ -148,6 +163,8 @@ static int __exit omap_rng_remove(struct platform_device *pdev)
|
|||
|
||||
omap_rng_write_reg(RNG_MASK_REG, 0x0);
|
||||
|
||||
iounmap(rng_base);
|
||||
|
||||
if (cpu_is_omap24xx()) {
|
||||
clk_disable(rng_ick);
|
||||
clk_put(rng_ick);
|
||||
|
|
|
@ -589,11 +589,16 @@ omap_i2c_probe(struct platform_device *pdev)
|
|||
|
||||
dev->dev = &pdev->dev;
|
||||
dev->irq = irq->start;
|
||||
dev->base = (void __iomem *) IO_ADDRESS(mem->start);
|
||||
dev->base = ioremap(mem->start, mem->end - mem->start + 1);
|
||||
if (!dev->base) {
|
||||
r = -ENOMEM;
|
||||
goto err_free_mem;
|
||||
}
|
||||
|
||||
platform_set_drvdata(pdev, dev);
|
||||
|
||||
if ((r = omap_i2c_get_clocks(dev)) != 0)
|
||||
goto err_free_mem;
|
||||
goto err_iounmap;
|
||||
|
||||
omap_i2c_unidle(dev);
|
||||
|
||||
|
@ -640,6 +645,8 @@ err_unuse_clocks:
|
|||
omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
|
||||
omap_i2c_idle(dev);
|
||||
omap_i2c_put_clocks(dev);
|
||||
err_iounmap:
|
||||
iounmap(dev->base);
|
||||
err_free_mem:
|
||||
platform_set_drvdata(pdev, NULL);
|
||||
kfree(dev);
|
||||
|
@ -661,6 +668,7 @@ omap_i2c_remove(struct platform_device *pdev)
|
|||
i2c_del_adapter(&dev->adapter);
|
||||
omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
|
||||
omap_i2c_put_clocks(dev);
|
||||
iounmap(dev->base);
|
||||
kfree(dev);
|
||||
mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
release_mem_region(mem->start, (mem->end - mem->start) + 1);
|
||||
|
|
|
@ -62,7 +62,7 @@ struct omap_kp {
|
|||
unsigned int debounce;
|
||||
};
|
||||
|
||||
DECLARE_TASKLET_DISABLED(kp_tasklet, omap_kp_tasklet, 0);
|
||||
static DECLARE_TASKLET_DISABLED(kp_tasklet, omap_kp_tasklet, 0);
|
||||
|
||||
static int *keymap;
|
||||
static unsigned int *row_gpios;
|
||||
|
|
|
@ -172,7 +172,7 @@ struct mmc_omap_host {
|
|||
struct omap_mmc_platform_data *pdata;
|
||||
};
|
||||
|
||||
void mmc_omap_fclk_offdelay(struct mmc_omap_slot *slot)
|
||||
static void mmc_omap_fclk_offdelay(struct mmc_omap_slot *slot)
|
||||
{
|
||||
unsigned long tick_ns;
|
||||
|
||||
|
@ -182,7 +182,7 @@ void mmc_omap_fclk_offdelay(struct mmc_omap_slot *slot)
|
|||
}
|
||||
}
|
||||
|
||||
void mmc_omap_fclk_enable(struct mmc_omap_host *host, unsigned int enable)
|
||||
static void mmc_omap_fclk_enable(struct mmc_omap_host *host, unsigned int enable)
|
||||
{
|
||||
unsigned long flags;
|
||||
|
||||
|
@ -1455,7 +1455,9 @@ static int __init mmc_omap_probe(struct platform_device *pdev)
|
|||
|
||||
host->irq = irq;
|
||||
host->phys_base = host->mem_res->start;
|
||||
host->virt_base = (void __iomem *) IO_ADDRESS(host->phys_base);
|
||||
host->virt_base = ioremap(res->start, res->end - res->start + 1);
|
||||
if (!host->virt_base)
|
||||
goto err_ioremap;
|
||||
|
||||
if (cpu_is_omap24xx()) {
|
||||
host->iclk = clk_get(&pdev->dev, "mmc_ick");
|
||||
|
@ -1510,6 +1512,8 @@ err_free_iclk:
|
|||
clk_put(host->iclk);
|
||||
}
|
||||
err_free_mmc_host:
|
||||
iounmap(host->virt_base);
|
||||
err_ioremap:
|
||||
kfree(host);
|
||||
err_free_mem_region:
|
||||
release_mem_region(res->start, res->end - res->start + 1);
|
||||
|
@ -1536,6 +1540,7 @@ static int mmc_omap_remove(struct platform_device *pdev)
|
|||
if (host->fclk && !IS_ERR(host->fclk))
|
||||
clk_put(host->fclk);
|
||||
|
||||
iounmap(host->virt_base);
|
||||
release_mem_region(pdev->resource[0].start,
|
||||
pdev->resource[0].end - pdev->resource[0].start + 1);
|
||||
|
||||
|
|
|
@ -2211,9 +2211,9 @@ serial8250_set_termios(struct uart_port *port, struct ktermios *termios,
|
|||
serial_outp(up, UART_EFR, efr);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_ARCH_OMAP15XX
|
||||
#ifdef CONFIG_ARCH_OMAP
|
||||
/* Workaround to enable 115200 baud on OMAP1510 internal ports */
|
||||
if (cpu_is_omap1510() && is_omap_port((unsigned int)up->port.membase)) {
|
||||
if (cpu_is_omap1510() && is_omap_port(up)) {
|
||||
if (baud == 115200) {
|
||||
quot = 1;
|
||||
serial_out(up, UART_OMAP_OSC_12M_SEL, 1);
|
||||
|
@ -2266,18 +2266,27 @@ serial8250_pm(struct uart_port *port, unsigned int state,
|
|||
p->pm(port, state, oldstate);
|
||||
}
|
||||
|
||||
static unsigned int serial8250_port_size(struct uart_8250_port *pt)
|
||||
{
|
||||
if (pt->port.iotype == UPIO_AU)
|
||||
return 0x100000;
|
||||
#ifdef CONFIG_ARCH_OMAP
|
||||
if (is_omap_port(pt))
|
||||
return 0x16 << pt->port.regshift;
|
||||
#endif
|
||||
return 8 << pt->port.regshift;
|
||||
}
|
||||
|
||||
/*
|
||||
* Resource handling.
|
||||
*/
|
||||
static int serial8250_request_std_resource(struct uart_8250_port *up)
|
||||
{
|
||||
unsigned int size = 8 << up->port.regshift;
|
||||
unsigned int size = serial8250_port_size(up);
|
||||
int ret = 0;
|
||||
|
||||
switch (up->port.iotype) {
|
||||
case UPIO_AU:
|
||||
size = 0x100000;
|
||||
/* fall thru */
|
||||
case UPIO_TSI:
|
||||
case UPIO_MEM32:
|
||||
case UPIO_MEM:
|
||||
|
@ -2311,12 +2320,10 @@ static int serial8250_request_std_resource(struct uart_8250_port *up)
|
|||
|
||||
static void serial8250_release_std_resource(struct uart_8250_port *up)
|
||||
{
|
||||
unsigned int size = 8 << up->port.regshift;
|
||||
unsigned int size = serial8250_port_size(up);
|
||||
|
||||
switch (up->port.iotype) {
|
||||
case UPIO_AU:
|
||||
size = 0x100000;
|
||||
/* fall thru */
|
||||
case UPIO_TSI:
|
||||
case UPIO_MEM32:
|
||||
case UPIO_MEM:
|
||||
|
|
|
@ -119,12 +119,14 @@ struct omap2_mcspi {
|
|||
struct clk *fck;
|
||||
/* Virtual base address of the controller */
|
||||
void __iomem *base;
|
||||
unsigned long phys;
|
||||
/* SPI1 has 4 channels, while SPI2 has 2 */
|
||||
struct omap2_mcspi_dma *dma_channels;
|
||||
};
|
||||
|
||||
struct omap2_mcspi_cs {
|
||||
void __iomem *base;
|
||||
unsigned long phys;
|
||||
int word_len;
|
||||
};
|
||||
|
||||
|
@ -233,7 +235,7 @@ omap2_mcspi_txrx_dma(struct spi_device *spi, struct spi_transfer *xfer)
|
|||
c = count;
|
||||
word_len = cs->word_len;
|
||||
|
||||
base = (unsigned long) io_v2p(cs->base);
|
||||
base = cs->phys;
|
||||
tx_reg = base + OMAP2_MCSPI_TX0;
|
||||
rx_reg = base + OMAP2_MCSPI_RX0;
|
||||
rx = xfer->rx_buf;
|
||||
|
@ -633,6 +635,7 @@ static int omap2_mcspi_setup(struct spi_device *spi)
|
|||
if (!cs)
|
||||
return -ENOMEM;
|
||||
cs->base = mcspi->base + spi->chip_select * 0x14;
|
||||
cs->phys = mcspi->phys + spi->chip_select * 0x14;
|
||||
spi->controller_state = cs;
|
||||
}
|
||||
|
||||
|
@ -1005,7 +1008,13 @@ static int __init omap2_mcspi_probe(struct platform_device *pdev)
|
|||
goto err1;
|
||||
}
|
||||
|
||||
mcspi->base = (void __iomem *) io_p2v(r->start);
|
||||
mcspi->phys = r->start;
|
||||
mcspi->base = ioremap(r->start, r->end - r->start + 1);
|
||||
if (!mcspi->base) {
|
||||
dev_dbg(&pdev->dev, "can't ioremap MCSPI\n");
|
||||
status = -ENOMEM;
|
||||
goto err1aa;
|
||||
}
|
||||
|
||||
INIT_WORK(&mcspi->work, omap2_mcspi_work);
|
||||
|
||||
|
@ -1055,6 +1064,8 @@ err3:
|
|||
err2:
|
||||
clk_put(mcspi->ick);
|
||||
err1a:
|
||||
iounmap(mcspi->base);
|
||||
err1aa:
|
||||
release_mem_region(r->start, (r->end - r->start) + 1);
|
||||
err1:
|
||||
spi_master_put(master);
|
||||
|
@ -1067,6 +1078,7 @@ static int __exit omap2_mcspi_remove(struct platform_device *pdev)
|
|||
struct omap2_mcspi *mcspi;
|
||||
struct omap2_mcspi_dma *dma_channels;
|
||||
struct resource *r;
|
||||
void __iomem *base;
|
||||
|
||||
master = dev_get_drvdata(&pdev->dev);
|
||||
mcspi = spi_master_get_devdata(master);
|
||||
|
@ -1078,7 +1090,9 @@ static int __exit omap2_mcspi_remove(struct platform_device *pdev)
|
|||
r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
release_mem_region(r->start, (r->end - r->start) + 1);
|
||||
|
||||
base = mcspi->base;
|
||||
spi_unregister_master(master);
|
||||
iounmap(base);
|
||||
kfree(dma_channels);
|
||||
|
||||
return 0;
|
||||
|
|
|
@ -59,7 +59,6 @@
|
|||
* and irqs should show there too...
|
||||
*/
|
||||
#define UWIRE_BASE_PHYS 0xFFFB3000
|
||||
#define UWIRE_BASE ((void *__iomem)IO_ADDRESS(UWIRE_BASE_PHYS))
|
||||
|
||||
/* uWire Registers: */
|
||||
#define UWIRE_IO_SIZE 0x20
|
||||
|
@ -103,16 +102,21 @@ struct uwire_state {
|
|||
};
|
||||
|
||||
/* REVISIT compile time constant for idx_shift? */
|
||||
/*
|
||||
* Or, put it in a structure which is used throughout the driver;
|
||||
* that avoids having to issue two loads for each bit of static data.
|
||||
*/
|
||||
static unsigned int uwire_idx_shift;
|
||||
static void __iomem *uwire_base;
|
||||
|
||||
static inline void uwire_write_reg(int idx, u16 val)
|
||||
{
|
||||
__raw_writew(val, UWIRE_BASE + (idx << uwire_idx_shift));
|
||||
__raw_writew(val, uwire_base + (idx << uwire_idx_shift));
|
||||
}
|
||||
|
||||
static inline u16 uwire_read_reg(int idx)
|
||||
{
|
||||
return __raw_readw(UWIRE_BASE + (idx << uwire_idx_shift));
|
||||
return __raw_readw(uwire_base + (idx << uwire_idx_shift));
|
||||
}
|
||||
|
||||
static inline void omap_uwire_configure_mode(u8 cs, unsigned long flags)
|
||||
|
@ -492,6 +496,14 @@ static int __init uwire_probe(struct platform_device *pdev)
|
|||
return -ENODEV;
|
||||
|
||||
uwire = spi_master_get_devdata(master);
|
||||
|
||||
uwire_base = ioremap(UWIRE_BASE_PHYS, UWIRE_IO_SIZE);
|
||||
if (!uwire_base) {
|
||||
dev_dbg(&pdev->dev, "can't ioremap UWIRE\n");
|
||||
spi_master_put(master);
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
dev_set_drvdata(&pdev->dev, uwire);
|
||||
|
||||
uwire->ck = clk_get(&pdev->dev, "armxor_ck");
|
||||
|
@ -520,8 +532,10 @@ static int __init uwire_probe(struct platform_device *pdev)
|
|||
uwire->bitbang.txrx_bufs = uwire_txrx;
|
||||
|
||||
status = spi_bitbang_start(&uwire->bitbang);
|
||||
if (status < 0)
|
||||
if (status < 0) {
|
||||
uwire_off(uwire);
|
||||
iounmap(uwire_base);
|
||||
}
|
||||
return status;
|
||||
}
|
||||
|
||||
|
@ -534,6 +548,7 @@ static int __exit uwire_remove(struct platform_device *pdev)
|
|||
|
||||
status = spi_bitbang_stop(&uwire->bitbang);
|
||||
uwire_off(uwire);
|
||||
iounmap(uwire_base);
|
||||
return status;
|
||||
}
|
||||
|
||||
|
|
|
@ -344,7 +344,12 @@ static int usb_hcd_omap_probe (const struct hc_driver *driver,
|
|||
goto err1;
|
||||
}
|
||||
|
||||
hcd->regs = (void __iomem *) (int) IO_ADDRESS(hcd->rsrc_start);
|
||||
hcd->regs = ioremap(hcd->rsrc_start, hcd->rsrc_len);
|
||||
if (!hcd->regs) {
|
||||
dev_err(&pdev->dev, "can't ioremap OHCI HCD\n");
|
||||
retval = -ENOMEM;
|
||||
goto err2;
|
||||
}
|
||||
|
||||
ohci = hcd_to_ohci(hcd);
|
||||
ohci_hcd_init(ohci);
|
||||
|
@ -355,11 +360,11 @@ static int usb_hcd_omap_probe (const struct hc_driver *driver,
|
|||
irq = platform_get_irq(pdev, 0);
|
||||
if (irq < 0) {
|
||||
retval = -ENXIO;
|
||||
goto err2;
|
||||
goto err3;
|
||||
}
|
||||
retval = usb_add_hcd(hcd, irq, IRQF_DISABLED);
|
||||
if (retval)
|
||||
goto err2;
|
||||
goto err3;
|
||||
|
||||
host_initialized = 1;
|
||||
|
||||
|
@ -367,6 +372,8 @@ static int usb_hcd_omap_probe (const struct hc_driver *driver,
|
|||
omap_ohci_clock_power(0);
|
||||
|
||||
return 0;
|
||||
err3:
|
||||
iounmap(hcd->regs);
|
||||
err2:
|
||||
release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
|
||||
err1:
|
||||
|
@ -401,6 +408,7 @@ usb_hcd_omap_remove (struct usb_hcd *hcd, struct platform_device *pdev)
|
|||
}
|
||||
if (machine_is_omap_osk())
|
||||
omap_free_gpio(9);
|
||||
iounmap(hcd->regs);
|
||||
release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
|
||||
usb_put_hcd(hcd);
|
||||
clk_put(usb_dc_ck);
|
||||
|
|
|
@ -156,7 +156,7 @@ struct resmap {
|
|||
};
|
||||
|
||||
static struct {
|
||||
u32 base;
|
||||
void __iomem *base;
|
||||
|
||||
struct omapfb_mem_desc mem_desc;
|
||||
struct resmap *res_map[DISPC_MEMTYPE_NUM];
|
||||
|
@ -212,9 +212,9 @@ static void enable_rfbi_mode(int enable)
|
|||
dispc_write_reg(DISPC_CONTROL, l);
|
||||
|
||||
/* Set bypass mode in RFBI module */
|
||||
l = __raw_readl(io_p2v(RFBI_CONTROL));
|
||||
l = __raw_readl(IO_ADDRESS(RFBI_CONTROL));
|
||||
l |= enable ? 0 : (1 << 1);
|
||||
__raw_writel(l, io_p2v(RFBI_CONTROL));
|
||||
__raw_writel(l, IO_ADDRESS(RFBI_CONTROL));
|
||||
}
|
||||
|
||||
static void set_lcd_data_lines(int data_lines)
|
||||
|
@ -1349,14 +1349,19 @@ static int omap_dispc_init(struct omapfb_device *fbdev, int ext_mode,
|
|||
|
||||
memset(&dispc, 0, sizeof(dispc));
|
||||
|
||||
dispc.base = io_p2v(DISPC_BASE);
|
||||
dispc.base = ioremap(DISPC_BASE, SZ_1K);
|
||||
if (!dispc.base) {
|
||||
dev_err(fbdev->dev, "can't ioremap DISPC\n");
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
dispc.fbdev = fbdev;
|
||||
dispc.ext_mode = ext_mode;
|
||||
|
||||
init_completion(&dispc.frame_done);
|
||||
|
||||
if ((r = get_dss_clocks()) < 0)
|
||||
return r;
|
||||
goto fail0;
|
||||
|
||||
enable_interface_clocks(1);
|
||||
enable_lcd_clocks(1);
|
||||
|
@ -1414,7 +1419,7 @@ static int omap_dispc_init(struct omapfb_device *fbdev, int ext_mode,
|
|||
}
|
||||
|
||||
/* L3 firewall setting: enable access to OCM RAM */
|
||||
__raw_writel(0x402000b0, io_p2v(0x680050a0));
|
||||
__raw_writel(0x402000b0, IO_ADDRESS(0x680050a0));
|
||||
|
||||
if ((r = alloc_palette_ram()) < 0)
|
||||
goto fail2;
|
||||
|
@ -1464,7 +1469,8 @@ fail1:
|
|||
enable_lcd_clocks(0);
|
||||
enable_interface_clocks(0);
|
||||
put_dss_clocks();
|
||||
|
||||
fail0:
|
||||
iounmap(dispc.base);
|
||||
return r;
|
||||
}
|
||||
|
||||
|
@ -1481,6 +1487,7 @@ static void omap_dispc_cleanup(void)
|
|||
free_irq(INT_24XX_DSS_IRQ, dispc.fbdev);
|
||||
enable_interface_clocks(0);
|
||||
put_dss_clocks();
|
||||
iounmap(dispc.base);
|
||||
}
|
||||
|
||||
const struct lcd_ctrl omap2_int_ctrl = {
|
||||
|
|
|
@ -40,4 +40,6 @@ extern void omap_dispc_enable_digit_out(int enable);
|
|||
extern int omap_dispc_request_irq(void (*callback)(void *data), void *data);
|
||||
extern void omap_dispc_free_irq(void);
|
||||
|
||||
extern const struct lcd_ctrl omap2_int_ctrl;
|
||||
|
||||
#endif
|
||||
|
|
|
@ -47,7 +47,7 @@ static unsigned long h4_panel_get_caps(struct lcd_panel *panel)
|
|||
return 0;
|
||||
}
|
||||
|
||||
struct lcd_panel h4_panel = {
|
||||
static struct lcd_panel h4_panel = {
|
||||
.name = "h4",
|
||||
.config = OMAP_LCDC_PANEL_TFT,
|
||||
|
||||
|
@ -91,7 +91,7 @@ static int h4_panel_resume(struct platform_device *pdev)
|
|||
return 0;
|
||||
}
|
||||
|
||||
struct platform_driver h4_panel_driver = {
|
||||
static struct platform_driver h4_panel_driver = {
|
||||
.probe = h4_panel_probe,
|
||||
.remove = h4_panel_remove,
|
||||
.suspend = h4_panel_suspend,
|
||||
|
|
|
@ -34,6 +34,8 @@
|
|||
|
||||
#include <asm/mach-types.h>
|
||||
|
||||
#include "lcdc.h"
|
||||
|
||||
#define MODULE_NAME "lcdc"
|
||||
|
||||
#define OMAP_LCDC_BASE 0xfffec000
|
||||
|
|
Some files were not shown because too many files have changed in this diff Show more
Loading…
Reference in a new issue