gpu: ipu-v3: Use videomode in struct ipu_di_signal_cfg
This patch changes struct ipu_di_signal_cfg to use struct videomode to define video timings and flags. Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
This commit is contained in:
parent
eb10d63555
commit
b6835a719a
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@ -153,34 +153,18 @@ static int ipu_crtc_mode_set(struct drm_crtc *crtc,
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out_pixel_fmt = ipu_crtc->interface_pix_fmt;
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out_pixel_fmt = ipu_crtc->interface_pix_fmt;
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if (mode->flags & DRM_MODE_FLAG_INTERLACE)
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sig_cfg.interlaced = 1;
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if (mode->flags & DRM_MODE_FLAG_PHSYNC)
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sig_cfg.Hsync_pol = 1;
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if (mode->flags & DRM_MODE_FLAG_PVSYNC)
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sig_cfg.Vsync_pol = 1;
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sig_cfg.enable_pol = 1;
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sig_cfg.enable_pol = 1;
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sig_cfg.clk_pol = 0;
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sig_cfg.clk_pol = 0;
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sig_cfg.width = mode->hdisplay;
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sig_cfg.height = mode->vdisplay;
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sig_cfg.pixel_fmt = out_pixel_fmt;
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sig_cfg.pixel_fmt = out_pixel_fmt;
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sig_cfg.h_start_width = mode->htotal - mode->hsync_end;
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sig_cfg.h_sync_width = mode->hsync_end - mode->hsync_start;
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sig_cfg.h_end_width = mode->hsync_start - mode->hdisplay;
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sig_cfg.v_start_width = mode->vtotal - mode->vsync_end;
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sig_cfg.v_sync_width = mode->vsync_end - mode->vsync_start;
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sig_cfg.v_end_width = mode->vsync_start - mode->vdisplay;
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sig_cfg.pixelclock = mode->clock * 1000;
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sig_cfg.clkflags = ipu_crtc->di_clkflags;
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sig_cfg.clkflags = ipu_crtc->di_clkflags;
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sig_cfg.v_to_h_sync = 0;
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sig_cfg.v_to_h_sync = 0;
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sig_cfg.hsync_pin = ipu_crtc->di_hsync_pin;
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sig_cfg.hsync_pin = ipu_crtc->di_hsync_pin;
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sig_cfg.vsync_pin = ipu_crtc->di_vsync_pin;
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sig_cfg.vsync_pin = ipu_crtc->di_vsync_pin;
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ret = ipu_dc_init_sync(ipu_crtc->dc, ipu_crtc->di, sig_cfg.interlaced,
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drm_display_mode_to_videomode(mode, &sig_cfg.mode);
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ret = ipu_dc_init_sync(ipu_crtc->dc, ipu_crtc->di,
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mode->flags & DRM_MODE_FLAG_INTERLACE,
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out_pixel_fmt, mode->hdisplay);
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out_pixel_fmt, mode->hdisplay);
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if (ret) {
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if (ret) {
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dev_err(ipu_crtc->dev,
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dev_err(ipu_crtc->dev,
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@ -207,10 +207,10 @@ static void ipu_di_sync_config(struct ipu_di *di, struct di_sync_config *config,
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static void ipu_di_sync_config_interlaced(struct ipu_di *di,
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static void ipu_di_sync_config_interlaced(struct ipu_di *di,
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struct ipu_di_signal_cfg *sig)
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struct ipu_di_signal_cfg *sig)
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{
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{
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u32 h_total = sig->width + sig->h_sync_width +
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u32 h_total = sig->mode.hactive + sig->mode.hsync_len +
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sig->h_start_width + sig->h_end_width;
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sig->mode.hback_porch + sig->mode.hfront_porch;
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u32 v_total = sig->height + sig->v_sync_width +
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u32 v_total = sig->mode.vactive + sig->mode.vsync_len +
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sig->v_start_width + sig->v_end_width;
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sig->mode.vback_porch + sig->mode.vfront_porch;
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u32 reg;
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u32 reg;
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struct di_sync_config cfg[] = {
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struct di_sync_config cfg[] = {
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{
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{
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@ -229,13 +229,13 @@ static void ipu_di_sync_config_interlaced(struct ipu_di *di,
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}, {
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}, {
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.run_count = v_total / 2 - 1,
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.run_count = v_total / 2 - 1,
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.run_src = DI_SYNC_HSYNC,
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.run_src = DI_SYNC_HSYNC,
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.offset_count = sig->v_start_width,
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.offset_count = sig->mode.vback_porch,
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.offset_src = DI_SYNC_HSYNC,
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.offset_src = DI_SYNC_HSYNC,
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.repeat_count = 2,
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.repeat_count = 2,
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.cnt_clr_src = DI_SYNC_VSYNC,
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.cnt_clr_src = DI_SYNC_VSYNC,
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}, {
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}, {
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.run_src = DI_SYNC_HSYNC,
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.run_src = DI_SYNC_HSYNC,
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.repeat_count = sig->height / 2,
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.repeat_count = sig->mode.vactive / 2,
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.cnt_clr_src = 4,
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.cnt_clr_src = 4,
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}, {
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}, {
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.run_count = v_total - 1,
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.run_count = v_total - 1,
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@ -249,9 +249,9 @@ static void ipu_di_sync_config_interlaced(struct ipu_di *di,
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.cnt_clr_src = DI_SYNC_VSYNC,
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.cnt_clr_src = DI_SYNC_VSYNC,
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}, {
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}, {
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.run_src = DI_SYNC_CLK,
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.run_src = DI_SYNC_CLK,
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.offset_count = sig->h_start_width,
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.offset_count = sig->mode.hback_porch,
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.offset_src = DI_SYNC_CLK,
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.offset_src = DI_SYNC_CLK,
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.repeat_count = sig->width,
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.repeat_count = sig->mode.hactive,
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.cnt_clr_src = 5,
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.cnt_clr_src = 5,
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}, {
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}, {
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.run_count = v_total - 1,
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.run_count = v_total - 1,
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@ -277,10 +277,10 @@ static void ipu_di_sync_config_interlaced(struct ipu_di *di,
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static void ipu_di_sync_config_noninterlaced(struct ipu_di *di,
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static void ipu_di_sync_config_noninterlaced(struct ipu_di *di,
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struct ipu_di_signal_cfg *sig, int div)
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struct ipu_di_signal_cfg *sig, int div)
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{
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{
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u32 h_total = sig->width + sig->h_sync_width + sig->h_start_width +
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u32 h_total = sig->mode.hactive + sig->mode.hsync_len +
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sig->h_end_width;
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sig->mode.hback_porch + sig->mode.hfront_porch;
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u32 v_total = sig->height + sig->v_sync_width + sig->v_start_width +
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u32 v_total = sig->mode.vactive + sig->mode.vsync_len +
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sig->v_end_width;
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sig->mode.vback_porch + sig->mode.vfront_porch;
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struct di_sync_config cfg[] = {
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struct di_sync_config cfg[] = {
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{
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{
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/* 1: INT_HSYNC */
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/* 1: INT_HSYNC */
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@ -294,27 +294,29 @@ static void ipu_di_sync_config_noninterlaced(struct ipu_di *di,
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.offset_src = DI_SYNC_CLK,
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.offset_src = DI_SYNC_CLK,
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.cnt_polarity_gen_en = 1,
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.cnt_polarity_gen_en = 1,
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.cnt_polarity_trigger_src = DI_SYNC_CLK,
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.cnt_polarity_trigger_src = DI_SYNC_CLK,
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.cnt_down = sig->h_sync_width * 2,
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.cnt_down = sig->mode.hsync_len * 2,
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} , {
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} , {
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/* PIN3: VSYNC */
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/* PIN3: VSYNC */
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.run_count = v_total - 1,
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.run_count = v_total - 1,
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.run_src = DI_SYNC_INT_HSYNC,
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.run_src = DI_SYNC_INT_HSYNC,
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.cnt_polarity_gen_en = 1,
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.cnt_polarity_gen_en = 1,
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.cnt_polarity_trigger_src = DI_SYNC_INT_HSYNC,
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.cnt_polarity_trigger_src = DI_SYNC_INT_HSYNC,
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.cnt_down = sig->v_sync_width * 2,
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.cnt_down = sig->mode.vsync_len * 2,
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} , {
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} , {
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/* 4: Line Active */
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/* 4: Line Active */
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.run_src = DI_SYNC_HSYNC,
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.run_src = DI_SYNC_HSYNC,
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.offset_count = sig->v_sync_width + sig->v_start_width,
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.offset_count = sig->mode.vsync_len +
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sig->mode.vback_porch,
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.offset_src = DI_SYNC_HSYNC,
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.offset_src = DI_SYNC_HSYNC,
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.repeat_count = sig->height,
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.repeat_count = sig->mode.vactive,
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.cnt_clr_src = DI_SYNC_VSYNC,
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.cnt_clr_src = DI_SYNC_VSYNC,
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} , {
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} , {
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/* 5: Pixel Active, referenced by DC */
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/* 5: Pixel Active, referenced by DC */
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.run_src = DI_SYNC_CLK,
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.run_src = DI_SYNC_CLK,
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.offset_count = sig->h_sync_width + sig->h_start_width,
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.offset_count = sig->mode.hsync_len +
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sig->mode.hback_porch,
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.offset_src = DI_SYNC_CLK,
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.offset_src = DI_SYNC_CLK,
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.repeat_count = sig->width,
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.repeat_count = sig->mode.hactive,
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.cnt_clr_src = 5, /* Line Active */
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.cnt_clr_src = 5, /* Line Active */
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} , {
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} , {
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/* unused */
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/* unused */
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@ -339,9 +341,10 @@ static void ipu_di_sync_config_noninterlaced(struct ipu_di *di,
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} , {
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} , {
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/* 3: Line Active */
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/* 3: Line Active */
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.run_src = DI_SYNC_INT_HSYNC,
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.run_src = DI_SYNC_INT_HSYNC,
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.offset_count = sig->v_sync_width + sig->v_start_width,
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.offset_count = sig->mode.vsync_len +
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sig->mode.vback_porch,
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.offset_src = DI_SYNC_INT_HSYNC,
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.offset_src = DI_SYNC_INT_HSYNC,
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.repeat_count = sig->height,
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.repeat_count = sig->mode.vactive,
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.cnt_clr_src = 3 /* VSYNC */,
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.cnt_clr_src = 3 /* VSYNC */,
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} , {
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} , {
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/* PIN4: HSYNC for VGA via TVEv2 on TQ MBa53 */
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/* PIN4: HSYNC for VGA via TVEv2 on TQ MBa53 */
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@ -351,13 +354,14 @@ static void ipu_di_sync_config_noninterlaced(struct ipu_di *di,
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.offset_src = DI_SYNC_CLK,
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.offset_src = DI_SYNC_CLK,
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.cnt_polarity_gen_en = 1,
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.cnt_polarity_gen_en = 1,
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.cnt_polarity_trigger_src = DI_SYNC_CLK,
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.cnt_polarity_trigger_src = DI_SYNC_CLK,
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.cnt_down = sig->h_sync_width * 2,
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.cnt_down = sig->mode.hsync_len * 2,
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} , {
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} , {
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/* 5: Pixel Active signal to DC */
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/* 5: Pixel Active signal to DC */
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.run_src = DI_SYNC_CLK,
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.run_src = DI_SYNC_CLK,
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.offset_count = sig->h_sync_width + sig->h_start_width,
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.offset_count = sig->mode.hsync_len +
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sig->mode.hback_porch,
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.offset_src = DI_SYNC_CLK,
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.offset_src = DI_SYNC_CLK,
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.repeat_count = sig->width,
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.repeat_count = sig->mode.hactive,
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.cnt_clr_src = 4, /* Line Active */
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.cnt_clr_src = 4, /* Line Active */
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} , {
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} , {
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/* PIN6: VSYNC for VGA via TVEv2 on TQ MBa53 */
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/* PIN6: VSYNC for VGA via TVEv2 on TQ MBa53 */
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@ -367,7 +371,7 @@ static void ipu_di_sync_config_noninterlaced(struct ipu_di *di,
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.offset_src = DI_SYNC_INT_HSYNC,
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.offset_src = DI_SYNC_INT_HSYNC,
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.cnt_polarity_gen_en = 1,
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.cnt_polarity_gen_en = 1,
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.cnt_polarity_trigger_src = DI_SYNC_INT_HSYNC,
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.cnt_polarity_trigger_src = DI_SYNC_INT_HSYNC,
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.cnt_down = sig->v_sync_width * 2,
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.cnt_down = sig->mode.vsync_len * 2,
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} , {
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} , {
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/* PIN4: HSYNC for VGA via TVEv2 on i.MX53-QSB */
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/* PIN4: HSYNC for VGA via TVEv2 on i.MX53-QSB */
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.run_count = h_total - 1,
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.run_count = h_total - 1,
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@ -376,7 +380,7 @@ static void ipu_di_sync_config_noninterlaced(struct ipu_di *di,
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.offset_src = DI_SYNC_CLK,
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.offset_src = DI_SYNC_CLK,
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.cnt_polarity_gen_en = 1,
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.cnt_polarity_gen_en = 1,
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.cnt_polarity_trigger_src = DI_SYNC_CLK,
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.cnt_polarity_trigger_src = DI_SYNC_CLK,
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.cnt_down = sig->h_sync_width * 2,
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.cnt_down = sig->mode.hsync_len * 2,
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} , {
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} , {
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/* PIN6: VSYNC for VGA via TVEv2 on i.MX53-QSB */
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/* PIN6: VSYNC for VGA via TVEv2 on i.MX53-QSB */
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.run_count = v_total - 1,
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.run_count = v_total - 1,
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@ -385,7 +389,7 @@ static void ipu_di_sync_config_noninterlaced(struct ipu_di *di,
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.offset_src = DI_SYNC_INT_HSYNC,
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.offset_src = DI_SYNC_INT_HSYNC,
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.cnt_polarity_gen_en = 1,
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.cnt_polarity_gen_en = 1,
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.cnt_polarity_trigger_src = DI_SYNC_INT_HSYNC,
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.cnt_polarity_trigger_src = DI_SYNC_INT_HSYNC,
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.cnt_down = sig->v_sync_width * 2,
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.cnt_down = sig->mode.vsync_len * 2,
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} , {
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} , {
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/* unused */
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/* unused */
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},
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},
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@ -433,10 +437,11 @@ static void ipu_di_config_clock(struct ipu_di *di,
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unsigned long in_rate;
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unsigned long in_rate;
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unsigned div;
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unsigned div;
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clk_set_rate(clk, sig->pixelclock);
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clk_set_rate(clk, sig->mode.pixelclock);
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in_rate = clk_get_rate(clk);
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in_rate = clk_get_rate(clk);
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div = (in_rate + sig->pixelclock / 2) / sig->pixelclock;
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div = (in_rate + sig->mode.pixelclock / 2) /
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sig->mode.pixelclock;
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if (div == 0)
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if (div == 0)
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div = 1;
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div = 1;
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@ -454,10 +459,11 @@ static void ipu_di_config_clock(struct ipu_di *di,
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unsigned div, error;
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unsigned div, error;
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clkrate = clk_get_rate(di->clk_ipu);
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clkrate = clk_get_rate(di->clk_ipu);
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div = (clkrate + sig->pixelclock / 2) / sig->pixelclock;
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div = (clkrate + sig->mode.pixelclock / 2) /
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sig->mode.pixelclock;
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rate = clkrate / div;
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rate = clkrate / div;
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error = rate / (sig->pixelclock / 1000);
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error = rate / (sig->mode.pixelclock / 1000);
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dev_dbg(di->ipu->dev, " IPU clock can give %lu with divider %u, error %d.%u%%\n",
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dev_dbg(di->ipu->dev, " IPU clock can give %lu with divider %u, error %d.%u%%\n",
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rate, div, (signed)(error - 1000) / 10, error % 10);
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rate, div, (signed)(error - 1000) / 10, error % 10);
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@ -473,10 +479,11 @@ static void ipu_di_config_clock(struct ipu_di *di,
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clk = di->clk_di;
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clk = di->clk_di;
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clk_set_rate(clk, sig->pixelclock);
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clk_set_rate(clk, sig->mode.pixelclock);
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in_rate = clk_get_rate(clk);
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in_rate = clk_get_rate(clk);
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div = (in_rate + sig->pixelclock / 2) / sig->pixelclock;
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div = (in_rate + sig->mode.pixelclock / 2) /
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sig->mode.pixelclock;
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if (div == 0)
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if (div == 0)
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div = 1;
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div = 1;
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@ -504,7 +511,7 @@ static void ipu_di_config_clock(struct ipu_di *di,
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ipu_di_write(di, val, DI_GENERAL);
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ipu_di_write(di, val, DI_GENERAL);
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dev_dbg(di->ipu->dev, "Want %luHz IPU %luHz DI %luHz using %s, %luHz\n",
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dev_dbg(di->ipu->dev, "Want %luHz IPU %luHz DI %luHz using %s, %luHz\n",
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sig->pixelclock,
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sig->mode.pixelclock,
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clk_get_rate(di->clk_ipu),
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clk_get_rate(di->clk_ipu),
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clk_get_rate(di->clk_di),
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clk_get_rate(di->clk_di),
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clk == di->clk_di ? "DI" : "IPU",
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clk == di->clk_di ? "DI" : "IPU",
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@ -547,15 +554,15 @@ int ipu_di_init_sync_panel(struct ipu_di *di, struct ipu_di_signal_cfg *sig)
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u32 div;
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u32 div;
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dev_dbg(di->ipu->dev, "disp %d: panel size = %d x %d\n",
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dev_dbg(di->ipu->dev, "disp %d: panel size = %d x %d\n",
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di->id, sig->width, sig->height);
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di->id, sig->mode.hactive, sig->mode.vactive);
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if ((sig->v_sync_width == 0) || (sig->h_sync_width == 0))
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if ((sig->mode.vsync_len == 0) || (sig->mode.hsync_len == 0))
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return -EINVAL;
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return -EINVAL;
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dev_dbg(di->ipu->dev, "Clocks: IPU %luHz DI %luHz Needed %luHz\n",
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dev_dbg(di->ipu->dev, "Clocks: IPU %luHz DI %luHz Needed %luHz\n",
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clk_get_rate(di->clk_ipu),
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clk_get_rate(di->clk_ipu),
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clk_get_rate(di->clk_di),
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clk_get_rate(di->clk_di),
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sig->pixelclock);
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sig->mode.pixelclock);
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mutex_lock(&di_mutex);
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mutex_lock(&di_mutex);
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@ -574,7 +581,7 @@ int ipu_di_init_sync_panel(struct ipu_di *di, struct ipu_di_signal_cfg *sig)
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di_gen = ipu_di_read(di, DI_GENERAL) & DI_GEN_DI_CLK_EXT;
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di_gen = ipu_di_read(di, DI_GENERAL) & DI_GEN_DI_CLK_EXT;
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||||||
di_gen |= DI_GEN_DI_VSYNC_EXT;
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di_gen |= DI_GEN_DI_VSYNC_EXT;
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||||||
|
|
||||||
if (sig->interlaced) {
|
if (sig->mode.flags & DISPLAY_FLAGS_INTERLACED) {
|
||||||
ipu_di_sync_config_interlaced(di, sig);
|
ipu_di_sync_config_interlaced(di, sig);
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||||||
|
|
||||||
/* set y_sel = 1 */
|
/* set y_sel = 1 */
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||||||
|
@ -584,9 +591,9 @@ int ipu_di_init_sync_panel(struct ipu_di *di, struct ipu_di_signal_cfg *sig)
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||||||
|
|
||||||
vsync_cnt = 7;
|
vsync_cnt = 7;
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||||||
|
|
||||||
if (sig->Hsync_pol)
|
if (sig->mode.flags & DISPLAY_FLAGS_HSYNC_HIGH)
|
||||||
di_gen |= DI_GEN_POLARITY_3;
|
di_gen |= DI_GEN_POLARITY_3;
|
||||||
if (sig->Vsync_pol)
|
if (sig->mode.flags & DISPLAY_FLAGS_VSYNC_HIGH)
|
||||||
di_gen |= DI_GEN_POLARITY_2;
|
di_gen |= DI_GEN_POLARITY_2;
|
||||||
} else {
|
} else {
|
||||||
ipu_di_sync_config_noninterlaced(di, sig, div);
|
ipu_di_sync_config_noninterlaced(di, sig, div);
|
||||||
|
@ -600,7 +607,7 @@ int ipu_di_init_sync_panel(struct ipu_di *di, struct ipu_di_signal_cfg *sig)
|
||||||
if (!(sig->hsync_pin == 2 && sig->vsync_pin == 3))
|
if (!(sig->hsync_pin == 2 && sig->vsync_pin == 3))
|
||||||
vsync_cnt = 6;
|
vsync_cnt = 6;
|
||||||
|
|
||||||
if (sig->Hsync_pol) {
|
if (sig->mode.flags & DISPLAY_FLAGS_HSYNC_HIGH) {
|
||||||
if (sig->hsync_pin == 2)
|
if (sig->hsync_pin == 2)
|
||||||
di_gen |= DI_GEN_POLARITY_2;
|
di_gen |= DI_GEN_POLARITY_2;
|
||||||
else if (sig->hsync_pin == 4)
|
else if (sig->hsync_pin == 4)
|
||||||
|
@ -608,7 +615,7 @@ int ipu_di_init_sync_panel(struct ipu_di *di, struct ipu_di_signal_cfg *sig)
|
||||||
else if (sig->hsync_pin == 7)
|
else if (sig->hsync_pin == 7)
|
||||||
di_gen |= DI_GEN_POLARITY_7;
|
di_gen |= DI_GEN_POLARITY_7;
|
||||||
}
|
}
|
||||||
if (sig->Vsync_pol) {
|
if (sig->mode.flags & DISPLAY_FLAGS_VSYNC_HIGH) {
|
||||||
if (sig->vsync_pin == 3)
|
if (sig->vsync_pin == 3)
|
||||||
di_gen |= DI_GEN_POLARITY_3;
|
di_gen |= DI_GEN_POLARITY_3;
|
||||||
else if (sig->vsync_pin == 6)
|
else if (sig->vsync_pin == 6)
|
||||||
|
|
|
@ -33,28 +33,15 @@ enum ipuv3_type {
|
||||||
* Bitfield of Display Interface signal polarities.
|
* Bitfield of Display Interface signal polarities.
|
||||||
*/
|
*/
|
||||||
struct ipu_di_signal_cfg {
|
struct ipu_di_signal_cfg {
|
||||||
unsigned datamask_en:1;
|
|
||||||
unsigned interlaced:1;
|
|
||||||
unsigned odd_field_first:1;
|
|
||||||
unsigned clksel_en:1;
|
|
||||||
unsigned clkidle_en:1;
|
|
||||||
unsigned data_pol:1; /* true = inverted */
|
unsigned data_pol:1; /* true = inverted */
|
||||||
unsigned clk_pol:1; /* true = rising edge */
|
unsigned clk_pol:1; /* true = rising edge */
|
||||||
unsigned enable_pol:1;
|
unsigned enable_pol:1;
|
||||||
unsigned Hsync_pol:1; /* true = active high */
|
|
||||||
unsigned Vsync_pol:1;
|
|
||||||
|
|
||||||
u16 width;
|
struct videomode mode;
|
||||||
u16 height;
|
|
||||||
u32 pixel_fmt;
|
u32 pixel_fmt;
|
||||||
u16 h_start_width;
|
|
||||||
u16 h_sync_width;
|
|
||||||
u16 h_end_width;
|
|
||||||
u16 v_start_width;
|
|
||||||
u16 v_sync_width;
|
|
||||||
u16 v_end_width;
|
|
||||||
u32 v_to_h_sync;
|
u32 v_to_h_sync;
|
||||||
unsigned long pixelclock;
|
|
||||||
#define IPU_DI_CLKMODE_SYNC (1 << 0)
|
#define IPU_DI_CLKMODE_SYNC (1 << 0)
|
||||||
#define IPU_DI_CLKMODE_EXT (1 << 1)
|
#define IPU_DI_CLKMODE_EXT (1 << 1)
|
||||||
unsigned long clkflags;
|
unsigned long clkflags;
|
||||||
|
|
Loading…
Reference in a new issue