ARM: 7954/1: mm: remove remaining domain support from ARMv6
CPU_32v6 currently selects CPU_USE_DOMAINS if CPU_V6 and MMU. This is because ARM 1136 r0pX CPUs lack the v6k extensions, and therefore do not have hardware thread registers. The lack of these registers requires the kernel to update the vectors page at each context switch in order to write a new TLS pointer. This write must be done via the userspace mapping, since aliasing caches can lead to expensive flushing when using kmap. Finally, this requires the vectors page to be mapped r/w for kernel and r/o for user, which has implications for things like put_user which must trigger CoW appropriately when targetting user pages. The upshot of all this is that a v6/v7 kernel makes use of domains to segregate kernel and user memory accesses. This has the nasty side-effect of making device mappings executable, which has been observed to cause subtle bugs on recent cores (e.g. Cortex-A15 performing a speculative instruction fetch from the GIC and acking an interrupt in the process). This patch solves this problem by removing the remaining domain support from ARMv6. A new memory type is added specifically for the vectors page which allows that page (and only that page) to be mapped as user r/o, kernel r/w. All other user r/o pages are mapped also as kernel r/o. Patch co-developed with Russell King. Cc: <stable@vger.kernel.org> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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@ -3,11 +3,6 @@
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#ifdef __KERNEL__
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#if defined(CONFIG_CPU_USE_DOMAINS) && defined(CONFIG_SMP)
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/* ARM doesn't provide unprivileged exclusive memory accessors */
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#include <asm-generic/futex.h>
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#else
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#include <linux/futex.h>
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#include <linux/uaccess.h>
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#include <asm/errno.h>
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@ -164,6 +159,5 @@ futex_atomic_op_inuser (int encoded_op, u32 __user *uaddr)
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return ret;
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}
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#endif /* !(CPU_USE_DOMAINS && SMP) */
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#endif /* __KERNEL__ */
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#endif /* _ASM_ARM_FUTEX_H */
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@ -140,6 +140,7 @@
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#define L_PTE_MT_DEV_NONSHARED (_AT(pteval_t, 0x0c) << 2) /* 1100 */
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#define L_PTE_MT_DEV_WC (_AT(pteval_t, 0x09) << 2) /* 1001 */
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#define L_PTE_MT_DEV_CACHED (_AT(pteval_t, 0x0b) << 2) /* 1011 */
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#define L_PTE_MT_VECTORS (_AT(pteval_t, 0x0f) << 2) /* 1111 */
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#define L_PTE_MT_MASK (_AT(pteval_t, 0x0f) << 2)
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#ifndef __ASSEMBLY__
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@ -446,7 +446,6 @@ config CPU_32v5
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config CPU_32v6
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bool
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select CPU_USE_DOMAINS if CPU_V6 && MMU
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select TLS_REG_EMUL if !CPU_32v6K && !MMU
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config CPU_32v6K
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@ -671,7 +670,7 @@ config ARM_VIRT_EXT
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config SWP_EMULATE
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bool "Emulate SWP/SWPB instructions"
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depends on !CPU_USE_DOMAINS && CPU_V7
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depends on CPU_V7
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default y if SMP
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select HAVE_PROC_CPU if PROC_FS
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help
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@ -510,6 +510,16 @@ static void __init build_mem_type_table(void)
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s2_pgprot = cp->pte_s2;
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hyp_device_pgprot = s2_device_pgprot = mem_types[MT_DEVICE].prot_pte;
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/*
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* We don't use domains on ARMv6 (since this causes problems with
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* v6/v7 kernels), so we must use a separate memory type for user
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* r/o, kernel r/w to map the vectors page.
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*/
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#ifndef CONFIG_ARM_LPAE
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if (cpu_arch == CPU_ARCH_ARMv6)
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vecs_pgprot |= L_PTE_MT_VECTORS;
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#endif
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/*
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* ARMv6 and above have extended page tables.
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*/
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@ -112,13 +112,9 @@
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* 100x 1 0 1 r/o no acc
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* 10x0 1 0 1 r/o no acc
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* 1011 0 0 1 r/w no acc
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* 110x 0 1 0 r/w r/o
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* 11x0 0 1 0 r/w r/o
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* 1111 0 1 1 r/w r/w
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*
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* If !CONFIG_CPU_USE_DOMAINS, the following permissions are changed:
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* 110x 1 1 1 r/o r/o
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* 11x0 1 1 1 r/o r/o
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* 1111 0 1 1 r/w r/w
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*/
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.macro armv6_mt_table pfx
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\pfx\()_mt_table:
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@ -137,7 +133,7 @@
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.long PTE_EXT_TEX(2) @ L_PTE_MT_DEV_NONSHARED
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.long 0x00 @ unused
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.long 0x00 @ unused
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.long 0x00 @ unused
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.long PTE_CACHEABLE | PTE_BUFFERABLE | PTE_EXT_APX @ L_PTE_MT_VECTORS
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.endm
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.macro armv6_set_pte_ext pfx
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@ -158,24 +154,21 @@
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tst r1, #L_PTE_USER
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orrne r3, r3, #PTE_EXT_AP1
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#ifdef CONFIG_CPU_USE_DOMAINS
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@ allow kernel read/write access to read-only user pages
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tstne r3, #PTE_EXT_APX
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bicne r3, r3, #PTE_EXT_APX | PTE_EXT_AP0
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#endif
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@ user read-only -> kernel read-only
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bicne r3, r3, #PTE_EXT_AP0
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tst r1, #L_PTE_XN
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orrne r3, r3, #PTE_EXT_XN
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orr r3, r3, r2
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eor r3, r3, r2
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tst r1, #L_PTE_YOUNG
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tstne r1, #L_PTE_PRESENT
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moveq r3, #0
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#ifndef CONFIG_CPU_USE_DOMAINS
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tstne r1, #L_PTE_NONE
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movne r3, #0
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#endif
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str r3, [r0]
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mcr p15, 0, r0, c7, c10, 1 @ flush_pte
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@ -90,21 +90,14 @@ ENTRY(cpu_v7_set_pte_ext)
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tst r1, #L_PTE_USER
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orrne r3, r3, #PTE_EXT_AP1
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#ifdef CONFIG_CPU_USE_DOMAINS
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@ allow kernel read/write access to read-only user pages
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tstne r3, #PTE_EXT_APX
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bicne r3, r3, #PTE_EXT_APX | PTE_EXT_AP0
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#endif
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tst r1, #L_PTE_XN
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orrne r3, r3, #PTE_EXT_XN
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tst r1, #L_PTE_YOUNG
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tstne r1, #L_PTE_VALID
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#ifndef CONFIG_CPU_USE_DOMAINS
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eorne r1, r1, #L_PTE_NONE
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tstne r1, #L_PTE_NONE
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#endif
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moveq r3, #0
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ARM( str r3, [r0, #2048]! )
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