powerpc/tm: Move TM abort cause codes to uapi
These cause codes are usable by userspace, so let's export to uapi. Signed-off-by: Michael Neuling <mikey@neuling.org> Cc: <stable@vger.kernel.org> # v3.9 Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
This commit is contained in:
parent
6ce6c629fd
commit
b75c100ef2
|
@ -111,20 +111,6 @@
|
|||
#define MSR_TM_TRANSACTIONAL(x) (((x) & MSR_TS_MASK) == MSR_TS_T)
|
||||
#define MSR_TM_SUSPENDED(x) (((x) & MSR_TS_MASK) == MSR_TS_S)
|
||||
|
||||
/* Reason codes describing kernel causes for transaction aborts. By
|
||||
convention, bit0 is copied to TEXASR[56] (IBM bit 7) which is set if
|
||||
the failure is persistent. PAPR saves 0xff-0xe0 for the hypervisor.
|
||||
*/
|
||||
#define TM_CAUSE_PERSISTENT 0x01
|
||||
#define TM_CAUSE_RESCHED 0xde
|
||||
#define TM_CAUSE_TLBI 0xdc
|
||||
#define TM_CAUSE_FAC_UNAV 0xda
|
||||
#define TM_CAUSE_SYSCALL 0xd8 /* future use */
|
||||
#define TM_CAUSE_MISC 0xd6 /* future use */
|
||||
#define TM_CAUSE_SIGNAL 0xd4
|
||||
#define TM_CAUSE_ALIGNMENT 0xd2
|
||||
#define TM_CAUSE_EMULATE 0xd0
|
||||
|
||||
#if defined(CONFIG_PPC_BOOK3S_64)
|
||||
#define MSR_64BIT MSR_SF
|
||||
|
||||
|
|
|
@ -5,6 +5,8 @@
|
|||
* Copyright 2012 Matt Evans & Michael Neuling, IBM Corporation.
|
||||
*/
|
||||
|
||||
#include <uapi/asm/tm.h>
|
||||
|
||||
#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
|
||||
extern void do_load_up_transact_fpu(struct thread_struct *thread);
|
||||
extern void do_load_up_transact_altivec(struct thread_struct *thread);
|
||||
|
|
|
@ -40,6 +40,7 @@ header-y += statfs.h
|
|||
header-y += swab.h
|
||||
header-y += termbits.h
|
||||
header-y += termios.h
|
||||
header-y += tm.h
|
||||
header-y += types.h
|
||||
header-y += ucontext.h
|
||||
header-y += unistd.h
|
||||
|
|
18
arch/powerpc/include/uapi/asm/tm.h
Normal file
18
arch/powerpc/include/uapi/asm/tm.h
Normal file
|
@ -0,0 +1,18 @@
|
|||
#ifndef _ASM_POWERPC_TM_H
|
||||
#define _ASM_POWERPC_TM_H
|
||||
|
||||
/* Reason codes describing kernel causes for transaction aborts. By
|
||||
* convention, bit0 is copied to TEXASR[56] (IBM bit 7) which is set if
|
||||
* the failure is persistent. PAPR saves 0xff-0xe0 for the hypervisor.
|
||||
*/
|
||||
#define TM_CAUSE_PERSISTENT 0x01
|
||||
#define TM_CAUSE_RESCHED 0xde
|
||||
#define TM_CAUSE_TLBI 0xdc
|
||||
#define TM_CAUSE_FAC_UNAV 0xda
|
||||
#define TM_CAUSE_SYSCALL 0xd8 /* future use */
|
||||
#define TM_CAUSE_MISC 0xd6 /* future use */
|
||||
#define TM_CAUSE_SIGNAL 0xd4
|
||||
#define TM_CAUSE_ALIGNMENT 0xd2
|
||||
#define TM_CAUSE_EMULATE 0xd0
|
||||
|
||||
#endif
|
Loading…
Reference in a new issue