drm/nouveau/disp: allow user direct access to channel control registers
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
parent
648d4dfde7
commit
b76f15295e
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@ -82,6 +82,16 @@ nv50_disp_chan_destroy(struct nv50_disp_chan *chan)
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nouveau_namedb_destroy(&chan->base);
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nouveau_namedb_destroy(&chan->base);
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}
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}
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int
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nv50_disp_chan_map(struct nouveau_object *object, u64 *addr, u32 *size)
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{
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struct nv50_disp_chan *chan = (void *)object;
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*addr = nv_device_resource_start(nv_device(object), 0) +
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0x640000 + (chan->chid * 0x1000);
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*size = 0x001000;
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return 0;
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}
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u32
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u32
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nv50_disp_chan_rd32(struct nouveau_object *object, u64 addr)
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nv50_disp_chan_rd32(struct nouveau_object *object, u64 addr)
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{
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{
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@ -496,6 +506,7 @@ nv50_disp_mast_ofuncs = {
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.base.dtor = nv50_disp_dmac_dtor,
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.base.dtor = nv50_disp_dmac_dtor,
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.base.init = nv50_disp_mast_init,
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.base.init = nv50_disp_mast_init,
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.base.fini = nv50_disp_mast_fini,
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.base.fini = nv50_disp_mast_fini,
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.base.map = nv50_disp_chan_map,
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.base.rd32 = nv50_disp_chan_rd32,
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.base.rd32 = nv50_disp_chan_rd32,
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.base.wr32 = nv50_disp_chan_wr32,
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.base.wr32 = nv50_disp_chan_wr32,
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.chid = 0,
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.chid = 0,
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@ -596,6 +607,7 @@ nv50_disp_sync_ofuncs = {
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.base.dtor = nv50_disp_dmac_dtor,
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.base.dtor = nv50_disp_dmac_dtor,
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.base.init = nv50_disp_dmac_init,
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.base.init = nv50_disp_dmac_init,
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.base.fini = nv50_disp_dmac_fini,
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.base.fini = nv50_disp_dmac_fini,
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.base.map = nv50_disp_chan_map,
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.base.rd32 = nv50_disp_chan_rd32,
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.base.rd32 = nv50_disp_chan_rd32,
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.base.wr32 = nv50_disp_chan_wr32,
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.base.wr32 = nv50_disp_chan_wr32,
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.chid = 1,
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.chid = 1,
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@ -684,6 +696,7 @@ nv50_disp_ovly_ofuncs = {
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.base.dtor = nv50_disp_dmac_dtor,
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.base.dtor = nv50_disp_dmac_dtor,
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.base.init = nv50_disp_dmac_init,
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.base.init = nv50_disp_dmac_init,
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.base.fini = nv50_disp_dmac_fini,
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.base.fini = nv50_disp_dmac_fini,
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.base.map = nv50_disp_chan_map,
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.base.rd32 = nv50_disp_chan_rd32,
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.base.rd32 = nv50_disp_chan_rd32,
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.base.wr32 = nv50_disp_chan_wr32,
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.base.wr32 = nv50_disp_chan_wr32,
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.chid = 3,
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.chid = 3,
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@ -800,6 +813,7 @@ nv50_disp_oimm_ofuncs = {
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.base.dtor = nv50_disp_pioc_dtor,
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.base.dtor = nv50_disp_pioc_dtor,
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.base.init = nv50_disp_pioc_init,
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.base.init = nv50_disp_pioc_init,
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.base.fini = nv50_disp_pioc_fini,
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.base.fini = nv50_disp_pioc_fini,
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.base.map = nv50_disp_chan_map,
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.base.rd32 = nv50_disp_chan_rd32,
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.base.rd32 = nv50_disp_chan_rd32,
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.base.wr32 = nv50_disp_chan_wr32,
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.base.wr32 = nv50_disp_chan_wr32,
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.chid = 5,
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.chid = 5,
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@ -846,6 +860,7 @@ nv50_disp_curs_ofuncs = {
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.base.dtor = nv50_disp_pioc_dtor,
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.base.dtor = nv50_disp_pioc_dtor,
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.base.init = nv50_disp_pioc_init,
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.base.init = nv50_disp_pioc_init,
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.base.fini = nv50_disp_pioc_fini,
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.base.fini = nv50_disp_pioc_fini,
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.base.map = nv50_disp_chan_map,
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.base.rd32 = nv50_disp_chan_rd32,
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.base.rd32 = nv50_disp_chan_rd32,
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.base.wr32 = nv50_disp_chan_wr32,
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.base.wr32 = nv50_disp_chan_wr32,
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.chid = 7,
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.chid = 7,
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@ -116,6 +116,7 @@ struct nv50_disp_chan {
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int chid;
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int chid;
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};
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};
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int nv50_disp_chan_map(struct nouveau_object *, u64 *, u32 *);
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u32 nv50_disp_chan_rd32(struct nouveau_object *, u64);
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u32 nv50_disp_chan_rd32(struct nouveau_object *, u64);
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void nv50_disp_chan_wr32(struct nouveau_object *, u64, u32);
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void nv50_disp_chan_wr32(struct nouveau_object *, u64, u32);
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@ -326,6 +326,7 @@ nvd0_disp_mast_ofuncs = {
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.base.dtor = nv50_disp_dmac_dtor,
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.base.dtor = nv50_disp_dmac_dtor,
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.base.init = nvd0_disp_mast_init,
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.base.init = nvd0_disp_mast_init,
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.base.fini = nvd0_disp_mast_fini,
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.base.fini = nvd0_disp_mast_fini,
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.base.map = nv50_disp_chan_map,
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.base.rd32 = nv50_disp_chan_rd32,
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.base.rd32 = nv50_disp_chan_rd32,
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.base.wr32 = nv50_disp_chan_wr32,
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.base.wr32 = nv50_disp_chan_wr32,
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.chid = 0,
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.chid = 0,
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@ -418,6 +419,7 @@ nvd0_disp_sync_ofuncs = {
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.base.dtor = nv50_disp_dmac_dtor,
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.base.dtor = nv50_disp_dmac_dtor,
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.base.init = nvd0_disp_dmac_init,
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.base.init = nvd0_disp_dmac_init,
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.base.fini = nvd0_disp_dmac_fini,
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.base.fini = nvd0_disp_dmac_fini,
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.base.map = nv50_disp_chan_map,
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.base.rd32 = nv50_disp_chan_rd32,
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.base.rd32 = nv50_disp_chan_rd32,
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.base.wr32 = nv50_disp_chan_wr32,
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.base.wr32 = nv50_disp_chan_wr32,
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.chid = 1,
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.chid = 1,
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@ -497,6 +499,7 @@ nvd0_disp_ovly_ofuncs = {
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.base.dtor = nv50_disp_dmac_dtor,
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.base.dtor = nv50_disp_dmac_dtor,
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.base.init = nvd0_disp_dmac_init,
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.base.init = nvd0_disp_dmac_init,
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.base.fini = nvd0_disp_dmac_fini,
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.base.fini = nvd0_disp_dmac_fini,
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.base.map = nv50_disp_chan_map,
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.base.rd32 = nv50_disp_chan_rd32,
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.base.rd32 = nv50_disp_chan_rd32,
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.base.wr32 = nv50_disp_chan_wr32,
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.base.wr32 = nv50_disp_chan_wr32,
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.chid = 5,
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.chid = 5,
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@ -567,6 +570,7 @@ nvd0_disp_oimm_ofuncs = {
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.base.dtor = nv50_disp_pioc_dtor,
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.base.dtor = nv50_disp_pioc_dtor,
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.base.init = nvd0_disp_pioc_init,
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.base.init = nvd0_disp_pioc_init,
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.base.fini = nvd0_disp_pioc_fini,
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.base.fini = nvd0_disp_pioc_fini,
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.base.map = nv50_disp_chan_map,
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.base.rd32 = nv50_disp_chan_rd32,
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.base.rd32 = nv50_disp_chan_rd32,
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.base.wr32 = nv50_disp_chan_wr32,
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.base.wr32 = nv50_disp_chan_wr32,
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.chid = 9,
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.chid = 9,
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@ -582,6 +586,7 @@ nvd0_disp_curs_ofuncs = {
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.base.dtor = nv50_disp_pioc_dtor,
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.base.dtor = nv50_disp_pioc_dtor,
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.base.init = nvd0_disp_pioc_init,
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.base.init = nvd0_disp_pioc_init,
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.base.fini = nvd0_disp_pioc_fini,
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.base.fini = nvd0_disp_pioc_fini,
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.base.map = nv50_disp_chan_map,
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.base.rd32 = nv50_disp_chan_rd32,
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.base.rd32 = nv50_disp_chan_rd32,
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.base.wr32 = nv50_disp_chan_wr32,
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.base.wr32 = nv50_disp_chan_wr32,
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.chid = 13,
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.chid = 13,
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@ -69,9 +69,11 @@ nv50_chan_create(struct nvif_object *disp, const u32 *oclass, u8 head,
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int ret = nvif_object_init(disp, NULL, (oclass[0] << 16) | head,
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int ret = nvif_object_init(disp, NULL, (oclass[0] << 16) | head,
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oclass[0], data, size,
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oclass[0], data, size,
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&chan->user);
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&chan->user);
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if (oclass++, ret == 0)
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if (oclass++, ret == 0) {
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nvif_object_map(&chan->user);
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return ret;
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return ret;
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}
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}
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}
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return -ENOSYS;
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return -ENOSYS;
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}
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}
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