genirq: Generic chip: Add big endian I/O accessors
Use io{read,write}32be if the caller specified IRQ_GC_BE_IO when creating the irqchip. Signed-off-by: Kevin Cernekee <cernekee@gmail.com> Acked-by: Thomas Gleixner <tglx@linutronix.de> Acked-by: Acked-by: Arnd Bergmann <arnd@arndb.de> Link: https://lkml.kernel.org/r/1415342669-30640-5-git-send-email-cernekee@gmail.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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@ -738,12 +738,14 @@ struct irq_chip_generic {
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* the parent irq. Usually GPIO implementations
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* the parent irq. Usually GPIO implementations
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* @IRQ_GC_MASK_CACHE_PER_TYPE: Mask cache is chip type private
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* @IRQ_GC_MASK_CACHE_PER_TYPE: Mask cache is chip type private
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* @IRQ_GC_NO_MASK: Do not calculate irq_data->mask
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* @IRQ_GC_NO_MASK: Do not calculate irq_data->mask
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* @IRQ_GC_BE_IO: Use big-endian register accesses (default: LE)
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*/
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*/
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enum irq_gc_flags {
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enum irq_gc_flags {
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IRQ_GC_INIT_MASK_CACHE = 1 << 0,
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IRQ_GC_INIT_MASK_CACHE = 1 << 0,
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IRQ_GC_INIT_NESTED_LOCK = 1 << 1,
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IRQ_GC_INIT_NESTED_LOCK = 1 << 1,
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IRQ_GC_MASK_CACHE_PER_TYPE = 1 << 2,
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IRQ_GC_MASK_CACHE_PER_TYPE = 1 << 2,
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IRQ_GC_NO_MASK = 1 << 3,
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IRQ_GC_NO_MASK = 1 << 3,
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IRQ_GC_BE_IO = 1 << 4,
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};
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};
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/*
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/*
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@ -191,6 +191,16 @@ int irq_gc_set_wake(struct irq_data *d, unsigned int on)
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return 0;
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return 0;
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}
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}
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static u32 irq_readl_be(void __iomem *addr)
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{
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return ioread32be(addr);
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}
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static void irq_writel_be(u32 val, void __iomem *addr)
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{
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iowrite32be(val, addr);
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}
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static void
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static void
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irq_init_generic_chip(struct irq_chip_generic *gc, const char *name,
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irq_init_generic_chip(struct irq_chip_generic *gc, const char *name,
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int num_ct, unsigned int irq_base,
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int num_ct, unsigned int irq_base,
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@ -300,7 +310,13 @@ int irq_alloc_domain_generic_chips(struct irq_domain *d, int irqs_per_chip,
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dgc->gc[i] = gc = tmp;
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dgc->gc[i] = gc = tmp;
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irq_init_generic_chip(gc, name, num_ct, i * irqs_per_chip,
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irq_init_generic_chip(gc, name, num_ct, i * irqs_per_chip,
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NULL, handler);
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NULL, handler);
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gc->domain = d;
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gc->domain = d;
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if (gcflags & IRQ_GC_BE_IO) {
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gc->reg_readl = &irq_readl_be;
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gc->reg_writel = &irq_writel_be;
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}
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raw_spin_lock_irqsave(&gc_lock, flags);
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raw_spin_lock_irqsave(&gc_lock, flags);
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list_add_tail(&gc->list, &gc_list);
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list_add_tail(&gc->list, &gc_list);
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raw_spin_unlock_irqrestore(&gc_lock, flags);
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raw_spin_unlock_irqrestore(&gc_lock, flags);
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