drm/i915: Pass dev_priv to INTEL_INFO everywhere apart from the gen use
After this patch only conversion of INTEL_INFO(p)->gen to INTEL_GEN(dev_priv) remains before the __I915__ macro can be removed. v2: Tidy vlv_compute_wm. (David Weinehall) Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Cc: David Weinehall <david.weinehall@linux.intel.com> Reviewed-by: David Weinehall <david.weinehall@linux.intel.com>
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@ -150,7 +150,7 @@ static void intel_detect_pch(struct drm_device *dev)
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/* In all current cases, num_pipes is equivalent to the PCH_NOP setting
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* (which really amounts to a PCH but no South Display).
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*/
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if (INTEL_INFO(dev)->num_pipes == 0) {
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if (INTEL_INFO(dev_priv)->num_pipes == 0) {
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dev_priv->pch_type = PCH_NOP;
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return;
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}
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@ -607,7 +607,7 @@ static int i915_load_modeset_init(struct drm_device *dev)
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intel_modeset_gem_init(dev);
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if (INTEL_INFO(dev)->num_pipes == 0)
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if (INTEL_INFO(dev_priv)->num_pipes == 0)
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return 0;
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ret = intel_fbdev_init(dev);
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@ -707,7 +707,7 @@ static int gen8_48b_mm_switch(struct i915_hw_ppgtt *ppgtt,
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*/
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static void mark_tlbs_dirty(struct i915_hw_ppgtt *ppgtt)
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{
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ppgtt->pd_dirty_rings = INTEL_INFO(ppgtt->base.dev)->ring_mask;
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ppgtt->pd_dirty_rings = INTEL_INFO(to_i915(ppgtt->base.dev))->ring_mask;
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}
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/* Removes entries from a single page table, releasing it if it's empty.
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@ -345,11 +345,10 @@ static void haswell_load_luts(struct drm_crtc_state *crtc_state)
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static void broadwell_load_luts(struct drm_crtc_state *state)
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{
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struct drm_crtc *crtc = state->crtc;
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struct drm_device *dev = crtc->dev;
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struct drm_i915_private *dev_priv = to_i915(dev);
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struct drm_i915_private *dev_priv = to_i915(crtc->dev);
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struct intel_crtc_state *intel_state = to_intel_crtc_state(state);
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enum pipe pipe = to_intel_crtc(crtc)->pipe;
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uint32_t i, lut_size = INTEL_INFO(dev)->color.degamma_lut_size;
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uint32_t i, lut_size = INTEL_INFO(dev_priv)->color.degamma_lut_size;
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if (crtc_state_is_legacy(state)) {
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haswell_load_luts(state);
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@ -428,8 +427,7 @@ static void broadwell_load_luts(struct drm_crtc_state *state)
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static void cherryview_load_luts(struct drm_crtc_state *state)
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{
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struct drm_crtc *crtc = state->crtc;
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struct drm_device *dev = crtc->dev;
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struct drm_i915_private *dev_priv = to_i915(dev);
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struct drm_i915_private *dev_priv = to_i915(crtc->dev);
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enum pipe pipe = to_intel_crtc(crtc)->pipe;
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struct drm_color_lut *lut;
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uint32_t i, lut_size;
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@ -446,7 +444,7 @@ static void cherryview_load_luts(struct drm_crtc_state *state)
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if (state->degamma_lut) {
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lut = (struct drm_color_lut *) state->degamma_lut->data;
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lut_size = INTEL_INFO(dev)->color.degamma_lut_size;
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lut_size = INTEL_INFO(dev_priv)->color.degamma_lut_size;
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for (i = 0; i < lut_size; i++) {
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/* Write LUT in U0.14 format. */
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word0 =
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@ -461,7 +459,7 @@ static void cherryview_load_luts(struct drm_crtc_state *state)
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if (state->gamma_lut) {
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lut = (struct drm_color_lut *) state->gamma_lut->data;
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lut_size = INTEL_INFO(dev)->color.gamma_lut_size;
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lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
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for (i = 0; i < lut_size; i++) {
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/* Write LUT in U0.10 format. */
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word0 =
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@ -497,12 +495,12 @@ void intel_color_load_luts(struct drm_crtc_state *crtc_state)
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int intel_color_check(struct drm_crtc *crtc,
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struct drm_crtc_state *crtc_state)
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{
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struct drm_device *dev = crtc->dev;
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struct drm_i915_private *dev_priv = to_i915(crtc->dev);
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size_t gamma_length, degamma_length;
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degamma_length = INTEL_INFO(dev)->color.degamma_lut_size *
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degamma_length = INTEL_INFO(dev_priv)->color.degamma_lut_size *
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sizeof(struct drm_color_lut);
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gamma_length = INTEL_INFO(dev)->color.gamma_lut_size *
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gamma_length = INTEL_INFO(dev_priv)->color.gamma_lut_size *
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sizeof(struct drm_color_lut);
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/*
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@ -529,8 +527,7 @@ int intel_color_check(struct drm_crtc *crtc,
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void intel_color_init(struct drm_crtc *crtc)
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{
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struct drm_device *dev = crtc->dev;
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struct drm_i915_private *dev_priv = to_i915(dev);
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struct drm_i915_private *dev_priv = to_i915(crtc->dev);
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drm_mode_crtc_set_gamma_size(crtc, 256);
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@ -549,10 +546,10 @@ void intel_color_init(struct drm_crtc *crtc)
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}
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/* Enable color management support when we have degamma & gamma LUTs. */
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if (INTEL_INFO(dev)->color.degamma_lut_size != 0 &&
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INTEL_INFO(dev)->color.gamma_lut_size != 0)
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if (INTEL_INFO(dev_priv)->color.degamma_lut_size != 0 &&
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INTEL_INFO(dev_priv)->color.gamma_lut_size != 0)
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drm_crtc_enable_color_mgmt(crtc,
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INTEL_INFO(dev)->color.degamma_lut_size,
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true,
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INTEL_INFO(dev)->color.gamma_lut_size);
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INTEL_INFO(dev_priv)->color.degamma_lut_size,
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true,
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INTEL_INFO(dev_priv)->color.gamma_lut_size);
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}
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@ -7059,7 +7059,7 @@ static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
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}
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}
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if (INTEL_INFO(dev)->num_pipes == 2)
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if (INTEL_INFO(dev_priv)->num_pipes == 2)
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return 0;
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/* Ivybridge 3 pipe is really complicated */
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@ -14738,8 +14738,7 @@ intel_prepare_plane_fb(struct drm_plane *plane,
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{
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struct intel_atomic_state *intel_state =
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to_intel_atomic_state(new_state->state);
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struct drm_device *dev = plane->dev;
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struct drm_i915_private *dev_priv = to_i915(dev);
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struct drm_i915_private *dev_priv = to_i915(plane->dev);
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struct drm_framebuffer *fb = new_state->fb;
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struct drm_i915_gem_object *obj = intel_fb_obj(fb);
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struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb);
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@ -14796,7 +14795,7 @@ intel_prepare_plane_fb(struct drm_plane *plane,
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}
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if (plane->type == DRM_PLANE_TYPE_CURSOR &&
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INTEL_INFO(dev)->cursor_needs_physical) {
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INTEL_INFO(dev_priv)->cursor_needs_physical) {
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int align = IS_I830(dev_priv) ? 16 * 1024 : 256;
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ret = i915_gem_object_attach_phys(obj, align);
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if (ret) {
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@ -14829,7 +14828,7 @@ void
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intel_cleanup_plane_fb(struct drm_plane *plane,
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struct drm_plane_state *old_state)
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{
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struct drm_device *dev = plane->dev;
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struct drm_i915_private *dev_priv = to_i915(plane->dev);
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struct intel_plane_state *old_intel_state;
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struct drm_i915_gem_object *old_obj = intel_fb_obj(old_state->fb);
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struct drm_i915_gem_object *obj = intel_fb_obj(plane->state->fb);
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@ -14840,7 +14839,7 @@ intel_cleanup_plane_fb(struct drm_plane *plane,
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return;
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if (old_obj && (plane->type != DRM_PLANE_TYPE_CURSOR ||
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!INTEL_INFO(dev)->cursor_needs_physical))
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!INTEL_INFO(dev_priv)->cursor_needs_physical))
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intel_unpin_fb_obj(old_state->fb, old_state->rotation);
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}
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@ -15165,13 +15164,13 @@ intel_update_cursor_plane(struct drm_plane *plane,
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{
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struct drm_crtc *crtc = crtc_state->base.crtc;
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struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
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struct drm_device *dev = plane->dev;
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struct drm_i915_private *dev_priv = to_i915(plane->dev);
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struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
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uint32_t addr;
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if (!obj)
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addr = 0;
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else if (!INTEL_INFO(dev)->cursor_needs_physical)
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else if (!INTEL_INFO(dev_priv)->cursor_needs_physical)
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addr = i915_gem_object_ggtt_offset(obj, NULL);
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else
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addr = obj->phys_handle->busaddr;
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@ -16453,7 +16452,7 @@ int intel_modeset_init(struct drm_device *dev)
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intel_init_pm(dev_priv);
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if (INTEL_INFO(dev)->num_pipes == 0)
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if (INTEL_INFO(dev_priv)->num_pipes == 0)
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return 0;
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/*
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@ -16499,8 +16498,8 @@ int intel_modeset_init(struct drm_device *dev)
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dev->mode_config.fb_base = ggtt->mappable_base;
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DRM_DEBUG_KMS("%d display pipe%s available.\n",
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INTEL_INFO(dev)->num_pipes,
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INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
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INTEL_INFO(dev_priv)->num_pipes,
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INTEL_INFO(dev_priv)->num_pipes > 1 ? "s" : "");
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for_each_pipe(dev_priv, pipe) {
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int ret;
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@ -16588,11 +16587,10 @@ static void intel_enable_pipe_a(struct drm_device *dev)
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static bool
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intel_check_plane_mapping(struct intel_crtc *crtc)
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{
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struct drm_device *dev = crtc->base.dev;
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struct drm_i915_private *dev_priv = to_i915(dev);
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struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
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u32 val;
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if (INTEL_INFO(dev)->num_pipes == 1)
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if (INTEL_INFO(dev_priv)->num_pipes == 1)
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return true;
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val = I915_READ(DSPCNTR(!crtc->plane));
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@ -17345,7 +17343,7 @@ intel_display_print_error_state(struct drm_i915_error_state_buf *m,
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if (!error)
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return;
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err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
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err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev_priv)->num_pipes);
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if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
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err_printf(m, "PWR_WELL_CTL2: %08x\n",
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error->power_well_driver);
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@ -359,7 +359,7 @@ static bool intel_fb_initial_config(struct drm_fb_helper *fb_helper,
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struct drm_fb_offset *offsets,
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bool *enabled, int width, int height)
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{
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struct drm_device *dev = fb_helper->dev;
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struct drm_i915_private *dev_priv = to_i915(fb_helper->dev);
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unsigned long conn_configured, mask;
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unsigned int count = min(fb_helper->connector_count, BITS_PER_LONG);
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int i, j;
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@ -512,7 +512,7 @@ retry:
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* fbdev helper library.
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*/
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if (num_connectors_enabled != num_connectors_detected &&
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num_connectors_enabled < INTEL_INFO(dev)->num_pipes) {
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num_connectors_enabled < INTEL_INFO(dev_priv)->num_pipes) {
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DRM_DEBUG_KMS("fallback: Not all outputs enabled\n");
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DRM_DEBUG_KMS("Enabled: %i, detected: %i\n", num_connectors_enabled,
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num_connectors_detected);
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@ -700,11 +700,11 @@ static void intel_fbdev_suspend_worker(struct work_struct *work)
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int intel_fbdev_init(struct drm_device *dev)
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{
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struct intel_fbdev *ifbdev;
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struct drm_i915_private *dev_priv = to_i915(dev);
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struct intel_fbdev *ifbdev;
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int ret;
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if (WARN_ON(INTEL_INFO(dev)->num_pipes == 0))
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if (WARN_ON(INTEL_INFO(dev_priv)->num_pipes == 0))
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return -ENODEV;
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ifbdev = kzalloc(sizeof(struct intel_fbdev), GFP_KERNEL);
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@ -717,7 +717,7 @@ int intel_fbdev_init(struct drm_device *dev)
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ifbdev->preferred_bpp = 32;
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ret = drm_fb_helper_init(dev, &ifbdev->helper,
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INTEL_INFO(dev)->num_pipes, 4);
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INTEL_INFO(dev_priv)->num_pipes, 4);
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if (ret) {
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kfree(ifbdev);
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return ret;
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@ -1061,7 +1061,8 @@ static void vlv_invert_wms(struct intel_crtc *crtc)
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for (level = 0; level < wm_state->num_levels; level++) {
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struct drm_device *dev = crtc->base.dev;
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const int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1;
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const int sr_fifo_size =
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INTEL_INFO(to_i915(dev))->num_pipes * 512 - 1;
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struct intel_plane *plane;
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wm_state->sr[level].plane = sr_fifo_size - wm_state->sr[level].plane;
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static void vlv_compute_wm(struct intel_crtc *crtc)
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{
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struct drm_device *dev = crtc->base.dev;
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struct drm_i915_private *dev_priv = to_i915(dev);
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struct vlv_wm_state *wm_state = &crtc->wm_state;
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struct intel_plane *plane;
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int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1;
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int sr_fifo_size = INTEL_INFO(dev_priv)->num_pipes * 512 - 1;
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int level;
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memset(wm_state, 0, sizeof(*wm_state));
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wm_state->cxsr = crtc->pipe != PIPE_C && crtc->wm.cxsr_allowed;
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wm_state->num_levels = to_i915(dev)->wm.max_level + 1;
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wm_state->num_levels = dev_priv->wm.max_level + 1;
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wm_state->num_active_planes = 0;
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@ -1179,7 +1181,7 @@ static void vlv_compute_wm(struct intel_crtc *crtc)
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}
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/* clear any (partially) filled invalid levels */
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for (level = wm_state->num_levels; level < to_i915(dev)->wm.max_level + 1; level++) {
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for (level = wm_state->num_levels; level < dev_priv->wm.max_level + 1; level++) {
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memset(&wm_state->wm[level], 0, sizeof(wm_state->wm[level]));
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memset(&wm_state->sr[level], 0, sizeof(wm_state->sr[level]));
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}
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@ -1920,7 +1922,7 @@ static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
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/* HSW allows LP1+ watermarks even with multiple pipes */
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if (level == 0 || config->num_pipes_active > 1) {
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fifo_size /= INTEL_INFO(dev)->num_pipes;
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fifo_size /= INTEL_INFO(to_i915(dev))->num_pipes;
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/*
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* For some reason the non self refresh
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