PCI: read revision ID by default
Currently there are 97 occurrences where drivers need the pci revision ID. We can do this once for all devices. Even the pci subsystem needs the revision several times for quirks. The extra u8 member pads out nicely in the pci_dev struct. Signed-off-by: Auke Kok <auke-jan.h.kok@intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
This commit is contained in:
parent
56906c612e
commit
b8a3a5214d
|
@ -367,8 +367,10 @@ struct pci_dev *of_create_pci_dev(struct device_node *node,
|
|||
sprintf(pci_name(dev), "%04x:%02x:%02x.%d", pci_domain_nr(bus),
|
||||
dev->bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn));
|
||||
dev->class = get_int_prop(node, "class-code", 0);
|
||||
dev->revision = get_int_prop(node, "revision-id", 0);
|
||||
|
||||
DBG(" class: 0x%x\n", dev->class);
|
||||
DBG(" revision: 0x%x\n", dev->revision);
|
||||
|
||||
dev->current_state = 4; /* unknown power state */
|
||||
dev->error_state = pci_channel_io_normal;
|
||||
|
|
|
@ -448,6 +448,7 @@ struct pci_dev *of_create_pci_dev(struct pci_pbm_info *pbm,
|
|||
*/
|
||||
pci_read_config_dword(dev, PCI_CLASS_REVISION, &class);
|
||||
dev->class = class >> 8;
|
||||
dev->revision = class & 0xff;
|
||||
|
||||
sprintf(pci_name(dev), "%04x:%02x:%02x.%d", pci_domain_nr(bus),
|
||||
dev->bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn));
|
||||
|
|
|
@ -702,6 +702,7 @@ static int pci_setup_device(struct pci_dev * dev)
|
|||
dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn));
|
||||
|
||||
pci_read_config_dword(dev, PCI_CLASS_REVISION, &class);
|
||||
dev->revision = class & 0xff;
|
||||
class >>= 8; /* upper 3 bytes */
|
||||
dev->class = class;
|
||||
class >>= 8;
|
||||
|
|
|
@ -139,6 +139,7 @@ struct pci_dev {
|
|||
unsigned short subsystem_vendor;
|
||||
unsigned short subsystem_device;
|
||||
unsigned int class; /* 3 bytes: (base,sub,prog-if) */
|
||||
u8 revision; /* PCI revision, low byte of class word */
|
||||
u8 hdr_type; /* PCI header type (`multi' flag masked out) */
|
||||
u8 rom_base_reg; /* which config register controls the ROM */
|
||||
u8 pin; /* which interrupt pin this device uses */
|
||||
|
|
Loading…
Reference in a new issue