Merge branch 'pxa/devel' into next/devel2
Conflicts: arch/arm/mach-s3c2416/s3c2416.c
This commit is contained in:
commit
b8bc83971c
|
@ -2706,10 +2706,11 @@ bytes respectively. Such letter suffixes can also be entirely omitted.
|
|||
functions are at fixed addresses, they make nice
|
||||
targets for exploits that can control RIP.
|
||||
|
||||
emulate [default] Vsyscalls turn into traps and are
|
||||
emulated reasonably safely.
|
||||
emulate Vsyscalls turn into traps and are emulated
|
||||
reasonably safely.
|
||||
|
||||
native Vsyscalls are native syscall instructions.
|
||||
native [default] Vsyscalls are native syscall
|
||||
instructions.
|
||||
This is a little bit faster than trapping
|
||||
and makes a few dynamic recompilers work
|
||||
better than they would in emulation mode.
|
||||
|
|
|
@ -1042,7 +1042,7 @@ conf/interface/*:
|
|||
The functional behaviour for certain settings is different
|
||||
depending on whether local forwarding is enabled or not.
|
||||
|
||||
accept_ra - BOOLEAN
|
||||
accept_ra - INTEGER
|
||||
Accept Router Advertisements; autoconfigure using them.
|
||||
|
||||
Possible values are:
|
||||
|
@ -1106,7 +1106,7 @@ dad_transmits - INTEGER
|
|||
The amount of Duplicate Address Detection probes to send.
|
||||
Default: 1
|
||||
|
||||
forwarding - BOOLEAN
|
||||
forwarding - INTEGER
|
||||
Configure interface-specific Host/Router behaviour.
|
||||
|
||||
Note: It is recommended to have the same setting on all
|
||||
|
|
|
@ -27,7 +27,7 @@ applying a filter to each packet that assigns it to one of a small number
|
|||
of logical flows. Packets for each flow are steered to a separate receive
|
||||
queue, which in turn can be processed by separate CPUs. This mechanism is
|
||||
generally known as “Receive-side Scaling” (RSS). The goal of RSS and
|
||||
the other scaling techniques to increase performance uniformly.
|
||||
the other scaling techniques is to increase performance uniformly.
|
||||
Multi-queue distribution can also be used for traffic prioritization, but
|
||||
that is not the focus of these techniques.
|
||||
|
||||
|
@ -186,10 +186,10 @@ are steered using plain RPS. Multiple table entries may point to the
|
|||
same CPU. Indeed, with many flows and few CPUs, it is very likely that
|
||||
a single application thread handles flows with many different flow hashes.
|
||||
|
||||
rps_sock_table is a global flow table that contains the *desired* CPU for
|
||||
flows: the CPU that is currently processing the flow in userspace. Each
|
||||
table value is a CPU index that is updated during calls to recvmsg and
|
||||
sendmsg (specifically, inet_recvmsg(), inet_sendmsg(), inet_sendpage()
|
||||
rps_sock_flow_table is a global flow table that contains the *desired* CPU
|
||||
for flows: the CPU that is currently processing the flow in userspace.
|
||||
Each table value is a CPU index that is updated during calls to recvmsg
|
||||
and sendmsg (specifically, inet_recvmsg(), inet_sendmsg(), inet_sendpage()
|
||||
and tcp_splice_read()).
|
||||
|
||||
When the scheduler moves a thread to a new CPU while it has outstanding
|
||||
|
@ -243,7 +243,7 @@ configured. The number of entries in the global flow table is set through:
|
|||
|
||||
The number of entries in the per-queue flow table are set through:
|
||||
|
||||
/sys/class/net/<dev>/queues/tx-<n>/rps_flow_cnt
|
||||
/sys/class/net/<dev>/queues/rx-<n>/rps_flow_cnt
|
||||
|
||||
== Suggested Configuration
|
||||
|
||||
|
|
|
@ -2460,7 +2460,7 @@ S: Supported
|
|||
F: drivers/infiniband/hw/ehca/
|
||||
|
||||
EHEA (IBM pSeries eHEA 10Gb ethernet adapter) DRIVER
|
||||
M: Breno Leitao <leitao@linux.vnet.ibm.com>
|
||||
M: Thadeu Lima de Souza Cascardo <cascardo@linux.vnet.ibm.com>
|
||||
L: netdev@vger.kernel.org
|
||||
S: Maintained
|
||||
F: drivers/net/ehea/
|
||||
|
@ -3313,7 +3313,7 @@ M: David Woodhouse <dwmw2@infradead.org>
|
|||
L: iommu@lists.linux-foundation.org
|
||||
T: git git://git.infradead.org/iommu-2.6.git
|
||||
S: Supported
|
||||
F: drivers/pci/intel-iommu.c
|
||||
F: drivers/iommu/intel-iommu.c
|
||||
F: include/linux/intel-iommu.h
|
||||
|
||||
INTEL IOP-ADMA DMA DRIVER
|
||||
|
@ -6366,15 +6366,14 @@ F: net/ipv4/tcp_lp.c
|
|||
|
||||
TEGRA SUPPORT
|
||||
M: Colin Cross <ccross@android.com>
|
||||
M: Erik Gilling <konkers@android.com>
|
||||
M: Olof Johansson <olof@lixom.net>
|
||||
M: Stephen Warren <swarren@nvidia.com>
|
||||
L: linux-tegra@vger.kernel.org
|
||||
T: git git://android.git.kernel.org/kernel/tegra.git
|
||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/olof/tegra.git
|
||||
S: Supported
|
||||
F: arch/arm/mach-tegra
|
||||
|
||||
TEHUTI ETHERNET DRIVER
|
||||
M: Alexander Indenbaum <baum@tehutinetworks.net>
|
||||
M: Andy Gospodarek <andy@greyhouse.net>
|
||||
L: netdev@vger.kernel.org
|
||||
S: Supported
|
||||
|
|
2
Makefile
2
Makefile
|
@ -1,7 +1,7 @@
|
|||
VERSION = 3
|
||||
PATCHLEVEL = 1
|
||||
SUBLEVEL = 0
|
||||
EXTRAVERSION = -rc8
|
||||
EXTRAVERSION =
|
||||
NAME = "Divemaster Edition"
|
||||
|
||||
# *DOCUMENTATION*
|
||||
|
|
|
@ -559,6 +559,7 @@ config ARCH_MMP
|
|||
select TICK_ONESHOT
|
||||
select PLAT_PXA
|
||||
select SPARSE_IRQ
|
||||
select GENERIC_ALLOCATOR
|
||||
help
|
||||
Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
|
||||
|
||||
|
|
|
@ -259,7 +259,6 @@ static void __init vic_disable(void __iomem *base)
|
|||
writel(0, base + VIC_INT_SELECT);
|
||||
writel(0, base + VIC_INT_ENABLE);
|
||||
writel(~0, base + VIC_INT_ENABLE_CLEAR);
|
||||
writel(0, base + VIC_IRQ_STATUS);
|
||||
writel(0, base + VIC_ITCR);
|
||||
writel(~0, base + VIC_INT_SOFT_CLEAR);
|
||||
}
|
||||
|
|
|
@ -10,6 +10,8 @@
|
|||
#ifndef __ASM_ARM_LOCALTIMER_H
|
||||
#define __ASM_ARM_LOCALTIMER_H
|
||||
|
||||
#include <linux/errno.h>
|
||||
|
||||
struct clock_event_device;
|
||||
|
||||
/*
|
||||
|
|
|
@ -321,8 +321,8 @@ static const unsigned armv7_a9_perf_map[PERF_COUNT_HW_MAX] = {
|
|||
[PERF_COUNT_HW_CPU_CYCLES] = ARMV7_PERFCTR_CPU_CYCLES,
|
||||
[PERF_COUNT_HW_INSTRUCTIONS] =
|
||||
ARMV7_PERFCTR_INST_OUT_OF_RENAME_STAGE,
|
||||
[PERF_COUNT_HW_CACHE_REFERENCES] = ARMV7_PERFCTR_COHERENT_LINE_HIT,
|
||||
[PERF_COUNT_HW_CACHE_MISSES] = ARMV7_PERFCTR_COHERENT_LINE_MISS,
|
||||
[PERF_COUNT_HW_CACHE_REFERENCES] = ARMV7_PERFCTR_DCACHE_ACCESS,
|
||||
[PERF_COUNT_HW_CACHE_MISSES] = ARMV7_PERFCTR_DCACHE_REFILL,
|
||||
[PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV7_PERFCTR_PC_WRITE,
|
||||
[PERF_COUNT_HW_BRANCH_MISSES] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
|
||||
[PERF_COUNT_HW_BUS_CYCLES] = ARMV7_PERFCTR_CLOCK_CYCLES,
|
||||
|
|
|
@ -7,7 +7,7 @@ obj-y += common.o clock.o devices.o time.o
|
|||
# SoC support
|
||||
obj-$(CONFIG_CPU_PXA168) += pxa168.o irq-pxa168.o
|
||||
obj-$(CONFIG_CPU_PXA910) += pxa910.o irq-pxa168.o
|
||||
obj-$(CONFIG_CPU_MMP2) += mmp2.o irq-mmp2.o
|
||||
obj-$(CONFIG_CPU_MMP2) += mmp2.o irq-mmp2.o sram.o
|
||||
|
||||
# board support
|
||||
obj-$(CONFIG_MACH_ASPENITE) += aspenite.o
|
||||
|
|
|
@ -186,6 +186,15 @@ static struct sdhci_pxa_platdata mmp2_sdh_platdata_mmc2 = {
|
|||
| PXA_FLAG_SD_8_BIT_CAPABLE_SLOT,
|
||||
};
|
||||
|
||||
static struct sram_platdata mmp2_asram_platdata = {
|
||||
.pool_name = "asram",
|
||||
.granularity = SRAM_GRANULARITY,
|
||||
};
|
||||
|
||||
static struct sram_platdata mmp2_isram_platdata = {
|
||||
.pool_name = "isram",
|
||||
.granularity = SRAM_GRANULARITY,
|
||||
};
|
||||
|
||||
static void __init brownstone_init(void)
|
||||
{
|
||||
|
@ -197,6 +206,8 @@ static void __init brownstone_init(void)
|
|||
mmp2_add_twsi(1, NULL, ARRAY_AND_SIZE(brownstone_twsi1_info));
|
||||
mmp2_add_sdhost(0, &mmp2_sdh_platdata_mmc0); /* SD/MMC */
|
||||
mmp2_add_sdhost(2, &mmp2_sdh_platdata_mmc2); /* eMMC */
|
||||
mmp2_add_asram(&mmp2_asram_platdata);
|
||||
mmp2_add_isram(&mmp2_isram_platdata);
|
||||
|
||||
/* enable 5v regulator */
|
||||
platform_device_register(&brownstone_v_5vp_device);
|
||||
|
|
|
@ -13,6 +13,7 @@ extern void mmp2_clear_pmic_int(void);
|
|||
#include <linux/i2c.h>
|
||||
#include <linux/i2c/pxa-i2c.h>
|
||||
#include <mach/devices.h>
|
||||
#include <mach/sram.h>
|
||||
|
||||
extern struct pxa_device_desc mmp2_device_uart1;
|
||||
extern struct pxa_device_desc mmp2_device_uart2;
|
||||
|
@ -28,6 +29,8 @@ extern struct pxa_device_desc mmp2_device_sdh0;
|
|||
extern struct pxa_device_desc mmp2_device_sdh1;
|
||||
extern struct pxa_device_desc mmp2_device_sdh2;
|
||||
extern struct pxa_device_desc mmp2_device_sdh3;
|
||||
extern struct pxa_device_desc mmp2_device_asram;
|
||||
extern struct pxa_device_desc mmp2_device_isram;
|
||||
|
||||
static inline int mmp2_add_uart(int id)
|
||||
{
|
||||
|
@ -85,5 +88,15 @@ static inline int mmp2_add_sdhost(int id, struct sdhci_pxa_platdata *data)
|
|||
return pxa_register_device(d, data, sizeof(*data));
|
||||
}
|
||||
|
||||
static inline int mmp2_add_asram(struct sram_platdata *data)
|
||||
{
|
||||
return pxa_register_device(&mmp2_device_asram, data, sizeof(*data));
|
||||
}
|
||||
|
||||
static inline int mmp2_add_isram(struct sram_platdata *data)
|
||||
{
|
||||
return pxa_register_device(&mmp2_device_isram, data, sizeof(*data));
|
||||
}
|
||||
|
||||
#endif /* __ASM_MACH_MMP2_H */
|
||||
|
||||
|
|
35
arch/arm/mach-mmp/include/mach/sram.h
Normal file
35
arch/arm/mach-mmp/include/mach/sram.h
Normal file
|
@ -0,0 +1,35 @@
|
|||
/*
|
||||
* linux/arch/arm/mach-mmp/include/mach/sram.h
|
||||
*
|
||||
* SRAM Memory Management
|
||||
*
|
||||
* Copyright (c) 2011 Marvell Semiconductors Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __ASM_ARCH_SRAM_H
|
||||
#define __ASM_ARCH_SRAM_H
|
||||
|
||||
#include <linux/genalloc.h>
|
||||
|
||||
/* ARBITRARY: SRAM allocations are multiples of this 2^N size */
|
||||
#define SRAM_GRANULARITY 512
|
||||
|
||||
enum sram_type {
|
||||
MMP_SRAM_UNDEFINED = 0,
|
||||
MMP_ASRAM,
|
||||
MMP_ISRAM,
|
||||
};
|
||||
|
||||
struct sram_platdata {
|
||||
char *pool_name;
|
||||
int granularity;
|
||||
};
|
||||
|
||||
extern struct gen_pool *sram_get_gpool(char *pool_name);
|
||||
|
||||
#endif /* __ASM_ARCH_SRAM_H */
|
|
@ -226,4 +226,7 @@ MMP2_DEVICE(sdh0, "sdhci-pxav3", 0, MMC, 0xd4280000, 0x120);
|
|||
MMP2_DEVICE(sdh1, "sdhci-pxav3", 1, MMC2, 0xd4280800, 0x120);
|
||||
MMP2_DEVICE(sdh2, "sdhci-pxav3", 2, MMC3, 0xd4281000, 0x120);
|
||||
MMP2_DEVICE(sdh3, "sdhci-pxav3", 3, MMC4, 0xd4281800, 0x120);
|
||||
MMP2_DEVICE(asram, "asram", -1, NONE, 0xe0000000, 0x4000);
|
||||
/* 0xd1000000 ~ 0xd101ffff is reserved for secure processor */
|
||||
MMP2_DEVICE(isram, "isram", -1, NONE, 0xd1020000, 0x18000);
|
||||
|
||||
|
|
168
arch/arm/mach-mmp/sram.c
Normal file
168
arch/arm/mach-mmp/sram.c
Normal file
|
@ -0,0 +1,168 @@
|
|||
/*
|
||||
* linux/arch/arm/mach-mmp/sram.c
|
||||
*
|
||||
* based on mach-davinci/sram.c - DaVinci simple SRAM allocator
|
||||
*
|
||||
* Copyright (c) 2011 Marvell Semiconductors Inc.
|
||||
* All Rights Reserved
|
||||
*
|
||||
* Add for mmp sram support - Leo Yan <leoy@marvell.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
*/
|
||||
|
||||
#include <linux/module.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/genalloc.h>
|
||||
|
||||
#include <mach/sram.h>
|
||||
|
||||
struct sram_bank_info {
|
||||
char *pool_name;
|
||||
struct gen_pool *gpool;
|
||||
int granularity;
|
||||
|
||||
phys_addr_t sram_phys;
|
||||
void __iomem *sram_virt;
|
||||
u32 sram_size;
|
||||
|
||||
struct list_head node;
|
||||
};
|
||||
|
||||
static DEFINE_MUTEX(sram_lock);
|
||||
static LIST_HEAD(sram_bank_list);
|
||||
|
||||
struct gen_pool *sram_get_gpool(char *pool_name)
|
||||
{
|
||||
struct sram_bank_info *info = NULL;
|
||||
|
||||
if (!pool_name)
|
||||
return NULL;
|
||||
|
||||
mutex_lock(&sram_lock);
|
||||
|
||||
list_for_each_entry(info, &sram_bank_list, node)
|
||||
if (!strcmp(pool_name, info->pool_name))
|
||||
break;
|
||||
|
||||
mutex_unlock(&sram_lock);
|
||||
|
||||
if (&info->node == &sram_bank_list)
|
||||
return NULL;
|
||||
|
||||
return info->gpool;
|
||||
}
|
||||
EXPORT_SYMBOL(sram_get_gpool);
|
||||
|
||||
static int __devinit sram_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct sram_platdata *pdata = pdev->dev.platform_data;
|
||||
struct sram_bank_info *info;
|
||||
struct resource *res;
|
||||
int ret = 0;
|
||||
|
||||
if (!pdata && !pdata->pool_name)
|
||||
return -ENODEV;
|
||||
|
||||
info = kzalloc(sizeof(*info), GFP_KERNEL);
|
||||
if (!info)
|
||||
return -ENOMEM;
|
||||
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
if (res == NULL) {
|
||||
dev_err(&pdev->dev, "no memory resource defined\n");
|
||||
ret = -ENODEV;
|
||||
goto out;
|
||||
}
|
||||
|
||||
if (!resource_size(res))
|
||||
return 0;
|
||||
|
||||
info->sram_phys = (phys_addr_t)res->start;
|
||||
info->sram_size = resource_size(res);
|
||||
info->sram_virt = ioremap(info->sram_phys, info->sram_size);
|
||||
info->pool_name = kstrdup(pdata->pool_name, GFP_KERNEL);
|
||||
info->granularity = pdata->granularity;
|
||||
|
||||
info->gpool = gen_pool_create(ilog2(info->granularity), -1);
|
||||
if (!info->gpool) {
|
||||
dev_err(&pdev->dev, "create pool failed\n");
|
||||
ret = -ENOMEM;
|
||||
goto create_pool_err;
|
||||
}
|
||||
|
||||
ret = gen_pool_add_virt(info->gpool, (unsigned long)info->sram_virt,
|
||||
info->sram_phys, info->sram_size, -1);
|
||||
if (ret < 0) {
|
||||
dev_err(&pdev->dev, "add new chunk failed\n");
|
||||
ret = -ENOMEM;
|
||||
goto add_chunk_err;
|
||||
}
|
||||
|
||||
mutex_lock(&sram_lock);
|
||||
list_add(&info->node, &sram_bank_list);
|
||||
mutex_unlock(&sram_lock);
|
||||
|
||||
platform_set_drvdata(pdev, info);
|
||||
|
||||
dev_info(&pdev->dev, "initialized\n");
|
||||
return 0;
|
||||
|
||||
add_chunk_err:
|
||||
gen_pool_destroy(info->gpool);
|
||||
create_pool_err:
|
||||
iounmap(info->sram_virt);
|
||||
kfree(info->pool_name);
|
||||
out:
|
||||
kfree(info);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int __devexit sram_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct sram_bank_info *info;
|
||||
|
||||
info = platform_get_drvdata(pdev);
|
||||
if (info == NULL)
|
||||
return -ENODEV;
|
||||
|
||||
mutex_lock(&sram_lock);
|
||||
list_del(&info->node);
|
||||
mutex_unlock(&sram_lock);
|
||||
|
||||
gen_pool_destroy(info->gpool);
|
||||
iounmap(info->sram_virt);
|
||||
kfree(info->pool_name);
|
||||
kfree(info);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct platform_device_id sram_id_table[] = {
|
||||
{ "asram", MMP_ASRAM },
|
||||
{ "isram", MMP_ISRAM },
|
||||
{ }
|
||||
};
|
||||
|
||||
static struct platform_driver sram_driver = {
|
||||
.probe = sram_probe,
|
||||
.remove = sram_remove,
|
||||
.driver = {
|
||||
.name = "mmp-sram",
|
||||
},
|
||||
.id_table = sram_id_table,
|
||||
};
|
||||
|
||||
static int __init sram_init(void)
|
||||
{
|
||||
return platform_driver_register(&sram_driver);
|
||||
}
|
||||
core_initcall(sram_init);
|
||||
|
||||
MODULE_LICENSE("GPL");
|
|
@ -193,7 +193,8 @@ static int __init omap2430_i2c_init(void)
|
|||
{
|
||||
omap_register_i2c_bus(1, 100, sdp2430_i2c1_boardinfo,
|
||||
ARRAY_SIZE(sdp2430_i2c1_boardinfo));
|
||||
omap2_pmic_init("twl4030", &sdp2430_twldata);
|
||||
omap_pmic_init(2, 100, "twl4030", INT_24XX_SYS_NIRQ,
|
||||
&sdp2430_twldata);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
|
@ -137,8 +137,7 @@ static void omap4_hsmmc1_before_set_reg(struct device *dev, int slot,
|
|||
*/
|
||||
reg = omap4_ctrl_pad_readl(control_pbias_offset);
|
||||
reg &= ~(OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK |
|
||||
OMAP4_MMC1_PWRDNZ_MASK |
|
||||
OMAP4_USBC1_ICUSB_PWRDNZ_MASK);
|
||||
OMAP4_MMC1_PWRDNZ_MASK);
|
||||
omap4_ctrl_pad_writel(reg, control_pbias_offset);
|
||||
}
|
||||
|
||||
|
@ -156,8 +155,7 @@ static void omap4_hsmmc1_after_set_reg(struct device *dev, int slot,
|
|||
else
|
||||
reg |= OMAP4_MMC1_PBIASLITE_VMODE_MASK;
|
||||
reg |= (OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK |
|
||||
OMAP4_MMC1_PWRDNZ_MASK |
|
||||
OMAP4_USBC1_ICUSB_PWRDNZ_MASK);
|
||||
OMAP4_MMC1_PWRDNZ_MASK);
|
||||
omap4_ctrl_pad_writel(reg, control_pbias_offset);
|
||||
|
||||
timeout = jiffies + msecs_to_jiffies(5);
|
||||
|
@ -171,16 +169,14 @@ static void omap4_hsmmc1_after_set_reg(struct device *dev, int slot,
|
|||
if (reg & OMAP4_MMC1_PBIASLITE_VMODE_ERROR_MASK) {
|
||||
pr_err("Pbias Voltage is not same as LDO\n");
|
||||
/* Caution : On VMODE_ERROR Power Down MMC IO */
|
||||
reg &= ~(OMAP4_MMC1_PWRDNZ_MASK |
|
||||
OMAP4_USBC1_ICUSB_PWRDNZ_MASK);
|
||||
reg &= ~(OMAP4_MMC1_PWRDNZ_MASK);
|
||||
omap4_ctrl_pad_writel(reg, control_pbias_offset);
|
||||
}
|
||||
} else {
|
||||
reg = omap4_ctrl_pad_readl(control_pbias_offset);
|
||||
reg |= (OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK |
|
||||
OMAP4_MMC1_PWRDNZ_MASK |
|
||||
OMAP4_MMC1_PBIASLITE_VMODE_MASK |
|
||||
OMAP4_USBC1_ICUSB_PWRDNZ_MASK);
|
||||
OMAP4_MMC1_PBIASLITE_VMODE_MASK);
|
||||
omap4_ctrl_pad_writel(reg, control_pbias_offset);
|
||||
}
|
||||
}
|
||||
|
|
|
@ -137,9 +137,6 @@ void __init usb_musb_init(struct omap_musb_board_data *musb_board_data)
|
|||
musb_plat.mode = board_data->mode;
|
||||
musb_plat.extvbus = board_data->extvbus;
|
||||
|
||||
if (cpu_is_omap44xx())
|
||||
omap4430_phy_init(dev);
|
||||
|
||||
if (cpu_is_omap3517() || cpu_is_omap3505()) {
|
||||
oh_name = "am35x_otg_hs";
|
||||
name = "musb-am35x";
|
||||
|
|
|
@ -170,7 +170,9 @@ int __init s3c2410_init(void)
|
|||
{
|
||||
printk("S3C2410: Initialising architecture\n");
|
||||
|
||||
#ifdef CONFIG_PM
|
||||
register_syscore_ops(&s3c2410_pm_syscore_ops);
|
||||
#endif
|
||||
register_syscore_ops(&s3c24xx_irq_syscore_ops);
|
||||
|
||||
return sysdev_register(&s3c2410_sysdev);
|
||||
|
|
|
@ -245,7 +245,9 @@ int __init s3c2412_init(void)
|
|||
{
|
||||
printk("S3C2412: Initialising architecture\n");
|
||||
|
||||
#ifdef CONFIG_PM
|
||||
register_syscore_ops(&s3c2412_pm_syscore_ops);
|
||||
#endif
|
||||
register_syscore_ops(&s3c24xx_irq_syscore_ops);
|
||||
|
||||
return sysdev_register(&s3c2412_sysdev);
|
||||
|
|
|
@ -100,7 +100,9 @@ int __init s3c2416_init(void)
|
|||
|
||||
s3c_adc_setname("s3c2416-adc");
|
||||
|
||||
#ifdef CONFIG_PM
|
||||
register_syscore_ops(&s3c2416_pm_syscore_ops);
|
||||
#endif
|
||||
register_syscore_ops(&s3c24xx_irq_syscore_ops);
|
||||
|
||||
return sysdev_register(&s3c2416_sysdev);
|
||||
|
|
|
@ -55,7 +55,9 @@ int __init s3c2440_init(void)
|
|||
|
||||
/* register suspend/resume handlers */
|
||||
|
||||
#ifdef CONFIG_PM
|
||||
register_syscore_ops(&s3c2410_pm_syscore_ops);
|
||||
#endif
|
||||
register_syscore_ops(&s3c244x_pm_syscore_ops);
|
||||
register_syscore_ops(&s3c24xx_irq_syscore_ops);
|
||||
|
||||
|
|
|
@ -169,7 +169,9 @@ int __init s3c2442_init(void)
|
|||
{
|
||||
printk("S3C2442: Initialising architecture\n");
|
||||
|
||||
#ifdef CONFIG_PM
|
||||
register_syscore_ops(&s3c2410_pm_syscore_ops);
|
||||
#endif
|
||||
register_syscore_ops(&s3c244x_pm_syscore_ops);
|
||||
register_syscore_ops(&s3c24xx_irq_syscore_ops);
|
||||
|
||||
|
|
|
@ -32,7 +32,6 @@
|
|||
|
||||
#include <asm/system.h>
|
||||
|
||||
#include <mach/hardware.h>
|
||||
#include <mach/clk.h>
|
||||
|
||||
/* Frequency table index must be sequential starting at 0 */
|
||||
|
|
|
@ -6,6 +6,7 @@ config UX500_SOC_COMMON
|
|||
select ARM_GIC
|
||||
select HAS_MTU
|
||||
select ARM_ERRATA_753970
|
||||
select ARM_ERRATA_754322
|
||||
|
||||
menu "Ux500 SoC"
|
||||
|
||||
|
|
|
@ -496,6 +496,13 @@ static void __init free_unused_memmap(struct meminfo *mi)
|
|||
*/
|
||||
bank_start = min(bank_start,
|
||||
ALIGN(prev_bank_end, PAGES_PER_SECTION));
|
||||
#else
|
||||
/*
|
||||
* Align down here since the VM subsystem insists that the
|
||||
* memmap entries are valid from the bank start aligned to
|
||||
* MAX_ORDER_NR_PAGES.
|
||||
*/
|
||||
bank_start = round_down(bank_start, MAX_ORDER_NR_PAGES);
|
||||
#endif
|
||||
/*
|
||||
* If we had a previous bank, and there is a space
|
||||
|
|
|
@ -163,9 +163,9 @@ static __init int s5p_gpioint_add(struct samsung_gpio_chip *chip)
|
|||
ct->chip.irq_mask = irq_gc_mask_set_bit;
|
||||
ct->chip.irq_unmask = irq_gc_mask_clr_bit;
|
||||
ct->chip.irq_set_type = s5p_gpioint_set_type,
|
||||
ct->regs.ack = PEND_OFFSET + REG_OFFSET(chip->group);
|
||||
ct->regs.mask = MASK_OFFSET + REG_OFFSET(chip->group);
|
||||
ct->regs.type = CON_OFFSET + REG_OFFSET(chip->group);
|
||||
ct->regs.ack = PEND_OFFSET + REG_OFFSET(group - bank->start);
|
||||
ct->regs.mask = MASK_OFFSET + REG_OFFSET(group - bank->start);
|
||||
ct->regs.type = CON_OFFSET + REG_OFFSET(group - bank->start);
|
||||
irq_setup_generic_chip(gc, IRQ_MSK(chip->chip.ngpio),
|
||||
IRQ_GC_INIT_MASK_CACHE,
|
||||
IRQ_NOREQUEST | IRQ_NOPROBE, 0);
|
||||
|
|
|
@ -24,6 +24,7 @@ config MIPS
|
|||
select GENERIC_IRQ_PROBE
|
||||
select GENERIC_IRQ_SHOW
|
||||
select HAVE_ARCH_JUMP_LABEL
|
||||
select IRQ_FORCED_THREADING
|
||||
|
||||
menu "Machine selection"
|
||||
|
||||
|
@ -722,6 +723,7 @@ config CAVIUM_OCTEON_SIMULATOR
|
|||
select SYS_SUPPORTS_HIGHMEM
|
||||
select SYS_SUPPORTS_HOTPLUG_CPU
|
||||
select SYS_HAS_CPU_CAVIUM_OCTEON
|
||||
select HOLES_IN_ZONE
|
||||
help
|
||||
The Octeon simulator is software performance model of the Cavium
|
||||
Octeon Processor. It supports simulating Octeon processors on x86
|
||||
|
@ -744,6 +746,7 @@ config CAVIUM_OCTEON_REFERENCE_BOARD
|
|||
select ZONE_DMA32
|
||||
select USB_ARCH_HAS_OHCI
|
||||
select USB_ARCH_HAS_EHCI
|
||||
select HOLES_IN_ZONE
|
||||
help
|
||||
This option supports all of the Octeon reference boards from Cavium
|
||||
Networks. It builds a kernel that dynamically determines the Octeon
|
||||
|
@ -973,6 +976,9 @@ config ISA_DMA_API
|
|||
config GENERIC_GPIO
|
||||
bool
|
||||
|
||||
config HOLES_IN_ZONE
|
||||
bool
|
||||
|
||||
#
|
||||
# Endianess selection. Sufficiently obscure so many users don't know what to
|
||||
# answer,so we try hard to limit the available choices. Also the use of a
|
||||
|
|
|
@ -492,7 +492,7 @@ static void __init alchemy_setup_macs(int ctype)
|
|||
memcpy(au1xxx_eth0_platform_data.mac, ethaddr, 6);
|
||||
|
||||
ret = platform_device_register(&au1xxx_eth0_device);
|
||||
if (!ret)
|
||||
if (ret)
|
||||
printk(KERN_INFO "Alchemy: failed to register MAC0\n");
|
||||
|
||||
|
||||
|
|
|
@ -158,15 +158,21 @@ static void restore_core_regs(void)
|
|||
|
||||
void au_sleep(void)
|
||||
{
|
||||
int cpuid = alchemy_get_cputype();
|
||||
if (cpuid != ALCHEMY_CPU_UNKNOWN) {
|
||||
save_core_regs();
|
||||
if (cpuid <= ALCHEMY_CPU_AU1500)
|
||||
alchemy_sleep_au1000();
|
||||
else if (cpuid <= ALCHEMY_CPU_AU1200)
|
||||
alchemy_sleep_au1550();
|
||||
restore_core_regs();
|
||||
save_core_regs();
|
||||
|
||||
switch (alchemy_get_cputype()) {
|
||||
case ALCHEMY_CPU_AU1000:
|
||||
case ALCHEMY_CPU_AU1500:
|
||||
case ALCHEMY_CPU_AU1100:
|
||||
alchemy_sleep_au1000();
|
||||
break;
|
||||
case ALCHEMY_CPU_AU1550:
|
||||
case ALCHEMY_CPU_AU1200:
|
||||
alchemy_sleep_au1550();
|
||||
break;
|
||||
}
|
||||
|
||||
restore_core_regs();
|
||||
}
|
||||
|
||||
#endif /* CONFIG_PM */
|
||||
|
|
|
@ -89,8 +89,12 @@ static void bcsr_csc_handler(unsigned int irq, struct irq_desc *d)
|
|||
{
|
||||
unsigned short bisr = __raw_readw(bcsr_virt + BCSR_REG_INTSTAT);
|
||||
|
||||
disable_irq_nosync(irq);
|
||||
|
||||
for ( ; bisr; bisr &= bisr - 1)
|
||||
generic_handle_irq(bcsr_csc_base + __ffs(bisr));
|
||||
|
||||
enable_irq(irq);
|
||||
}
|
||||
|
||||
/* NOTE: both the enable and mask bits must be cleared, otherwise the
|
||||
|
|
|
@ -23,13 +23,6 @@ void __init board_setup(void)
|
|||
unsigned long freq0, clksrc, div, pfc;
|
||||
unsigned short whoami;
|
||||
|
||||
/* Set Config[OD] (disable overlapping bus transaction):
|
||||
* This gets rid of a _lot_ of spurious interrupts (especially
|
||||
* wrt. IDE); but incurs ~10% performance hit in some
|
||||
* cpu-bound applications.
|
||||
*/
|
||||
set_c0_config(1 << 19);
|
||||
|
||||
bcsr_init(DB1200_BCSR_PHYS_ADDR,
|
||||
DB1200_BCSR_PHYS_ADDR + DB1200_BCSR_HEXLED_OFS);
|
||||
|
||||
|
|
|
@ -98,7 +98,8 @@ static struct irq_chip ar7_sec_irq_type = {
|
|||
|
||||
static struct irqaction ar7_cascade_action = {
|
||||
.handler = no_action,
|
||||
.name = "AR7 cascade interrupt"
|
||||
.name = "AR7 cascade interrupt",
|
||||
.flags = IRQF_NO_THREAD,
|
||||
};
|
||||
|
||||
static void __init ar7_irq_init(int base)
|
||||
|
|
|
@ -222,6 +222,7 @@ static struct irq_chip bcm63xx_external_irq_chip = {
|
|||
static struct irqaction cpu_ip2_cascade_action = {
|
||||
.handler = no_action,
|
||||
.name = "cascade_ip2",
|
||||
.flags = IRQF_NO_THREAD,
|
||||
};
|
||||
|
||||
void __init arch_init_irq(void)
|
||||
|
|
|
@ -48,6 +48,7 @@ asmlinkage void plat_irq_dispatch(void)
|
|||
static struct irqaction cascade = {
|
||||
.handler = no_action,
|
||||
.name = "cascade",
|
||||
.flags = IRQF_NO_THREAD,
|
||||
};
|
||||
|
||||
void __init arch_init_irq(void)
|
||||
|
|
|
@ -101,20 +101,24 @@ int cpu_fpu_mask = DEC_CPU_IRQ_MASK(DEC_CPU_INR_FPU);
|
|||
static struct irqaction ioirq = {
|
||||
.handler = no_action,
|
||||
.name = "cascade",
|
||||
.flags = IRQF_NO_THREAD,
|
||||
};
|
||||
static struct irqaction fpuirq = {
|
||||
.handler = no_action,
|
||||
.name = "fpu",
|
||||
.flags = IRQF_NO_THREAD,
|
||||
};
|
||||
|
||||
static struct irqaction busirq = {
|
||||
.flags = IRQF_DISABLED,
|
||||
.name = "bus error",
|
||||
.flags = IRQF_NO_THREAD,
|
||||
};
|
||||
|
||||
static struct irqaction haltirq = {
|
||||
.handler = dec_intr_halt,
|
||||
.name = "halt",
|
||||
.flags = IRQF_NO_THREAD,
|
||||
};
|
||||
|
||||
|
||||
|
|
|
@ -169,7 +169,7 @@ void emma2rh_gpio_irq_init(void)
|
|||
|
||||
static struct irqaction irq_cascade = {
|
||||
.handler = no_action,
|
||||
.flags = 0,
|
||||
.flags = IRQF_NO_THREAD,
|
||||
.name = "cascade",
|
||||
.dev_id = NULL,
|
||||
.next = NULL,
|
||||
|
|
|
@ -54,7 +54,6 @@
|
|||
#define cpu_has_mips_r2_exec_hazard 0
|
||||
#define cpu_has_dsp 0
|
||||
#define cpu_has_mipsmt 0
|
||||
#define cpu_has_userlocal 0
|
||||
#define cpu_has_vint 0
|
||||
#define cpu_has_veic 0
|
||||
#define cpu_hwrena_impl_bits 0xc0000000
|
||||
|
|
|
@ -13,7 +13,6 @@
|
|||
#define __ASM_MACH_POWERTV_DMA_COHERENCE_H
|
||||
|
||||
#include <linux/sched.h>
|
||||
#include <linux/version.h>
|
||||
#include <linux/device.h>
|
||||
#include <asm/mach-powertv/asic.h>
|
||||
|
||||
|
|
|
@ -195,9 +195,9 @@
|
|||
* to cover the pipeline delay.
|
||||
*/
|
||||
.set mips32
|
||||
mfc0 v1, CP0_TCSTATUS
|
||||
mfc0 k0, CP0_TCSTATUS
|
||||
.set mips0
|
||||
LONG_S v1, PT_TCSTATUS(sp)
|
||||
LONG_S k0, PT_TCSTATUS(sp)
|
||||
#endif /* CONFIG_MIPS_MT_SMTC */
|
||||
LONG_S $4, PT_R4(sp)
|
||||
LONG_S $5, PT_R5(sp)
|
||||
|
|
|
@ -18,7 +18,7 @@
|
|||
#include <linux/init.h>
|
||||
|
||||
#include <linux/spinlock.h>
|
||||
#include <linux/sysdev.h>
|
||||
#include <linux/syscore_ops.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/gpio.h>
|
||||
#include <linux/delay.h>
|
||||
|
@ -86,7 +86,6 @@ struct jz_gpio_chip {
|
|||
spinlock_t lock;
|
||||
|
||||
struct gpio_chip gpio_chip;
|
||||
struct sys_device sysdev;
|
||||
};
|
||||
|
||||
static struct jz_gpio_chip jz4740_gpio_chips[];
|
||||
|
@ -459,49 +458,47 @@ static struct jz_gpio_chip jz4740_gpio_chips[] = {
|
|||
JZ4740_GPIO_CHIP(D),
|
||||
};
|
||||
|
||||
static inline struct jz_gpio_chip *sysdev_to_chip(struct sys_device *dev)
|
||||
static void jz4740_gpio_suspend_chip(struct jz_gpio_chip *chip)
|
||||
{
|
||||
return container_of(dev, struct jz_gpio_chip, sysdev);
|
||||
}
|
||||
|
||||
static int jz4740_gpio_suspend(struct sys_device *dev, pm_message_t state)
|
||||
{
|
||||
struct jz_gpio_chip *chip = sysdev_to_chip(dev);
|
||||
|
||||
chip->suspend_mask = readl(chip->base + JZ_REG_GPIO_MASK);
|
||||
writel(~(chip->wakeup), chip->base + JZ_REG_GPIO_MASK_SET);
|
||||
writel(chip->wakeup, chip->base + JZ_REG_GPIO_MASK_CLEAR);
|
||||
}
|
||||
|
||||
static int jz4740_gpio_suspend(void)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(jz4740_gpio_chips); i++)
|
||||
jz4740_gpio_suspend_chip(&jz4740_gpio_chips[i]);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int jz4740_gpio_resume(struct sys_device *dev)
|
||||
static void jz4740_gpio_resume_chip(struct jz_gpio_chip *chip)
|
||||
{
|
||||
struct jz_gpio_chip *chip = sysdev_to_chip(dev);
|
||||
uint32_t mask = chip->suspend_mask;
|
||||
|
||||
writel(~mask, chip->base + JZ_REG_GPIO_MASK_CLEAR);
|
||||
writel(mask, chip->base + JZ_REG_GPIO_MASK_SET);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct sysdev_class jz4740_gpio_sysdev_class = {
|
||||
.name = "gpio",
|
||||
static void jz4740_gpio_resume(void)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = ARRAY_SIZE(jz4740_gpio_chips) - 1; i >= 0 ; i--)
|
||||
jz4740_gpio_resume_chip(&jz4740_gpio_chips[i]);
|
||||
}
|
||||
|
||||
static struct syscore_ops jz4740_gpio_syscore_ops = {
|
||||
.suspend = jz4740_gpio_suspend,
|
||||
.resume = jz4740_gpio_resume,
|
||||
};
|
||||
|
||||
static int jz4740_gpio_chip_init(struct jz_gpio_chip *chip, unsigned int id)
|
||||
static void jz4740_gpio_chip_init(struct jz_gpio_chip *chip, unsigned int id)
|
||||
{
|
||||
int ret, irq;
|
||||
|
||||
chip->sysdev.id = id;
|
||||
chip->sysdev.cls = &jz4740_gpio_sysdev_class;
|
||||
ret = sysdev_register(&chip->sysdev);
|
||||
|
||||
if (ret)
|
||||
return ret;
|
||||
int irq;
|
||||
|
||||
spin_lock_init(&chip->lock);
|
||||
|
||||
|
@ -519,22 +516,17 @@ static int jz4740_gpio_chip_init(struct jz_gpio_chip *chip, unsigned int id)
|
|||
irq_set_chip_and_handler(irq, &jz_gpio_irq_chip,
|
||||
handle_level_irq);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int __init jz4740_gpio_init(void)
|
||||
{
|
||||
unsigned int i;
|
||||
int ret;
|
||||
|
||||
ret = sysdev_class_register(&jz4740_gpio_sysdev_class);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(jz4740_gpio_chips); ++i)
|
||||
jz4740_gpio_chip_init(&jz4740_gpio_chips[i], i);
|
||||
|
||||
register_syscore_ops(&jz4740_gpio_syscore_ops);
|
||||
|
||||
printk(KERN_INFO "JZ4740 GPIO initialized\n");
|
||||
|
||||
return 0;
|
||||
|
|
|
@ -19,6 +19,26 @@
|
|||
|
||||
#include <asm-generic/sections.h>
|
||||
|
||||
#if defined(KBUILD_MCOUNT_RA_ADDRESS) && defined(CONFIG_32BIT)
|
||||
#define MCOUNT_OFFSET_INSNS 5
|
||||
#else
|
||||
#define MCOUNT_OFFSET_INSNS 4
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Check if the address is in kernel space
|
||||
*
|
||||
* Clone core_kernel_text() from kernel/extable.c, but doesn't call
|
||||
* init_kernel_text() for Ftrace doesn't trace functions in init sections.
|
||||
*/
|
||||
static inline int in_kernel_space(unsigned long ip)
|
||||
{
|
||||
if (ip >= (unsigned long)_stext &&
|
||||
ip <= (unsigned long)_etext)
|
||||
return 1;
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_DYNAMIC_FTRACE
|
||||
|
||||
#define JAL 0x0c000000 /* jump & link: ip --> ra, jump to target */
|
||||
|
@ -54,20 +74,6 @@ static inline void ftrace_dyn_arch_init_insns(void)
|
|||
#endif
|
||||
}
|
||||
|
||||
/*
|
||||
* Check if the address is in kernel space
|
||||
*
|
||||
* Clone core_kernel_text() from kernel/extable.c, but doesn't call
|
||||
* init_kernel_text() for Ftrace doesn't trace functions in init sections.
|
||||
*/
|
||||
static inline int in_kernel_space(unsigned long ip)
|
||||
{
|
||||
if (ip >= (unsigned long)_stext &&
|
||||
ip <= (unsigned long)_etext)
|
||||
return 1;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int ftrace_modify_code(unsigned long ip, unsigned int new_code)
|
||||
{
|
||||
int faulted;
|
||||
|
@ -112,11 +118,6 @@ static int ftrace_modify_code(unsigned long ip, unsigned int new_code)
|
|||
* 1: offset = 4 instructions
|
||||
*/
|
||||
|
||||
#if defined(KBUILD_MCOUNT_RA_ADDRESS) && defined(CONFIG_32BIT)
|
||||
#define MCOUNT_OFFSET_INSNS 5
|
||||
#else
|
||||
#define MCOUNT_OFFSET_INSNS 4
|
||||
#endif
|
||||
#define INSN_B_1F (0x10000000 | MCOUNT_OFFSET_INSNS)
|
||||
|
||||
int ftrace_make_nop(struct module *mod,
|
||||
|
|
|
@ -229,7 +229,7 @@ static void i8259A_shutdown(void)
|
|||
*/
|
||||
if (i8259A_auto_eoi >= 0) {
|
||||
outb(0xff, PIC_MASTER_IMR); /* mask all of 8259A-1 */
|
||||
outb(0xff, PIC_SLAVE_IMR); /* mask all of 8259A-1 */
|
||||
outb(0xff, PIC_SLAVE_IMR); /* mask all of 8259A-2 */
|
||||
}
|
||||
}
|
||||
|
||||
|
@ -295,6 +295,7 @@ static void init_8259A(int auto_eoi)
|
|||
static struct irqaction irq2 = {
|
||||
.handler = no_action,
|
||||
.name = "cascade",
|
||||
.flags = IRQF_NO_THREAD,
|
||||
};
|
||||
|
||||
static struct resource pic1_io_resource = {
|
||||
|
|
|
@ -349,3 +349,10 @@ SYSCALL_DEFINE6(32_fanotify_mark, int, fanotify_fd, unsigned int, flags,
|
|||
return sys_fanotify_mark(fanotify_fd, flags, merge_64(a3, a4),
|
||||
dfd, pathname);
|
||||
}
|
||||
|
||||
SYSCALL_DEFINE6(32_futex, u32 __user *, uaddr, int, op, u32, val,
|
||||
struct compat_timespec __user *, utime, u32 __user *, uaddr2,
|
||||
u32, val3)
|
||||
{
|
||||
return compat_sys_futex(uaddr, op, val, utime, uaddr2, val3);
|
||||
}
|
||||
|
|
|
@ -315,7 +315,7 @@ EXPORT(sysn32_call_table)
|
|||
PTR sys_fremovexattr
|
||||
PTR sys_tkill
|
||||
PTR sys_ni_syscall
|
||||
PTR compat_sys_futex
|
||||
PTR sys_32_futex
|
||||
PTR compat_sys_sched_setaffinity /* 6195 */
|
||||
PTR compat_sys_sched_getaffinity
|
||||
PTR sys_cacheflush
|
||||
|
|
|
@ -441,7 +441,7 @@ sys_call_table:
|
|||
PTR sys_fremovexattr /* 4235 */
|
||||
PTR sys_tkill
|
||||
PTR sys_sendfile64
|
||||
PTR compat_sys_futex
|
||||
PTR sys_32_futex
|
||||
PTR compat_sys_sched_setaffinity
|
||||
PTR compat_sys_sched_getaffinity /* 4240 */
|
||||
PTR compat_sys_io_setup
|
||||
|
|
|
@ -8,6 +8,7 @@
|
|||
* Copyright (C) 1999, 2000 Silicon Graphics, Inc.
|
||||
*/
|
||||
#include <linux/cache.h>
|
||||
#include <linux/irqflags.h>
|
||||
#include <linux/sched.h>
|
||||
#include <linux/mm.h>
|
||||
#include <linux/personality.h>
|
||||
|
@ -658,6 +659,8 @@ static void do_signal(struct pt_regs *regs)
|
|||
asmlinkage void do_notify_resume(struct pt_regs *regs, void *unused,
|
||||
__u32 thread_info_flags)
|
||||
{
|
||||
local_irq_enable();
|
||||
|
||||
/* deal with pending signal delivery */
|
||||
if (thread_info_flags & (_TIF_SIGPENDING | _TIF_RESTORE_SIGMASK))
|
||||
do_signal(regs);
|
||||
|
|
|
@ -14,6 +14,7 @@
|
|||
#include <linux/bug.h>
|
||||
#include <linux/compiler.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/mm.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/sched.h>
|
||||
|
@ -364,21 +365,26 @@ static int regs_to_trapnr(struct pt_regs *regs)
|
|||
return (regs->cp0_cause >> 2) & 0x1f;
|
||||
}
|
||||
|
||||
static DEFINE_SPINLOCK(die_lock);
|
||||
static DEFINE_RAW_SPINLOCK(die_lock);
|
||||
|
||||
void __noreturn die(const char *str, struct pt_regs *regs)
|
||||
{
|
||||
static int die_counter;
|
||||
int sig = SIGSEGV;
|
||||
#ifdef CONFIG_MIPS_MT_SMTC
|
||||
unsigned long dvpret = dvpe();
|
||||
unsigned long dvpret;
|
||||
#endif /* CONFIG_MIPS_MT_SMTC */
|
||||
|
||||
oops_enter();
|
||||
|
||||
if (notify_die(DIE_OOPS, str, regs, 0, regs_to_trapnr(regs), SIGSEGV) == NOTIFY_STOP)
|
||||
sig = 0;
|
||||
|
||||
console_verbose();
|
||||
spin_lock_irq(&die_lock);
|
||||
raw_spin_lock_irq(&die_lock);
|
||||
#ifdef CONFIG_MIPS_MT_SMTC
|
||||
dvpret = dvpe();
|
||||
#endif /* CONFIG_MIPS_MT_SMTC */
|
||||
bust_spinlocks(1);
|
||||
#ifdef CONFIG_MIPS_MT_SMTC
|
||||
mips_mt_regdump(dvpret);
|
||||
|
@ -387,7 +393,9 @@ void __noreturn die(const char *str, struct pt_regs *regs)
|
|||
printk("%s[#%d]:\n", str, ++die_counter);
|
||||
show_registers(regs);
|
||||
add_taint(TAINT_DIE);
|
||||
spin_unlock_irq(&die_lock);
|
||||
raw_spin_unlock_irq(&die_lock);
|
||||
|
||||
oops_exit();
|
||||
|
||||
if (in_interrupt())
|
||||
panic("Fatal exception in interrupt");
|
||||
|
|
|
@ -192,7 +192,7 @@ static struct tc *get_tc(int index)
|
|||
}
|
||||
spin_unlock(&vpecontrol.tc_list_lock);
|
||||
|
||||
return NULL;
|
||||
return res;
|
||||
}
|
||||
|
||||
/* allocate a vpe and associate it with this minor (or index) */
|
||||
|
|
|
@ -123,11 +123,10 @@ void ltq_enable_irq(struct irq_data *d)
|
|||
static unsigned int ltq_startup_eiu_irq(struct irq_data *d)
|
||||
{
|
||||
int i;
|
||||
int irq_nr = d->irq - INT_NUM_IRQ0;
|
||||
|
||||
ltq_enable_irq(d);
|
||||
for (i = 0; i < MAX_EIU; i++) {
|
||||
if (irq_nr == ltq_eiu_irq[i]) {
|
||||
if (d->irq == ltq_eiu_irq[i]) {
|
||||
/* low level - we should really handle set_type */
|
||||
ltq_eiu_w32(ltq_eiu_r32(LTQ_EIU_EXIN_C) |
|
||||
(0x6 << (i * 4)), LTQ_EIU_EXIN_C);
|
||||
|
@ -147,11 +146,10 @@ static unsigned int ltq_startup_eiu_irq(struct irq_data *d)
|
|||
static void ltq_shutdown_eiu_irq(struct irq_data *d)
|
||||
{
|
||||
int i;
|
||||
int irq_nr = d->irq - INT_NUM_IRQ0;
|
||||
|
||||
ltq_disable_irq(d);
|
||||
for (i = 0; i < MAX_EIU; i++) {
|
||||
if (irq_nr == ltq_eiu_irq[i]) {
|
||||
if (d->irq == ltq_eiu_irq[i]) {
|
||||
/* disable */
|
||||
ltq_eiu_w32(ltq_eiu_r32(LTQ_EIU_EXIN_INEN) & ~(1 << i),
|
||||
LTQ_EIU_EXIN_INEN);
|
||||
|
|
|
@ -10,7 +10,6 @@
|
|||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/version.h>
|
||||
#include <linux/ioport.h>
|
||||
|
||||
#include <lantiq_soc.h>
|
||||
|
|
|
@ -8,7 +8,6 @@
|
|||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/version.h>
|
||||
#include <linux/ioport.h>
|
||||
|
||||
#include <lantiq_soc.h>
|
||||
|
|
|
@ -105,6 +105,7 @@ asmlinkage void plat_irq_dispatch(void)
|
|||
static struct irqaction cascade = {
|
||||
.handler = no_action,
|
||||
.name = "cascade",
|
||||
.flags = IRQF_NO_THREAD,
|
||||
};
|
||||
|
||||
void __init arch_init_irq(void)
|
||||
|
|
|
@ -42,6 +42,7 @@ asmlinkage void mach_irq_dispatch(unsigned int pending)
|
|||
static struct irqaction cascade_irqaction = {
|
||||
.handler = no_action,
|
||||
.name = "cascade",
|
||||
.flags = IRQF_NO_THREAD,
|
||||
};
|
||||
|
||||
void __init mach_init_irq(void)
|
||||
|
|
|
@ -96,12 +96,13 @@ static irqreturn_t ip6_action(int cpl, void *dev_id)
|
|||
struct irqaction ip6_irqaction = {
|
||||
.handler = ip6_action,
|
||||
.name = "cascade",
|
||||
.flags = IRQF_SHARED,
|
||||
.flags = IRQF_SHARED | IRQF_NO_THREAD,
|
||||
};
|
||||
|
||||
struct irqaction cascade_irqaction = {
|
||||
.handler = no_action,
|
||||
.name = "cascade",
|
||||
.flags = IRQF_NO_THREAD,
|
||||
};
|
||||
|
||||
void __init mach_init_irq(void)
|
||||
|
|
|
@ -6,6 +6,7 @@
|
|||
* Copyright (C) 2011 Wind River Systems,
|
||||
* written by Ralf Baechle <ralf@linux-mips.org>
|
||||
*/
|
||||
#include <linux/compiler.h>
|
||||
#include <linux/errno.h>
|
||||
#include <linux/mm.h>
|
||||
#include <linux/mman.h>
|
||||
|
@ -15,12 +16,11 @@
|
|||
#include <linux/sched.h>
|
||||
|
||||
unsigned long shm_align_mask = PAGE_SIZE - 1; /* Sane caches */
|
||||
|
||||
EXPORT_SYMBOL(shm_align_mask);
|
||||
|
||||
/* gap between mmap and stack */
|
||||
#define MIN_GAP (128*1024*1024UL)
|
||||
#define MAX_GAP ((TASK_SIZE)/6*5)
|
||||
#define MAX_GAP ((TASK_SIZE)/6*5)
|
||||
|
||||
static int mmap_is_legacy(void)
|
||||
{
|
||||
|
@ -57,13 +57,13 @@ static inline unsigned long COLOUR_ALIGN_DOWN(unsigned long addr,
|
|||
return base - off;
|
||||
}
|
||||
|
||||
#define COLOUR_ALIGN(addr,pgoff) \
|
||||
#define COLOUR_ALIGN(addr, pgoff) \
|
||||
((((addr) + shm_align_mask) & ~shm_align_mask) + \
|
||||
(((pgoff) << PAGE_SHIFT) & shm_align_mask))
|
||||
|
||||
enum mmap_allocation_direction {UP, DOWN};
|
||||
|
||||
static unsigned long arch_get_unmapped_area_foo(struct file *filp,
|
||||
static unsigned long arch_get_unmapped_area_common(struct file *filp,
|
||||
unsigned long addr0, unsigned long len, unsigned long pgoff,
|
||||
unsigned long flags, enum mmap_allocation_direction dir)
|
||||
{
|
||||
|
@ -103,16 +103,16 @@ static unsigned long arch_get_unmapped_area_foo(struct file *filp,
|
|||
|
||||
vma = find_vma(mm, addr);
|
||||
if (TASK_SIZE - len >= addr &&
|
||||
(!vma || addr + len <= vma->vm_start))
|
||||
(!vma || addr + len <= vma->vm_start))
|
||||
return addr;
|
||||
}
|
||||
|
||||
if (dir == UP) {
|
||||
addr = mm->mmap_base;
|
||||
if (do_color_align)
|
||||
addr = COLOUR_ALIGN(addr, pgoff);
|
||||
else
|
||||
addr = PAGE_ALIGN(addr);
|
||||
if (do_color_align)
|
||||
addr = COLOUR_ALIGN(addr, pgoff);
|
||||
else
|
||||
addr = PAGE_ALIGN(addr);
|
||||
|
||||
for (vma = find_vma(current->mm, addr); ; vma = vma->vm_next) {
|
||||
/* At this point: (!vma || addr < vma->vm_end). */
|
||||
|
@ -131,28 +131,30 @@ static unsigned long arch_get_unmapped_area_foo(struct file *filp,
|
|||
mm->free_area_cache = mm->mmap_base;
|
||||
}
|
||||
|
||||
/* either no address requested or can't fit in requested address hole */
|
||||
/*
|
||||
* either no address requested, or the mapping can't fit into
|
||||
* the requested address hole
|
||||
*/
|
||||
addr = mm->free_area_cache;
|
||||
if (do_color_align) {
|
||||
unsigned long base =
|
||||
COLOUR_ALIGN_DOWN(addr - len, pgoff);
|
||||
|
||||
if (do_color_align) {
|
||||
unsigned long base =
|
||||
COLOUR_ALIGN_DOWN(addr - len, pgoff);
|
||||
addr = base + len;
|
||||
}
|
||||
}
|
||||
|
||||
/* make sure it can fit in the remaining address space */
|
||||
if (likely(addr > len)) {
|
||||
vma = find_vma(mm, addr - len);
|
||||
if (!vma || addr <= vma->vm_start) {
|
||||
/* remember the address as a hint for next time */
|
||||
return mm->free_area_cache = addr-len;
|
||||
/* cache the address as a hint for next time */
|
||||
return mm->free_area_cache = addr - len;
|
||||
}
|
||||
}
|
||||
|
||||
if (unlikely(mm->mmap_base < len))
|
||||
goto bottomup;
|
||||
|
||||
addr = mm->mmap_base-len;
|
||||
addr = mm->mmap_base - len;
|
||||
if (do_color_align)
|
||||
addr = COLOUR_ALIGN_DOWN(addr, pgoff);
|
||||
|
||||
|
@ -163,8 +165,8 @@ static unsigned long arch_get_unmapped_area_foo(struct file *filp,
|
|||
* return with success:
|
||||
*/
|
||||
vma = find_vma(mm, addr);
|
||||
if (likely(!vma || addr+len <= vma->vm_start)) {
|
||||
/* remember the address as a hint for next time */
|
||||
if (likely(!vma || addr + len <= vma->vm_start)) {
|
||||
/* cache the address as a hint for next time */
|
||||
return mm->free_area_cache = addr;
|
||||
}
|
||||
|
||||
|
@ -173,7 +175,7 @@ static unsigned long arch_get_unmapped_area_foo(struct file *filp,
|
|||
mm->cached_hole_size = vma->vm_start - addr;
|
||||
|
||||
/* try just below the current vma->vm_start */
|
||||
addr = vma->vm_start-len;
|
||||
addr = vma->vm_start - len;
|
||||
if (do_color_align)
|
||||
addr = COLOUR_ALIGN_DOWN(addr, pgoff);
|
||||
} while (likely(len < vma->vm_start));
|
||||
|
@ -201,7 +203,7 @@ bottomup:
|
|||
unsigned long arch_get_unmapped_area(struct file *filp, unsigned long addr0,
|
||||
unsigned long len, unsigned long pgoff, unsigned long flags)
|
||||
{
|
||||
return arch_get_unmapped_area_foo(filp,
|
||||
return arch_get_unmapped_area_common(filp,
|
||||
addr0, len, pgoff, flags, UP);
|
||||
}
|
||||
|
||||
|
@ -213,7 +215,7 @@ unsigned long arch_get_unmapped_area_topdown(struct file *filp,
|
|||
unsigned long addr0, unsigned long len, unsigned long pgoff,
|
||||
unsigned long flags)
|
||||
{
|
||||
return arch_get_unmapped_area_foo(filp,
|
||||
return arch_get_unmapped_area_common(filp,
|
||||
addr0, len, pgoff, flags, DOWN);
|
||||
}
|
||||
|
||||
|
|
|
@ -1759,14 +1759,13 @@ static void __cpuinit build_r3000_tlb_modify_handler(void)
|
|||
u32 *p = handle_tlbm;
|
||||
struct uasm_label *l = labels;
|
||||
struct uasm_reloc *r = relocs;
|
||||
struct work_registers wr;
|
||||
|
||||
memset(handle_tlbm, 0, sizeof(handle_tlbm));
|
||||
memset(labels, 0, sizeof(labels));
|
||||
memset(relocs, 0, sizeof(relocs));
|
||||
|
||||
build_r3000_tlbchange_handler_head(&p, K0, K1);
|
||||
build_pte_modifiable(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbm);
|
||||
build_pte_modifiable(&p, &r, K0, K1, -1, label_nopage_tlbm);
|
||||
uasm_i_nop(&p); /* load delay */
|
||||
build_make_write(&p, &r, K0, K1);
|
||||
build_r3000_pte_reload_tlbwi(&p, K0, K1);
|
||||
|
@ -1963,7 +1962,8 @@ static void __cpuinit build_r4000_tlb_load_handler(void)
|
|||
uasm_i_andi(&p, wr.r3, wr.r3, 2);
|
||||
uasm_il_beqz(&p, &r, wr.r3, label_tlbl_goaround2);
|
||||
}
|
||||
|
||||
if (PM_DEFAULT_MASK == 0)
|
||||
uasm_i_nop(&p);
|
||||
/*
|
||||
* We clobbered C0_PAGEMASK, restore it. On the other branch
|
||||
* it is restored in build_huge_tlb_write_entry.
|
||||
|
|
|
@ -350,12 +350,14 @@ unsigned int plat_ipi_resched_int_xlate(unsigned int cpu)
|
|||
|
||||
static struct irqaction i8259irq = {
|
||||
.handler = no_action,
|
||||
.name = "XT-PIC cascade"
|
||||
.name = "XT-PIC cascade",
|
||||
.flags = IRQF_NO_THREAD,
|
||||
};
|
||||
|
||||
static struct irqaction corehi_irqaction = {
|
||||
.handler = no_action,
|
||||
.name = "CoreHi"
|
||||
.name = "CoreHi",
|
||||
.flags = IRQF_NO_THREAD,
|
||||
};
|
||||
|
||||
static msc_irqmap_t __initdata msc_irqmap[] = {
|
||||
|
|
|
@ -2,4 +2,4 @@ obj-y += setup.o platform.o irq.o setup.o time.o
|
|||
obj-$(CONFIG_SMP) += smp.o smpboot.o
|
||||
obj-$(CONFIG_EARLY_PRINTK) += xlr_console.o
|
||||
|
||||
EXTRA_CFLAGS += -Werror
|
||||
ccflags-y += -Werror
|
||||
|
|
|
@ -171,8 +171,13 @@ static int __devinit ltq_pci_startup(struct ltq_pci_data *conf)
|
|||
u32 temp_buffer;
|
||||
|
||||
/* set clock to 33Mhz */
|
||||
ltq_cgu_w32(ltq_cgu_r32(LTQ_CGU_IFCCR) & ~0xf00000, LTQ_CGU_IFCCR);
|
||||
ltq_cgu_w32(ltq_cgu_r32(LTQ_CGU_IFCCR) | 0x800000, LTQ_CGU_IFCCR);
|
||||
if (ltq_is_ar9()) {
|
||||
ltq_cgu_w32(ltq_cgu_r32(LTQ_CGU_IFCCR) & ~0x1f00000, LTQ_CGU_IFCCR);
|
||||
ltq_cgu_w32(ltq_cgu_r32(LTQ_CGU_IFCCR) | 0xe00000, LTQ_CGU_IFCCR);
|
||||
} else {
|
||||
ltq_cgu_w32(ltq_cgu_r32(LTQ_CGU_IFCCR) & ~0xf00000, LTQ_CGU_IFCCR);
|
||||
ltq_cgu_w32(ltq_cgu_r32(LTQ_CGU_IFCCR) | 0x800000, LTQ_CGU_IFCCR);
|
||||
}
|
||||
|
||||
/* external or internal clock ? */
|
||||
if (conf->clock) {
|
||||
|
|
|
@ -215,7 +215,7 @@ static int __init rc32434_pci_init(void)
|
|||
rc32434_pcibridge_init();
|
||||
|
||||
io_map_base = ioremap(rc32434_res_pci_io1.start,
|
||||
resource_size(&rcrc32434_res_pci_io1));
|
||||
resource_size(&rc32434_res_pci_io1));
|
||||
|
||||
if (!io_map_base)
|
||||
return -ENOMEM;
|
||||
|
|
|
@ -108,12 +108,14 @@ asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
|
|||
|
||||
static struct irqaction cic_cascade_msp = {
|
||||
.handler = no_action,
|
||||
.name = "MSP CIC cascade"
|
||||
.name = "MSP CIC cascade",
|
||||
.flags = IRQF_NO_THREAD,
|
||||
};
|
||||
|
||||
static struct irqaction per_cascade_msp = {
|
||||
.handler = no_action,
|
||||
.name = "MSP PER cascade"
|
||||
.name = "MSP PER cascade",
|
||||
.flags = IRQF_NO_THREAD,
|
||||
};
|
||||
|
||||
void __init arch_init_irq(void)
|
||||
|
|
|
@ -167,7 +167,7 @@ static struct irq_chip level_irq_type = {
|
|||
|
||||
static struct irqaction gic_action = {
|
||||
.handler = no_action,
|
||||
.flags = IRQF_DISABLED,
|
||||
.flags = IRQF_DISABLED | IRQF_NO_THREAD,
|
||||
.name = "GIC",
|
||||
};
|
||||
|
||||
|
|
|
@ -155,32 +155,32 @@ static void __irq_entry indy_buserror_irq(void)
|
|||
|
||||
static struct irqaction local0_cascade = {
|
||||
.handler = no_action,
|
||||
.flags = IRQF_DISABLED,
|
||||
.flags = IRQF_DISABLED | IRQF_NO_THREAD,
|
||||
.name = "local0 cascade",
|
||||
};
|
||||
|
||||
static struct irqaction local1_cascade = {
|
||||
.handler = no_action,
|
||||
.flags = IRQF_DISABLED,
|
||||
.flags = IRQF_DISABLED | IRQF_NO_THREAD,
|
||||
.name = "local1 cascade",
|
||||
};
|
||||
|
||||
static struct irqaction buserr = {
|
||||
.handler = no_action,
|
||||
.flags = IRQF_DISABLED,
|
||||
.flags = IRQF_DISABLED | IRQF_NO_THREAD,
|
||||
.name = "Bus Error",
|
||||
};
|
||||
|
||||
static struct irqaction map0_cascade = {
|
||||
.handler = no_action,
|
||||
.flags = IRQF_DISABLED,
|
||||
.flags = IRQF_DISABLED | IRQF_NO_THREAD,
|
||||
.name = "mapable0 cascade",
|
||||
};
|
||||
|
||||
#ifdef USE_LIO3_IRQ
|
||||
static struct irqaction map1_cascade = {
|
||||
.handler = no_action,
|
||||
.flags = IRQF_DISABLED,
|
||||
.flags = IRQF_DISABLED | IRQF_NO_THREAD,
|
||||
.name = "mapable1 cascade",
|
||||
};
|
||||
#define SGI_INTERRUPTS SGINT_END
|
||||
|
|
|
@ -359,6 +359,7 @@ void sni_rm200_init_8259A(void)
|
|||
static struct irqaction sni_rm200_irq2 = {
|
||||
.handler = no_action,
|
||||
.name = "cascade",
|
||||
.flags = IRQF_NO_THREAD,
|
||||
};
|
||||
|
||||
static struct resource sni_rm200_pic1_resource = {
|
||||
|
|
|
@ -34,6 +34,7 @@ static irq_cascade_t irq_cascade[NR_IRQS] __cacheline_aligned;
|
|||
static struct irqaction cascade_irqaction = {
|
||||
.handler = no_action,
|
||||
.name = "cascade",
|
||||
.flags = IRQF_NO_THREAD,
|
||||
};
|
||||
|
||||
int cascade_irq(unsigned int irq, int (*get_irq)(unsigned int))
|
||||
|
|
|
@ -561,6 +561,20 @@ static struct pci_ops u4_pcie_pci_ops =
|
|||
.write = u4_pcie_write_config,
|
||||
};
|
||||
|
||||
static void __devinit pmac_pci_fixup_u4_of_node(struct pci_dev *dev)
|
||||
{
|
||||
/* Apple's device-tree "hides" the root complex virtual P2P bridge
|
||||
* on U4. However, Linux sees it, causing the PCI <-> OF matching
|
||||
* code to fail to properly match devices below it. This works around
|
||||
* it by setting the node of the bridge to point to the PHB node,
|
||||
* which is not entirely correct but fixes the matching code and
|
||||
* doesn't break anything else. It's also the simplest possible fix.
|
||||
*/
|
||||
if (dev->dev.of_node == NULL)
|
||||
dev->dev.of_node = pcibios_get_phb_of_node(dev->bus);
|
||||
}
|
||||
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_APPLE, 0x5b, pmac_pci_fixup_u4_of_node);
|
||||
|
||||
#endif /* CONFIG_PPC64 */
|
||||
|
||||
#ifdef CONFIG_PPC32
|
||||
|
|
|
@ -188,7 +188,8 @@ extern char elf_platform[];
|
|||
#define SET_PERSONALITY(ex) \
|
||||
do { \
|
||||
if (personality(current->personality) != PER_LINUX32) \
|
||||
set_personality(PER_LINUX); \
|
||||
set_personality(PER_LINUX | \
|
||||
(current->personality & ~PER_MASK)); \
|
||||
if ((ex).e_ident[EI_CLASS] == ELFCLASS32) \
|
||||
set_thread_flag(TIF_31BIT); \
|
||||
else \
|
||||
|
|
|
@ -303,15 +303,15 @@ int gmap_unmap_segment(struct gmap *gmap, unsigned long to, unsigned long len)
|
|||
/* Walk the guest addr space page table */
|
||||
table = gmap->table + (((to + off) >> 53) & 0x7ff);
|
||||
if (*table & _REGION_ENTRY_INV)
|
||||
return 0;
|
||||
goto out;
|
||||
table = (unsigned long *)(*table & _REGION_ENTRY_ORIGIN);
|
||||
table = table + (((to + off) >> 42) & 0x7ff);
|
||||
if (*table & _REGION_ENTRY_INV)
|
||||
return 0;
|
||||
goto out;
|
||||
table = (unsigned long *)(*table & _REGION_ENTRY_ORIGIN);
|
||||
table = table + (((to + off) >> 31) & 0x7ff);
|
||||
if (*table & _REGION_ENTRY_INV)
|
||||
return 0;
|
||||
goto out;
|
||||
table = (unsigned long *)(*table & _REGION_ENTRY_ORIGIN);
|
||||
table = table + (((to + off) >> 20) & 0x7ff);
|
||||
|
||||
|
@ -319,6 +319,7 @@ int gmap_unmap_segment(struct gmap *gmap, unsigned long to, unsigned long len)
|
|||
flush |= gmap_unlink_segment(gmap, table);
|
||||
*table = _SEGMENT_ENTRY_INV;
|
||||
}
|
||||
out:
|
||||
up_read(&gmap->mm->mmap_sem);
|
||||
if (flush)
|
||||
gmap_flush_tlb(gmap);
|
||||
|
|
|
@ -280,7 +280,7 @@ static inline unsigned long srmmu_hwprobe(unsigned long vaddr)
|
|||
return retval;
|
||||
}
|
||||
#else
|
||||
#define srmmu_hwprobe(addr) (srmmu_swprobe(addr, 0) & SRMMU_PTE_PMASK)
|
||||
#define srmmu_hwprobe(addr) srmmu_swprobe(addr, 0)
|
||||
#endif
|
||||
|
||||
static inline int
|
||||
|
|
|
@ -43,6 +43,8 @@
|
|||
#define SUN4V_CHIP_NIAGARA1 0x01
|
||||
#define SUN4V_CHIP_NIAGARA2 0x02
|
||||
#define SUN4V_CHIP_NIAGARA3 0x03
|
||||
#define SUN4V_CHIP_NIAGARA4 0x04
|
||||
#define SUN4V_CHIP_NIAGARA5 0x05
|
||||
#define SUN4V_CHIP_UNKNOWN 0xff
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
|
|
@ -66,6 +66,8 @@ static struct xor_block_template xor_block_niagara = {
|
|||
((tlb_type == hypervisor && \
|
||||
(sun4v_chip_type == SUN4V_CHIP_NIAGARA1 || \
|
||||
sun4v_chip_type == SUN4V_CHIP_NIAGARA2 || \
|
||||
sun4v_chip_type == SUN4V_CHIP_NIAGARA3)) ? \
|
||||
sun4v_chip_type == SUN4V_CHIP_NIAGARA3 || \
|
||||
sun4v_chip_type == SUN4V_CHIP_NIAGARA4 || \
|
||||
sun4v_chip_type == SUN4V_CHIP_NIAGARA5)) ? \
|
||||
&xor_block_niagara : \
|
||||
&xor_block_VIS)
|
||||
|
|
|
@ -481,6 +481,18 @@ static void __init sun4v_cpu_probe(void)
|
|||
sparc_pmu_type = "niagara3";
|
||||
break;
|
||||
|
||||
case SUN4V_CHIP_NIAGARA4:
|
||||
sparc_cpu_type = "UltraSparc T4 (Niagara4)";
|
||||
sparc_fpu_type = "UltraSparc T4 integrated FPU";
|
||||
sparc_pmu_type = "niagara4";
|
||||
break;
|
||||
|
||||
case SUN4V_CHIP_NIAGARA5:
|
||||
sparc_cpu_type = "UltraSparc T5 (Niagara5)";
|
||||
sparc_fpu_type = "UltraSparc T5 integrated FPU";
|
||||
sparc_pmu_type = "niagara5";
|
||||
break;
|
||||
|
||||
default:
|
||||
printk(KERN_WARNING "CPU: Unknown sun4v cpu type [%s]\n",
|
||||
prom_cpu_compatible);
|
||||
|
|
|
@ -325,6 +325,8 @@ static int iterate_cpu(struct cpuinfo_tree *t, unsigned int root_index)
|
|||
case SUN4V_CHIP_NIAGARA1:
|
||||
case SUN4V_CHIP_NIAGARA2:
|
||||
case SUN4V_CHIP_NIAGARA3:
|
||||
case SUN4V_CHIP_NIAGARA4:
|
||||
case SUN4V_CHIP_NIAGARA5:
|
||||
rover_inc_table = niagara_iterate_method;
|
||||
break;
|
||||
default:
|
||||
|
|
|
@ -133,7 +133,7 @@ prom_sun4v_name:
|
|||
prom_niagara_prefix:
|
||||
.asciz "SUNW,UltraSPARC-T"
|
||||
prom_sparc_prefix:
|
||||
.asciz "SPARC-T"
|
||||
.asciz "SPARC-"
|
||||
.align 4
|
||||
prom_root_compatible:
|
||||
.skip 64
|
||||
|
@ -396,7 +396,7 @@ sun4v_chip_type:
|
|||
or %g1, %lo(prom_cpu_compatible), %g1
|
||||
sethi %hi(prom_sparc_prefix), %g7
|
||||
or %g7, %lo(prom_sparc_prefix), %g7
|
||||
mov 7, %g3
|
||||
mov 6, %g3
|
||||
90: ldub [%g7], %g2
|
||||
ldub [%g1], %g4
|
||||
cmp %g2, %g4
|
||||
|
@ -408,10 +408,23 @@ sun4v_chip_type:
|
|||
|
||||
sethi %hi(prom_cpu_compatible), %g1
|
||||
or %g1, %lo(prom_cpu_compatible), %g1
|
||||
ldub [%g1 + 7], %g2
|
||||
ldub [%g1 + 6], %g2
|
||||
cmp %g2, 'T'
|
||||
be,pt %xcc, 70f
|
||||
cmp %g2, 'M'
|
||||
bne,pn %xcc, 4f
|
||||
nop
|
||||
|
||||
70: ldub [%g1 + 7], %g2
|
||||
cmp %g2, '3'
|
||||
be,pt %xcc, 5f
|
||||
mov SUN4V_CHIP_NIAGARA3, %g4
|
||||
cmp %g2, '4'
|
||||
be,pt %xcc, 5f
|
||||
mov SUN4V_CHIP_NIAGARA4, %g4
|
||||
cmp %g2, '5'
|
||||
be,pt %xcc, 5f
|
||||
mov SUN4V_CHIP_NIAGARA5, %g4
|
||||
ba,pt %xcc, 4f
|
||||
nop
|
||||
|
||||
|
@ -543,6 +556,12 @@ niagara_tlb_fixup:
|
|||
be,pt %xcc, niagara2_patch
|
||||
nop
|
||||
cmp %g1, SUN4V_CHIP_NIAGARA3
|
||||
be,pt %xcc, niagara2_patch
|
||||
nop
|
||||
cmp %g1, SUN4V_CHIP_NIAGARA4
|
||||
be,pt %xcc, niagara2_patch
|
||||
nop
|
||||
cmp %g1, SUN4V_CHIP_NIAGARA5
|
||||
be,pt %xcc, niagara2_patch
|
||||
nop
|
||||
|
||||
|
|
|
@ -230,7 +230,8 @@ static void pci_parse_of_addrs(struct platform_device *op,
|
|||
res = &dev->resource[(i - PCI_BASE_ADDRESS_0) >> 2];
|
||||
} else if (i == dev->rom_base_reg) {
|
||||
res = &dev->resource[PCI_ROM_RESOURCE];
|
||||
flags |= IORESOURCE_READONLY | IORESOURCE_CACHEABLE;
|
||||
flags |= IORESOURCE_READONLY | IORESOURCE_CACHEABLE
|
||||
| IORESOURCE_SIZEALIGN;
|
||||
} else {
|
||||
printk(KERN_ERR "PCI: bad cfg reg num 0x%x\n", i);
|
||||
continue;
|
||||
|
|
|
@ -380,8 +380,7 @@ void flush_thread(void)
|
|||
#endif
|
||||
}
|
||||
|
||||
/* Now, this task is no longer a kernel thread. */
|
||||
current->thread.current_ds = USER_DS;
|
||||
/* This task is no longer a kernel thread. */
|
||||
if (current->thread.flags & SPARC_FLAG_KTHREAD) {
|
||||
current->thread.flags &= ~SPARC_FLAG_KTHREAD;
|
||||
|
||||
|
|
|
@ -368,9 +368,6 @@ void flush_thread(void)
|
|||
|
||||
/* Clear FPU register state. */
|
||||
t->fpsaved[0] = 0;
|
||||
|
||||
if (get_thread_current_ds() != ASI_AIUS)
|
||||
set_fs(USER_DS);
|
||||
}
|
||||
|
||||
/* It's a bit more tricky when 64-bit tasks are involved... */
|
||||
|
|
|
@ -137,7 +137,7 @@ static void __init process_switch(char c)
|
|||
prom_halt();
|
||||
break;
|
||||
case 'p':
|
||||
/* Just ignore, this behavior is now the default. */
|
||||
prom_early_console.flags &= ~CON_BOOT;
|
||||
break;
|
||||
default:
|
||||
printk("Unknown boot switch (-%c)\n", c);
|
||||
|
|
|
@ -106,7 +106,7 @@ static void __init process_switch(char c)
|
|||
prom_halt();
|
||||
break;
|
||||
case 'p':
|
||||
/* Just ignore, this behavior is now the default. */
|
||||
prom_early_console.flags &= ~CON_BOOT;
|
||||
break;
|
||||
case 'P':
|
||||
/* Force UltraSPARC-III P-Cache on. */
|
||||
|
@ -425,10 +425,14 @@ static void __init init_sparc64_elf_hwcap(void)
|
|||
else if (tlb_type == hypervisor) {
|
||||
if (sun4v_chip_type == SUN4V_CHIP_NIAGARA1 ||
|
||||
sun4v_chip_type == SUN4V_CHIP_NIAGARA2 ||
|
||||
sun4v_chip_type == SUN4V_CHIP_NIAGARA3)
|
||||
sun4v_chip_type == SUN4V_CHIP_NIAGARA3 ||
|
||||
sun4v_chip_type == SUN4V_CHIP_NIAGARA4 ||
|
||||
sun4v_chip_type == SUN4V_CHIP_NIAGARA5)
|
||||
cap |= HWCAP_SPARC_BLKINIT;
|
||||
if (sun4v_chip_type == SUN4V_CHIP_NIAGARA2 ||
|
||||
sun4v_chip_type == SUN4V_CHIP_NIAGARA3)
|
||||
sun4v_chip_type == SUN4V_CHIP_NIAGARA3 ||
|
||||
sun4v_chip_type == SUN4V_CHIP_NIAGARA4 ||
|
||||
sun4v_chip_type == SUN4V_CHIP_NIAGARA5)
|
||||
cap |= HWCAP_SPARC_N2;
|
||||
}
|
||||
|
||||
|
@ -452,11 +456,15 @@ static void __init init_sparc64_elf_hwcap(void)
|
|||
if (sun4v_chip_type == SUN4V_CHIP_NIAGARA1)
|
||||
cap |= AV_SPARC_ASI_BLK_INIT;
|
||||
if (sun4v_chip_type == SUN4V_CHIP_NIAGARA2 ||
|
||||
sun4v_chip_type == SUN4V_CHIP_NIAGARA3)
|
||||
sun4v_chip_type == SUN4V_CHIP_NIAGARA3 ||
|
||||
sun4v_chip_type == SUN4V_CHIP_NIAGARA4 ||
|
||||
sun4v_chip_type == SUN4V_CHIP_NIAGARA5)
|
||||
cap |= (AV_SPARC_VIS | AV_SPARC_VIS2 |
|
||||
AV_SPARC_ASI_BLK_INIT |
|
||||
AV_SPARC_POPC);
|
||||
if (sun4v_chip_type == SUN4V_CHIP_NIAGARA3)
|
||||
if (sun4v_chip_type == SUN4V_CHIP_NIAGARA3 ||
|
||||
sun4v_chip_type == SUN4V_CHIP_NIAGARA4 ||
|
||||
sun4v_chip_type == SUN4V_CHIP_NIAGARA5)
|
||||
cap |= (AV_SPARC_VIS3 | AV_SPARC_HPC |
|
||||
AV_SPARC_FMAF);
|
||||
}
|
||||
|
|
|
@ -273,10 +273,7 @@ void do_sigreturn32(struct pt_regs *regs)
|
|||
case 1: set.sig[0] = seta[0] + (((long)seta[1]) << 32);
|
||||
}
|
||||
sigdelsetmask(&set, ~_BLOCKABLE);
|
||||
spin_lock_irq(¤t->sighand->siglock);
|
||||
current->blocked = set;
|
||||
recalc_sigpending();
|
||||
spin_unlock_irq(¤t->sighand->siglock);
|
||||
set_current_blocked(&set);
|
||||
return;
|
||||
|
||||
segv:
|
||||
|
@ -377,10 +374,7 @@ asmlinkage void do_rt_sigreturn32(struct pt_regs *regs)
|
|||
case 1: set.sig[0] = seta.sig[0] + (((long)seta.sig[1]) << 32);
|
||||
}
|
||||
sigdelsetmask(&set, ~_BLOCKABLE);
|
||||
spin_lock_irq(¤t->sighand->siglock);
|
||||
current->blocked = set;
|
||||
recalc_sigpending();
|
||||
spin_unlock_irq(¤t->sighand->siglock);
|
||||
set_current_blocked(&set);
|
||||
return;
|
||||
segv:
|
||||
force_sig(SIGSEGV, current);
|
||||
|
@ -782,6 +776,7 @@ static inline int handle_signal32(unsigned long signr, struct k_sigaction *ka,
|
|||
siginfo_t *info,
|
||||
sigset_t *oldset, struct pt_regs *regs)
|
||||
{
|
||||
sigset_t blocked;
|
||||
int err;
|
||||
|
||||
if (ka->sa.sa_flags & SA_SIGINFO)
|
||||
|
@ -792,12 +787,10 @@ static inline int handle_signal32(unsigned long signr, struct k_sigaction *ka,
|
|||
if (err)
|
||||
return err;
|
||||
|
||||
spin_lock_irq(¤t->sighand->siglock);
|
||||
sigorsets(¤t->blocked,¤t->blocked,&ka->sa.sa_mask);
|
||||
sigorsets(&blocked, ¤t->blocked, &ka->sa.sa_mask);
|
||||
if (!(ka->sa.sa_flags & SA_NOMASK))
|
||||
sigaddset(¤t->blocked,signr);
|
||||
recalc_sigpending();
|
||||
spin_unlock_irq(¤t->sighand->siglock);
|
||||
sigaddset(&blocked, signr);
|
||||
set_current_blocked(&blocked);
|
||||
|
||||
tracehook_signal_handler(signr, info, ka, regs, 0);
|
||||
|
||||
|
@ -881,7 +874,7 @@ void do_signal32(sigset_t *oldset, struct pt_regs * regs,
|
|||
*/
|
||||
if (current_thread_info()->status & TS_RESTORE_SIGMASK) {
|
||||
current_thread_info()->status &= ~TS_RESTORE_SIGMASK;
|
||||
sigprocmask(SIG_SETMASK, ¤t->saved_sigmask, NULL);
|
||||
set_current_blocked(¤t->saved_sigmask);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
@ -62,12 +62,13 @@ struct rt_signal_frame {
|
|||
|
||||
static int _sigpause_common(old_sigset_t set)
|
||||
{
|
||||
set &= _BLOCKABLE;
|
||||
spin_lock_irq(¤t->sighand->siglock);
|
||||
sigset_t blocked;
|
||||
|
||||
current->saved_sigmask = current->blocked;
|
||||
siginitset(¤t->blocked, set);
|
||||
recalc_sigpending();
|
||||
spin_unlock_irq(¤t->sighand->siglock);
|
||||
|
||||
set &= _BLOCKABLE;
|
||||
siginitset(&blocked, set);
|
||||
set_current_blocked(&blocked);
|
||||
|
||||
current->state = TASK_INTERRUPTIBLE;
|
||||
schedule();
|
||||
|
@ -139,10 +140,7 @@ asmlinkage void do_sigreturn(struct pt_regs *regs)
|
|||
goto segv_and_exit;
|
||||
|
||||
sigdelsetmask(&set, ~_BLOCKABLE);
|
||||
spin_lock_irq(¤t->sighand->siglock);
|
||||
current->blocked = set;
|
||||
recalc_sigpending();
|
||||
spin_unlock_irq(¤t->sighand->siglock);
|
||||
set_current_blocked(&set);
|
||||
return;
|
||||
|
||||
segv_and_exit:
|
||||
|
@ -209,10 +207,7 @@ asmlinkage void do_rt_sigreturn(struct pt_regs *regs)
|
|||
}
|
||||
|
||||
sigdelsetmask(&set, ~_BLOCKABLE);
|
||||
spin_lock_irq(¤t->sighand->siglock);
|
||||
current->blocked = set;
|
||||
recalc_sigpending();
|
||||
spin_unlock_irq(¤t->sighand->siglock);
|
||||
set_current_blocked(&set);
|
||||
return;
|
||||
segv:
|
||||
force_sig(SIGSEGV, current);
|
||||
|
@ -470,6 +465,7 @@ static inline int
|
|||
handle_signal(unsigned long signr, struct k_sigaction *ka,
|
||||
siginfo_t *info, sigset_t *oldset, struct pt_regs *regs)
|
||||
{
|
||||
sigset_t blocked;
|
||||
int err;
|
||||
|
||||
if (ka->sa.sa_flags & SA_SIGINFO)
|
||||
|
@ -480,12 +476,10 @@ handle_signal(unsigned long signr, struct k_sigaction *ka,
|
|||
if (err)
|
||||
return err;
|
||||
|
||||
spin_lock_irq(¤t->sighand->siglock);
|
||||
sigorsets(¤t->blocked,¤t->blocked,&ka->sa.sa_mask);
|
||||
sigorsets(&blocked, ¤t->blocked, &ka->sa.sa_mask);
|
||||
if (!(ka->sa.sa_flags & SA_NOMASK))
|
||||
sigaddset(¤t->blocked, signr);
|
||||
recalc_sigpending();
|
||||
spin_unlock_irq(¤t->sighand->siglock);
|
||||
sigaddset(&blocked, signr);
|
||||
set_current_blocked(&blocked);
|
||||
|
||||
tracehook_signal_handler(signr, info, ka, regs, 0);
|
||||
|
||||
|
@ -581,7 +575,7 @@ static void do_signal(struct pt_regs *regs, unsigned long orig_i0)
|
|||
*/
|
||||
if (test_thread_flag(TIF_RESTORE_SIGMASK)) {
|
||||
clear_thread_flag(TIF_RESTORE_SIGMASK);
|
||||
sigprocmask(SIG_SETMASK, ¤t->saved_sigmask, NULL);
|
||||
set_current_blocked(¤t->saved_sigmask);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
@ -70,10 +70,7 @@ asmlinkage void sparc64_set_context(struct pt_regs *regs)
|
|||
goto do_sigsegv;
|
||||
}
|
||||
sigdelsetmask(&set, ~_BLOCKABLE);
|
||||
spin_lock_irq(¤t->sighand->siglock);
|
||||
current->blocked = set;
|
||||
recalc_sigpending();
|
||||
spin_unlock_irq(¤t->sighand->siglock);
|
||||
set_current_blocked(&set);
|
||||
}
|
||||
if (test_thread_flag(TIF_32BIT)) {
|
||||
pc &= 0xffffffff;
|
||||
|
@ -242,12 +239,13 @@ struct rt_signal_frame {
|
|||
|
||||
static long _sigpause_common(old_sigset_t set)
|
||||
{
|
||||
set &= _BLOCKABLE;
|
||||
spin_lock_irq(¤t->sighand->siglock);
|
||||
sigset_t blocked;
|
||||
|
||||
current->saved_sigmask = current->blocked;
|
||||
siginitset(¤t->blocked, set);
|
||||
recalc_sigpending();
|
||||
spin_unlock_irq(¤t->sighand->siglock);
|
||||
|
||||
set &= _BLOCKABLE;
|
||||
siginitset(&blocked, set);
|
||||
set_current_blocked(&blocked);
|
||||
|
||||
current->state = TASK_INTERRUPTIBLE;
|
||||
schedule();
|
||||
|
@ -327,10 +325,7 @@ void do_rt_sigreturn(struct pt_regs *regs)
|
|||
pt_regs_clear_syscall(regs);
|
||||
|
||||
sigdelsetmask(&set, ~_BLOCKABLE);
|
||||
spin_lock_irq(¤t->sighand->siglock);
|
||||
current->blocked = set;
|
||||
recalc_sigpending();
|
||||
spin_unlock_irq(¤t->sighand->siglock);
|
||||
set_current_blocked(&set);
|
||||
return;
|
||||
segv:
|
||||
force_sig(SIGSEGV, current);
|
||||
|
@ -484,18 +479,17 @@ static inline int handle_signal(unsigned long signr, struct k_sigaction *ka,
|
|||
siginfo_t *info,
|
||||
sigset_t *oldset, struct pt_regs *regs)
|
||||
{
|
||||
sigset_t blocked;
|
||||
int err;
|
||||
|
||||
err = setup_rt_frame(ka, regs, signr, oldset,
|
||||
(ka->sa.sa_flags & SA_SIGINFO) ? info : NULL);
|
||||
if (err)
|
||||
return err;
|
||||
spin_lock_irq(¤t->sighand->siglock);
|
||||
sigorsets(¤t->blocked,¤t->blocked,&ka->sa.sa_mask);
|
||||
sigorsets(&blocked, ¤t->blocked, &ka->sa.sa_mask);
|
||||
if (!(ka->sa.sa_flags & SA_NOMASK))
|
||||
sigaddset(¤t->blocked,signr);
|
||||
recalc_sigpending();
|
||||
spin_unlock_irq(¤t->sighand->siglock);
|
||||
sigaddset(&blocked, signr);
|
||||
set_current_blocked(&blocked);
|
||||
|
||||
tracehook_signal_handler(signr, info, ka, regs, 0);
|
||||
|
||||
|
@ -601,7 +595,7 @@ static void do_signal(struct pt_regs *regs, unsigned long orig_i0)
|
|||
*/
|
||||
if (current_thread_info()->status & TS_RESTORE_SIGMASK) {
|
||||
current_thread_info()->status &= ~TS_RESTORE_SIGMASK;
|
||||
sigprocmask(SIG_SETMASK, ¤t->saved_sigmask, NULL);
|
||||
set_current_blocked(¤t->saved_sigmask);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
@ -511,6 +511,11 @@ static void __init read_obp_translations(void)
|
|||
for (i = 0; i < prom_trans_ents; i++)
|
||||
prom_trans[i].data &= ~0x0003fe0000000000UL;
|
||||
}
|
||||
|
||||
/* Force execute bit on. */
|
||||
for (i = 0; i < prom_trans_ents; i++)
|
||||
prom_trans[i].data |= (tlb_type == hypervisor ?
|
||||
_PAGE_EXEC_4V : _PAGE_EXEC_4U);
|
||||
}
|
||||
|
||||
static void __init hypervisor_tlb_lock(unsigned long vaddr,
|
||||
|
|
|
@ -162,7 +162,7 @@ ready:
|
|||
printk(KERN_INFO "swprobe: padde %x\n", paddr_calc);
|
||||
if (paddr)
|
||||
*paddr = paddr_calc;
|
||||
return paddrbase;
|
||||
return pte;
|
||||
}
|
||||
|
||||
void leon_flush_icache_all(void)
|
||||
|
|
|
@ -21,7 +21,7 @@
|
|||
#include <asm/ptrace.h>
|
||||
#include <asm/thread_info.h>
|
||||
#include <asm/irqflags.h>
|
||||
#include <linux/atomic.h>
|
||||
#include <asm/atomic_32.h>
|
||||
#include <asm/asm-offsets.h>
|
||||
#include <hv/hypervisor.h>
|
||||
#include <arch/abi.h>
|
||||
|
|
|
@ -70,7 +70,7 @@
|
|||
*/
|
||||
|
||||
#include <linux/linkage.h>
|
||||
#include <linux/atomic.h>
|
||||
#include <asm/atomic_32.h>
|
||||
#include <asm/page.h>
|
||||
#include <asm/processor.h>
|
||||
|
||||
|
|
|
@ -42,8 +42,11 @@ int mach_set_rtc_mmss(unsigned long nowtime)
|
|||
{
|
||||
int real_seconds, real_minutes, cmos_minutes;
|
||||
unsigned char save_control, save_freq_select;
|
||||
unsigned long flags;
|
||||
int retval = 0;
|
||||
|
||||
spin_lock_irqsave(&rtc_lock, flags);
|
||||
|
||||
/* tell the clock it's being set */
|
||||
save_control = CMOS_READ(RTC_CONTROL);
|
||||
CMOS_WRITE((save_control|RTC_SET), RTC_CONTROL);
|
||||
|
@ -93,12 +96,17 @@ int mach_set_rtc_mmss(unsigned long nowtime)
|
|||
CMOS_WRITE(save_control, RTC_CONTROL);
|
||||
CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
|
||||
|
||||
spin_unlock_irqrestore(&rtc_lock, flags);
|
||||
|
||||
return retval;
|
||||
}
|
||||
|
||||
unsigned long mach_get_cmos_time(void)
|
||||
{
|
||||
unsigned int status, year, mon, day, hour, min, sec, century = 0;
|
||||
unsigned long flags;
|
||||
|
||||
spin_lock_irqsave(&rtc_lock, flags);
|
||||
|
||||
/*
|
||||
* If UIP is clear, then we have >= 244 microseconds before
|
||||
|
@ -125,6 +133,8 @@ unsigned long mach_get_cmos_time(void)
|
|||
status = CMOS_READ(RTC_CONTROL);
|
||||
WARN_ON_ONCE(RTC_ALWAYS_BCD && (status & RTC_DM_BINARY));
|
||||
|
||||
spin_unlock_irqrestore(&rtc_lock, flags);
|
||||
|
||||
if (RTC_ALWAYS_BCD || !(status & RTC_DM_BINARY)) {
|
||||
sec = bcd2bin(sec);
|
||||
min = bcd2bin(min);
|
||||
|
@ -169,24 +179,15 @@ EXPORT_SYMBOL(rtc_cmos_write);
|
|||
|
||||
int update_persistent_clock(struct timespec now)
|
||||
{
|
||||
unsigned long flags;
|
||||
int retval;
|
||||
|
||||
spin_lock_irqsave(&rtc_lock, flags);
|
||||
retval = x86_platform.set_wallclock(now.tv_sec);
|
||||
spin_unlock_irqrestore(&rtc_lock, flags);
|
||||
|
||||
return retval;
|
||||
return x86_platform.set_wallclock(now.tv_sec);
|
||||
}
|
||||
|
||||
/* not static: needed by APM */
|
||||
void read_persistent_clock(struct timespec *ts)
|
||||
{
|
||||
unsigned long retval, flags;
|
||||
unsigned long retval;
|
||||
|
||||
spin_lock_irqsave(&rtc_lock, flags);
|
||||
retval = x86_platform.get_wallclock();
|
||||
spin_unlock_irqrestore(&rtc_lock, flags);
|
||||
|
||||
ts->tv_sec = retval;
|
||||
ts->tv_nsec = 0;
|
||||
|
|
|
@ -56,7 +56,7 @@ DEFINE_VVAR(struct vsyscall_gtod_data, vsyscall_gtod_data) =
|
|||
.lock = __SEQLOCK_UNLOCKED(__vsyscall_gtod_data.lock),
|
||||
};
|
||||
|
||||
static enum { EMULATE, NATIVE, NONE } vsyscall_mode = EMULATE;
|
||||
static enum { EMULATE, NATIVE, NONE } vsyscall_mode = NATIVE;
|
||||
|
||||
static int __init vsyscall_setup(char *str)
|
||||
{
|
||||
|
|
|
@ -63,9 +63,8 @@ static void __init find_early_table_space(unsigned long end, int use_pse,
|
|||
#ifdef CONFIG_X86_32
|
||||
/* for fixmap */
|
||||
tables += roundup(__end_of_fixed_addresses * sizeof(pte_t), PAGE_SIZE);
|
||||
|
||||
good_end = max_pfn_mapped << PAGE_SHIFT;
|
||||
#endif
|
||||
good_end = max_pfn_mapped << PAGE_SHIFT;
|
||||
|
||||
base = memblock_find_in_range(start, good_end, tables, PAGE_SIZE);
|
||||
if (base == MEMBLOCK_ERROR)
|
||||
|
|
|
@ -43,6 +43,17 @@ static const struct dmi_system_id pci_use_crs_table[] __initconst = {
|
|||
DMI_MATCH(DMI_PRODUCT_NAME, "ALiveSATA2-GLAN"),
|
||||
},
|
||||
},
|
||||
/* https://bugzilla.kernel.org/show_bug.cgi?id=30552 */
|
||||
/* 2006 AMD HT/VIA system with two host bridges */
|
||||
{
|
||||
.callback = set_use_crs,
|
||||
.ident = "ASUS M2V-MX SE",
|
||||
.matches = {
|
||||
DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
|
||||
DMI_MATCH(DMI_BOARD_NAME, "M2V-MX SE"),
|
||||
DMI_MATCH(DMI_BIOS_VENDOR, "American Megatrends Inc."),
|
||||
},
|
||||
},
|
||||
{}
|
||||
};
|
||||
|
||||
|
|
|
@ -678,38 +678,40 @@ static int __init sfi_parse_devs(struct sfi_table_header *table)
|
|||
pentry = (struct sfi_device_table_entry *)sb->pentry;
|
||||
|
||||
for (i = 0; i < num; i++, pentry++) {
|
||||
if (pentry->irq != (u8)0xff) { /* native RTE case */
|
||||
int irq = pentry->irq;
|
||||
|
||||
if (irq != (u8)0xff) { /* native RTE case */
|
||||
/* these SPI2 devices are not exposed to system as PCI
|
||||
* devices, but they have separate RTE entry in IOAPIC
|
||||
* so we have to enable them one by one here
|
||||
*/
|
||||
ioapic = mp_find_ioapic(pentry->irq);
|
||||
ioapic = mp_find_ioapic(irq);
|
||||
irq_attr.ioapic = ioapic;
|
||||
irq_attr.ioapic_pin = pentry->irq;
|
||||
irq_attr.ioapic_pin = irq;
|
||||
irq_attr.trigger = 1;
|
||||
irq_attr.polarity = 1;
|
||||
io_apic_set_pci_routing(NULL, pentry->irq, &irq_attr);
|
||||
io_apic_set_pci_routing(NULL, irq, &irq_attr);
|
||||
} else
|
||||
pentry->irq = 0; /* No irq */
|
||||
irq = 0; /* No irq */
|
||||
|
||||
switch (pentry->type) {
|
||||
case SFI_DEV_TYPE_IPC:
|
||||
/* ID as IRQ is a hack that will go away */
|
||||
pdev = platform_device_alloc(pentry->name, pentry->irq);
|
||||
pdev = platform_device_alloc(pentry->name, irq);
|
||||
if (pdev == NULL) {
|
||||
pr_err("out of memory for SFI platform device '%s'.\n",
|
||||
pentry->name);
|
||||
continue;
|
||||
}
|
||||
install_irq_resource(pdev, pentry->irq);
|
||||
install_irq_resource(pdev, irq);
|
||||
pr_debug("info[%2d]: IPC bus, name = %16.16s, "
|
||||
"irq = 0x%2x\n", i, pentry->name, pentry->irq);
|
||||
"irq = 0x%2x\n", i, pentry->name, irq);
|
||||
sfi_handle_ipc_dev(pdev);
|
||||
break;
|
||||
case SFI_DEV_TYPE_SPI:
|
||||
memset(&spi_info, 0, sizeof(spi_info));
|
||||
strncpy(spi_info.modalias, pentry->name, SFI_NAME_LEN);
|
||||
spi_info.irq = pentry->irq;
|
||||
spi_info.irq = irq;
|
||||
spi_info.bus_num = pentry->host_num;
|
||||
spi_info.chip_select = pentry->addr;
|
||||
spi_info.max_speed_hz = pentry->max_freq;
|
||||
|
@ -726,7 +728,7 @@ static int __init sfi_parse_devs(struct sfi_table_header *table)
|
|||
memset(&i2c_info, 0, sizeof(i2c_info));
|
||||
bus = pentry->host_num;
|
||||
strncpy(i2c_info.type, pentry->name, SFI_NAME_LEN);
|
||||
i2c_info.irq = pentry->irq;
|
||||
i2c_info.irq = irq;
|
||||
i2c_info.addr = pentry->addr;
|
||||
pr_debug("info[%2d]: I2C bus = %d, name = %16.16s, "
|
||||
"irq = 0x%2x, addr = 0x%x\n", i, bus,
|
||||
|
|
|
@ -58,8 +58,11 @@ EXPORT_SYMBOL_GPL(vrtc_cmos_write);
|
|||
unsigned long vrtc_get_time(void)
|
||||
{
|
||||
u8 sec, min, hour, mday, mon;
|
||||
unsigned long flags;
|
||||
u32 year;
|
||||
|
||||
spin_lock_irqsave(&rtc_lock, flags);
|
||||
|
||||
while ((vrtc_cmos_read(RTC_FREQ_SELECT) & RTC_UIP))
|
||||
cpu_relax();
|
||||
|
||||
|
@ -70,6 +73,8 @@ unsigned long vrtc_get_time(void)
|
|||
mon = vrtc_cmos_read(RTC_MONTH);
|
||||
year = vrtc_cmos_read(RTC_YEAR);
|
||||
|
||||
spin_unlock_irqrestore(&rtc_lock, flags);
|
||||
|
||||
/* vRTC YEAR reg contains the offset to 1960 */
|
||||
year += 1960;
|
||||
|
||||
|
@ -83,8 +88,10 @@ unsigned long vrtc_get_time(void)
|
|||
int vrtc_set_mmss(unsigned long nowtime)
|
||||
{
|
||||
int real_sec, real_min;
|
||||
unsigned long flags;
|
||||
int vrtc_min;
|
||||
|
||||
spin_lock_irqsave(&rtc_lock, flags);
|
||||
vrtc_min = vrtc_cmos_read(RTC_MINUTES);
|
||||
|
||||
real_sec = nowtime % 60;
|
||||
|
@ -95,6 +102,8 @@ int vrtc_set_mmss(unsigned long nowtime)
|
|||
|
||||
vrtc_cmos_write(real_sec, RTC_SECONDS);
|
||||
vrtc_cmos_write(real_min, RTC_MINUTES);
|
||||
spin_unlock_irqrestore(&rtc_lock, flags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
|
@ -348,9 +348,10 @@ void blk_put_queue(struct request_queue *q)
|
|||
EXPORT_SYMBOL(blk_put_queue);
|
||||
|
||||
/*
|
||||
* Note: If a driver supplied the queue lock, it should not zap that lock
|
||||
* unexpectedly as some queue cleanup components like elevator_exit() and
|
||||
* blk_throtl_exit() need queue lock.
|
||||
* Note: If a driver supplied the queue lock, it is disconnected
|
||||
* by this function. The actual state of the lock doesn't matter
|
||||
* here as the request_queue isn't accessible after this point
|
||||
* (QUEUE_FLAG_DEAD is set) and no other requests will be queued.
|
||||
*/
|
||||
void blk_cleanup_queue(struct request_queue *q)
|
||||
{
|
||||
|
@ -367,10 +368,8 @@ void blk_cleanup_queue(struct request_queue *q)
|
|||
queue_flag_set_unlocked(QUEUE_FLAG_DEAD, q);
|
||||
mutex_unlock(&q->sysfs_lock);
|
||||
|
||||
if (q->elevator)
|
||||
elevator_exit(q->elevator);
|
||||
|
||||
blk_throtl_exit(q);
|
||||
if (q->queue_lock != &q->__queue_lock)
|
||||
q->queue_lock = &q->__queue_lock;
|
||||
|
||||
blk_put_queue(q);
|
||||
}
|
||||
|
|
|
@ -479,6 +479,11 @@ static void blk_release_queue(struct kobject *kobj)
|
|||
|
||||
blk_sync_queue(q);
|
||||
|
||||
if (q->elevator)
|
||||
elevator_exit(q->elevator);
|
||||
|
||||
blk_throtl_exit(q);
|
||||
|
||||
if (rl->rq_pool)
|
||||
mempool_destroy(rl->rq_pool);
|
||||
|
||||
|
|
|
@ -67,6 +67,9 @@ static int ghash_update(struct shash_desc *desc,
|
|||
struct ghash_ctx *ctx = crypto_shash_ctx(desc->tfm);
|
||||
u8 *dst = dctx->buffer;
|
||||
|
||||
if (!ctx->gf128)
|
||||
return -ENOKEY;
|
||||
|
||||
if (dctx->bytes) {
|
||||
int n = min(srclen, dctx->bytes);
|
||||
u8 *pos = dst + (GHASH_BLOCK_SIZE - dctx->bytes);
|
||||
|
@ -119,6 +122,9 @@ static int ghash_final(struct shash_desc *desc, u8 *dst)
|
|||
struct ghash_ctx *ctx = crypto_shash_ctx(desc->tfm);
|
||||
u8 *buf = dctx->buffer;
|
||||
|
||||
if (!ctx->gf128)
|
||||
return -ENOKEY;
|
||||
|
||||
ghash_flush(ctx, dctx);
|
||||
memcpy(dst, buf, GHASH_BLOCK_SIZE);
|
||||
|
||||
|
|
|
@ -34,8 +34,8 @@ struct gpio_bank {
|
|||
u16 irq;
|
||||
u16 virtual_irq_start;
|
||||
int method;
|
||||
#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
|
||||
u32 suspend_wakeup;
|
||||
#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
|
||||
u32 saved_wakeup;
|
||||
#endif
|
||||
u32 non_wakeup_gpios;
|
||||
|
|
|
@ -577,6 +577,7 @@ pca953x_get_alt_pdata(struct i2c_client *client, int *gpio_base, int *invert)
|
|||
void
|
||||
pca953x_get_alt_pdata(struct i2c_client *client, int *gpio_base, int *invert)
|
||||
{
|
||||
*gpio_base = -1;
|
||||
}
|
||||
#endif
|
||||
|
||||
|
|
|
@ -67,11 +67,11 @@ module_param_named(i915_enable_rc6, i915_enable_rc6, int, 0600);
|
|||
MODULE_PARM_DESC(i915_enable_rc6,
|
||||
"Enable power-saving render C-state 6 (default: true)");
|
||||
|
||||
unsigned int i915_enable_fbc __read_mostly = 1;
|
||||
unsigned int i915_enable_fbc __read_mostly = -1;
|
||||
module_param_named(i915_enable_fbc, i915_enable_fbc, int, 0600);
|
||||
MODULE_PARM_DESC(i915_enable_fbc,
|
||||
"Enable frame buffer compression for power savings "
|
||||
"(default: false)");
|
||||
"(default: -1 (use per-chip default))");
|
||||
|
||||
unsigned int i915_lvds_downclock __read_mostly = 0;
|
||||
module_param_named(lvds_downclock, i915_lvds_downclock, int, 0400);
|
||||
|
|
|
@ -1799,6 +1799,7 @@ static void intel_update_fbc(struct drm_device *dev)
|
|||
struct drm_framebuffer *fb;
|
||||
struct intel_framebuffer *intel_fb;
|
||||
struct drm_i915_gem_object *obj;
|
||||
int enable_fbc;
|
||||
|
||||
DRM_DEBUG_KMS("\n");
|
||||
|
||||
|
@ -1839,8 +1840,15 @@ static void intel_update_fbc(struct drm_device *dev)
|
|||
intel_fb = to_intel_framebuffer(fb);
|
||||
obj = intel_fb->obj;
|
||||
|
||||
if (!i915_enable_fbc) {
|
||||
DRM_DEBUG_KMS("fbc disabled per module param (default off)\n");
|
||||
enable_fbc = i915_enable_fbc;
|
||||
if (enable_fbc < 0) {
|
||||
DRM_DEBUG_KMS("fbc set to per-chip default\n");
|
||||
enable_fbc = 1;
|
||||
if (INTEL_INFO(dev)->gen <= 5)
|
||||
enable_fbc = 0;
|
||||
}
|
||||
if (!enable_fbc) {
|
||||
DRM_DEBUG_KMS("fbc disabled per module param\n");
|
||||
dev_priv->no_fbc_reason = FBC_MODULE_PARAM;
|
||||
goto out_disable;
|
||||
}
|
||||
|
@ -4687,13 +4695,13 @@ static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
|
|||
bpc = 6; /* min is 18bpp */
|
||||
break;
|
||||
case 24:
|
||||
bpc = min((unsigned int)8, display_bpc);
|
||||
bpc = 8;
|
||||
break;
|
||||
case 30:
|
||||
bpc = min((unsigned int)10, display_bpc);
|
||||
bpc = 10;
|
||||
break;
|
||||
case 48:
|
||||
bpc = min((unsigned int)12, display_bpc);
|
||||
bpc = 12;
|
||||
break;
|
||||
default:
|
||||
DRM_DEBUG("unsupported depth, assuming 24 bits\n");
|
||||
|
@ -4701,10 +4709,12 @@ static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
|
|||
break;
|
||||
}
|
||||
|
||||
display_bpc = min(display_bpc, bpc);
|
||||
|
||||
DRM_DEBUG_DRIVER("setting pipe bpc to %d (max display bpc %d)\n",
|
||||
bpc, display_bpc);
|
||||
|
||||
*pipe_bpp = bpc * 3;
|
||||
*pipe_bpp = display_bpc * 3;
|
||||
|
||||
return display_bpc != bpc;
|
||||
}
|
||||
|
|
Some files were not shown because too many files have changed in this diff Show more
Loading…
Reference in a new issue