ARM: at91: drop sam9_smc.c
sam9_smc.c has no users anymore, remove it along with both sam9_smc.h and mach/at91sam9_smc.h Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>steinar/wifi_calib_4_9_kernel
Alexandre Belloni
parent
5a90f8d3b1
commit
b8ccd9c39a
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@ -6,8 +6,6 @@ asflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include
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obj-y := soc.o
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obj-$(CONFIG_SOC_AT91SAM9) += sam9_smc.o
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# CPU-specific support
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obj-$(CONFIG_SOC_AT91RM9200) += at91rm9200.o
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obj-$(CONFIG_SOC_AT91SAM9) += at91sam9.o
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@ -1,98 +0,0 @@
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/*
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* arch/arm/mach-at91/include/mach/at91sam9_smc.h
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*
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* Copyright (C) 2007 Andrew Victor
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* Copyright (C) 2007 Atmel Corporation.
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*
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* Static Memory Controllers (SMC) - System peripherals registers.
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* Based on AT91SAM9261 datasheet revision D.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#ifndef AT91SAM9_SMC_H
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#define AT91SAM9_SMC_H
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#ifndef __ASSEMBLY__
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struct sam9_smc_config {
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/* Setup register */
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u8 ncs_read_setup;
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u8 nrd_setup;
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u8 ncs_write_setup;
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u8 nwe_setup;
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/* Pulse register */
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u8 ncs_read_pulse;
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u8 nrd_pulse;
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u8 ncs_write_pulse;
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u8 nwe_pulse;
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/* Cycle register */
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u16 read_cycle;
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u16 write_cycle;
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/* Mode register */
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u32 mode;
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u8 tdf_cycles:4;
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};
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extern void sam9_smc_configure(int id, int cs, struct sam9_smc_config *config);
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extern void sam9_smc_read(int id, int cs, struct sam9_smc_config *config);
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extern void sam9_smc_read_mode(int id, int cs, struct sam9_smc_config *config);
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extern void sam9_smc_write_mode(int id, int cs, struct sam9_smc_config *config);
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#endif
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#define AT91_SMC_SETUP 0x00 /* Setup Register for CS n */
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#define AT91_SMC_NWESETUP (0x3f << 0) /* NWE Setup Length */
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#define AT91_SMC_NWESETUP_(x) ((x) << 0)
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#define AT91_SMC_NCS_WRSETUP (0x3f << 8) /* NCS Setup Length in Write Access */
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#define AT91_SMC_NCS_WRSETUP_(x) ((x) << 8)
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#define AT91_SMC_NRDSETUP (0x3f << 16) /* NRD Setup Length */
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#define AT91_SMC_NRDSETUP_(x) ((x) << 16)
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#define AT91_SMC_NCS_RDSETUP (0x3f << 24) /* NCS Setup Length in Read Access */
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#define AT91_SMC_NCS_RDSETUP_(x) ((x) << 24)
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#define AT91_SMC_PULSE 0x04 /* Pulse Register for CS n */
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#define AT91_SMC_NWEPULSE (0x7f << 0) /* NWE Pulse Length */
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#define AT91_SMC_NWEPULSE_(x) ((x) << 0)
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#define AT91_SMC_NCS_WRPULSE (0x7f << 8) /* NCS Pulse Length in Write Access */
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#define AT91_SMC_NCS_WRPULSE_(x)((x) << 8)
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#define AT91_SMC_NRDPULSE (0x7f << 16) /* NRD Pulse Length */
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#define AT91_SMC_NRDPULSE_(x) ((x) << 16)
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#define AT91_SMC_NCS_RDPULSE (0x7f << 24) /* NCS Pulse Length in Read Access */
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#define AT91_SMC_NCS_RDPULSE_(x)((x) << 24)
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#define AT91_SMC_CYCLE 0x08 /* Cycle Register for CS n */
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#define AT91_SMC_NWECYCLE (0x1ff << 0 ) /* Total Write Cycle Length */
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#define AT91_SMC_NWECYCLE_(x) ((x) << 0)
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#define AT91_SMC_NRDCYCLE (0x1ff << 16) /* Total Read Cycle Length */
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#define AT91_SMC_NRDCYCLE_(x) ((x) << 16)
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#define AT91_SMC_MODE 0x0c /* Mode Register for CS n */
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#define AT91_SMC_READMODE (1 << 0) /* Read Mode */
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#define AT91_SMC_WRITEMODE (1 << 1) /* Write Mode */
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#define AT91_SMC_EXNWMODE (3 << 4) /* NWAIT Mode */
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#define AT91_SMC_EXNWMODE_DISABLE (0 << 4)
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#define AT91_SMC_EXNWMODE_FROZEN (2 << 4)
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#define AT91_SMC_EXNWMODE_READY (3 << 4)
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#define AT91_SMC_BAT (1 << 8) /* Byte Access Type */
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#define AT91_SMC_BAT_SELECT (0 << 8)
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#define AT91_SMC_BAT_WRITE (1 << 8)
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#define AT91_SMC_DBW (3 << 12) /* Data Bus Width */
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#define AT91_SMC_DBW_8 (0 << 12)
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#define AT91_SMC_DBW_16 (1 << 12)
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#define AT91_SMC_DBW_32 (2 << 12)
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#define AT91_SMC_TDF (0xf << 16) /* Data Float Time. */
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#define AT91_SMC_TDF_(x) ((x) << 16)
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#define AT91_SMC_TDFMODE (1 << 20) /* TDF Optimization - Enabled */
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#define AT91_SMC_PMEN (1 << 24) /* Page Mode Enabled */
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#define AT91_SMC_PS (3 << 28) /* Page Size */
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#define AT91_SMC_PS_4 (0 << 28)
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#define AT91_SMC_PS_8 (1 << 28)
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#define AT91_SMC_PS_16 (2 << 28)
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#define AT91_SMC_PS_32 (3 << 28)
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#endif
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@ -1,136 +0,0 @@
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/*
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* linux/arch/arm/mach-at91/sam9_smc.c
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*
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* Copyright (C) 2008 Andrew Victor
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* Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/module.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <mach/at91sam9_smc.h>
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#include "sam9_smc.h"
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#define AT91_SMC_CS(id, n) (smc_base_addr[id] + ((n) * 0x10))
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static void __iomem *smc_base_addr[2];
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static void sam9_smc_cs_write_mode(void __iomem *base,
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struct sam9_smc_config *config)
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{
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__raw_writel(config->mode
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| AT91_SMC_TDF_(config->tdf_cycles),
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base + AT91_SMC_MODE);
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}
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void sam9_smc_write_mode(int id, int cs,
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struct sam9_smc_config *config)
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{
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sam9_smc_cs_write_mode(AT91_SMC_CS(id, cs), config);
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}
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EXPORT_SYMBOL_GPL(sam9_smc_write_mode);
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static void sam9_smc_cs_configure(void __iomem *base,
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struct sam9_smc_config *config)
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{
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/* Setup register */
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__raw_writel(AT91_SMC_NWESETUP_(config->nwe_setup)
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| AT91_SMC_NCS_WRSETUP_(config->ncs_write_setup)
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| AT91_SMC_NRDSETUP_(config->nrd_setup)
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| AT91_SMC_NCS_RDSETUP_(config->ncs_read_setup),
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base + AT91_SMC_SETUP);
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/* Pulse register */
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__raw_writel(AT91_SMC_NWEPULSE_(config->nwe_pulse)
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| AT91_SMC_NCS_WRPULSE_(config->ncs_write_pulse)
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| AT91_SMC_NRDPULSE_(config->nrd_pulse)
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| AT91_SMC_NCS_RDPULSE_(config->ncs_read_pulse),
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base + AT91_SMC_PULSE);
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/* Cycle register */
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__raw_writel(AT91_SMC_NWECYCLE_(config->write_cycle)
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| AT91_SMC_NRDCYCLE_(config->read_cycle),
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base + AT91_SMC_CYCLE);
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/* Mode register */
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sam9_smc_cs_write_mode(base, config);
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}
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void sam9_smc_configure(int id, int cs,
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struct sam9_smc_config *config)
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{
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sam9_smc_cs_configure(AT91_SMC_CS(id, cs), config);
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}
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EXPORT_SYMBOL_GPL(sam9_smc_configure);
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static void sam9_smc_cs_read_mode(void __iomem *base,
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struct sam9_smc_config *config)
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{
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u32 val = __raw_readl(base + AT91_SMC_MODE);
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config->mode = (val & ~AT91_SMC_NWECYCLE);
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config->tdf_cycles = (val & AT91_SMC_NWECYCLE) >> 16 ;
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}
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void sam9_smc_read_mode(int id, int cs,
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struct sam9_smc_config *config)
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{
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sam9_smc_cs_read_mode(AT91_SMC_CS(id, cs), config);
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}
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EXPORT_SYMBOL_GPL(sam9_smc_read_mode);
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static void sam9_smc_cs_read(void __iomem *base,
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struct sam9_smc_config *config)
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{
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u32 val;
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/* Setup register */
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val = __raw_readl(base + AT91_SMC_SETUP);
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config->nwe_setup = val & AT91_SMC_NWESETUP;
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config->ncs_write_setup = (val & AT91_SMC_NCS_WRSETUP) >> 8;
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config->nrd_setup = (val & AT91_SMC_NRDSETUP) >> 16;
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config->ncs_read_setup = (val & AT91_SMC_NCS_RDSETUP) >> 24;
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/* Pulse register */
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val = __raw_readl(base + AT91_SMC_PULSE);
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config->nwe_pulse = val & AT91_SMC_NWEPULSE;
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config->ncs_write_pulse = (val & AT91_SMC_NCS_WRPULSE) >> 8;
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config->nrd_pulse = (val & AT91_SMC_NRDPULSE) >> 16;
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config->ncs_read_pulse = (val & AT91_SMC_NCS_RDPULSE) >> 24;
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/* Cycle register */
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val = __raw_readl(base + AT91_SMC_CYCLE);
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config->write_cycle = val & AT91_SMC_NWECYCLE;
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config->read_cycle = (val & AT91_SMC_NRDCYCLE) >> 16;
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/* Mode register */
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sam9_smc_cs_read_mode(base, config);
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}
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void sam9_smc_read(int id, int cs, struct sam9_smc_config *config)
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{
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sam9_smc_cs_read(AT91_SMC_CS(id, cs), config);
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}
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void __init at91sam9_ioremap_smc(int id, u32 addr)
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{
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if (id > 1) {
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pr_warn("%s: id > 2\n", __func__);
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return;
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}
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smc_base_addr[id] = ioremap(addr, 512);
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if (!smc_base_addr[id])
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pr_warn("Impossible to ioremap smc.%d 0x%x\n", id, addr);
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}
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@ -1,11 +0,0 @@
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/*
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* linux/arch/arm/mach-at91/sam9_smc.
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*
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* Copyright (C) 2008 Andrew Victor
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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extern void __init at91sam9_ioremap_smc(int id, u32 addr);
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