locking/arch: Rename set_mb() to smp_store_mb()
Since set_mb() is really about an smp_mb() -- not a IO/DMA barrier like mb() rename it to match the recent smp_load_acquire() and smp_store_release(). Suggested-by: Linus Torvalds <torvalds@linux-foundation.org> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: linux-kernel@vger.kernel.org Signed-off-by: Ingo Molnar <mingo@kernel.org>
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@ -1662,7 +1662,7 @@ CPU from reordering them.
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There are some more advanced barrier functions:
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(*) set_mb(var, value)
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(*) smp_store_mb(var, value)
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This assigns the value to the variable and then inserts a full memory
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barrier after it, depending on the function. It isn't guaranteed to
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@ -1975,7 +1975,7 @@ after it has altered the task state:
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CPU 1
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===============================
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set_current_state();
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set_mb();
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smp_store_mb();
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STORE current->state
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<general barrier>
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LOAD event_indicated
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@ -2016,7 +2016,7 @@ between the STORE to indicate the event and the STORE to set TASK_RUNNING:
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CPU 1 CPU 2
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=============================== ===============================
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set_current_state(); STORE event_indicated
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set_mb(); wake_up();
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smp_store_mb(); wake_up();
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STORE current->state <write barrier>
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<general barrier> STORE current->state
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LOAD event_indicated
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@ -81,7 +81,7 @@ do { \
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#define read_barrier_depends() do { } while(0)
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#define smp_read_barrier_depends() do { } while(0)
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#define set_mb(var, value) do { WRITE_ONCE(var, value); smp_mb(); } while (0)
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#define smp_store_mb(var, value) do { WRITE_ONCE(var, value); smp_mb(); } while (0)
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#define smp_mb__before_atomic() smp_mb()
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#define smp_mb__after_atomic() smp_mb()
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@ -114,7 +114,7 @@ do { \
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#define read_barrier_depends() do { } while(0)
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#define smp_read_barrier_depends() do { } while(0)
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#define set_mb(var, value) do { WRITE_ONCE(var, value); smp_mb(); } while (0)
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#define smp_store_mb(var, value) do { WRITE_ONCE(var, value); smp_mb(); } while (0)
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#define nop() asm volatile("nop");
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#define smp_mb__before_atomic() smp_mb()
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@ -77,12 +77,7 @@ do { \
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___p1; \
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})
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/*
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* XXX check on this ---I suspect what Linus really wants here is
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* acquire vs release semantics but we can't discuss this stuff with
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* Linus just yet. Grrr...
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*/
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#define set_mb(var, value) do { WRITE_ONCE(var, value); mb(); } while (0)
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#define smp_store_mb(var, value) do { WRITE_ONCE(var, value); mb(); } while (0)
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/*
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* The group barrier in front of the rsm & ssm are necessary to ensure
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@ -84,7 +84,7 @@ static inline void fence(void)
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#define read_barrier_depends() do { } while (0)
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#define smp_read_barrier_depends() do { } while (0)
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#define set_mb(var, value) do { WRITE_ONCE(var, value); smp_mb(); } while (0)
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#define smp_store_mb(var, value) do { WRITE_ONCE(var, value); smp_mb(); } while (0)
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#define smp_store_release(p, v) \
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do { \
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@ -112,7 +112,7 @@
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#define __WEAK_LLSC_MB " \n"
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#endif
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#define set_mb(var, value) \
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#define smp_store_mb(var, value) \
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do { WRITE_ONCE(var, value); smp_mb(); } while (0)
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#define smp_llsc_mb() __asm__ __volatile__(__WEAK_LLSC_MB : : :"memory")
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@ -34,7 +34,7 @@
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#define rmb() __asm__ __volatile__ ("sync" : : : "memory")
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#define wmb() __asm__ __volatile__ ("sync" : : : "memory")
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#define set_mb(var, value) do { WRITE_ONCE(var, value); mb(); } while (0)
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#define smp_store_mb(var, value) do { WRITE_ONCE(var, value); mb(); } while (0)
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#ifdef __SUBARCH_HAS_LWSYNC
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# define SMPWMB LWSYNC
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@ -36,7 +36,7 @@
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#define smp_mb__before_atomic() smp_mb()
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#define smp_mb__after_atomic() smp_mb()
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#define set_mb(var, value) do { WRITE_ONCE(var, value); mb(); } while (0)
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#define smp_store_mb(var, value) do { WRITE_ONCE(var, value); mb(); } while (0)
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#define smp_store_release(p, v) \
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do { \
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@ -32,7 +32,7 @@
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#define ctrl_barrier() __asm__ __volatile__ ("nop;nop;nop;nop;nop;nop;nop;nop")
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#endif
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#define set_mb(var, value) do { (void)xchg(&var, value); } while (0)
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#define smp_store_mb(var, value) do { (void)xchg(&var, value); } while (0)
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#include <asm-generic/barrier.h>
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@ -40,7 +40,7 @@ do { __asm__ __volatile__("ba,pt %%xcc, 1f\n\t" \
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#define dma_rmb() rmb()
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#define dma_wmb() wmb()
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#define set_mb(__var, __value) \
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#define smp_store_mb(__var, __value) \
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do { WRITE_ONCE(__var, __value); membar_safe("#StoreLoad"); } while(0)
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#ifdef CONFIG_SMP
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@ -35,12 +35,12 @@
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#define smp_mb() mb()
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#define smp_rmb() dma_rmb()
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#define smp_wmb() barrier()
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#define set_mb(var, value) do { (void)xchg(&var, value); } while (0)
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#define smp_store_mb(var, value) do { (void)xchg(&var, value); } while (0)
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#else /* !SMP */
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#define smp_mb() barrier()
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#define smp_rmb() barrier()
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#define smp_wmb() barrier()
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#define set_mb(var, value) do { WRITE_ONCE(var, value); barrier(); } while (0)
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#define smp_store_mb(var, value) do { WRITE_ONCE(var, value); barrier(); } while (0)
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#endif /* SMP */
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#define read_barrier_depends() do { } while (0)
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@ -39,7 +39,8 @@
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#define smp_mb() barrier()
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#define smp_rmb() barrier()
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#define smp_wmb() barrier()
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#define set_mb(var, value) do { WRITE_ONCE(var, value); barrier(); } while (0)
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#define smp_store_mb(var, value) do { WRITE_ONCE(var, value); barrier(); } while (0)
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#define read_barrier_depends() do { } while (0)
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#define smp_read_barrier_depends() do { } while (0)
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@ -189,7 +189,7 @@ static int __pollwake(wait_queue_t *wait, unsigned mode, int sync, void *key)
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* doesn't imply write barrier and the users expect write
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* barrier semantics on wakeup functions. The following
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* smp_wmb() is equivalent to smp_wmb() in try_to_wake_up()
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* and is paired with set_mb() in poll_schedule_timeout.
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* and is paired with smp_store_mb() in poll_schedule_timeout.
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*/
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smp_wmb();
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pwq->triggered = 1;
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@ -244,7 +244,7 @@ int poll_schedule_timeout(struct poll_wqueues *pwq, int state,
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/*
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* Prepare for the next iteration.
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*
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* The following set_mb() serves two purposes. First, it's
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* The following smp_store_mb() serves two purposes. First, it's
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* the counterpart rmb of the wmb in pollwake() such that data
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* written before wake up is always visible after wake up.
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* Second, the full barrier guarantees that triggered clearing
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@ -252,7 +252,7 @@ int poll_schedule_timeout(struct poll_wqueues *pwq, int state,
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* this problem doesn't exist for the first iteration as
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* add_wait_queue() has full barrier semantics.
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*/
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set_mb(pwq->triggered, 0);
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smp_store_mb(pwq->triggered, 0);
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return rc;
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}
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@ -66,8 +66,8 @@
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#define smp_read_barrier_depends() do { } while (0)
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#endif
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#ifndef set_mb
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#define set_mb(var, value) do { WRITE_ONCE(var, value); mb(); } while (0)
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#ifndef smp_store_mb
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#define smp_store_mb(var, value) do { WRITE_ONCE(var, value); mb(); } while (0)
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#endif
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#ifndef smp_mb__before_atomic
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@ -252,7 +252,7 @@ extern char ___assert_task_state[1 - 2*!!(
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#define set_task_state(tsk, state_value) \
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do { \
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(tsk)->task_state_change = _THIS_IP_; \
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set_mb((tsk)->state, (state_value)); \
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smp_store_mb((tsk)->state, (state_value)); \
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} while (0)
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/*
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#define set_current_state(state_value) \
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do { \
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current->task_state_change = _THIS_IP_; \
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set_mb(current->state, (state_value)); \
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smp_store_mb(current->state, (state_value)); \
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} while (0)
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#else
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#define __set_task_state(tsk, state_value) \
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do { (tsk)->state = (state_value); } while (0)
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#define set_task_state(tsk, state_value) \
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set_mb((tsk)->state, (state_value))
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smp_store_mb((tsk)->state, (state_value))
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/*
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* set_current_state() includes a barrier so that the write of current->state
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#define __set_current_state(state_value) \
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do { current->state = (state_value); } while (0)
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#define set_current_state(state_value) \
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set_mb(current->state, (state_value))
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smp_store_mb(current->state, (state_value))
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#endif
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{
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/*
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* The task state is guaranteed to be set before another task can
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* wake it. set_current_state() is implemented using set_mb() and
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* wake it. set_current_state() is implemented using smp_store_mb() and
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* queue_me() calls spin_unlock() upon completion, both serializing
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* access to the hash list and forcing another memory barrier.
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*/
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@ -175,7 +175,7 @@ static void pv_wait_node(struct mcs_spinlock *node)
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*
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* Matches the xchg() from pv_kick_node().
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*/
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set_mb(pn->state, vcpu_halted);
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smp_store_mb(pn->state, vcpu_halted);
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if (!READ_ONCE(node->locked))
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pv_wait(&pn->state, vcpu_halted);
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* condition being true _OR_ WQ_FLAG_WOKEN such that we will not miss
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* an event.
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*/
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set_mb(wait->flags, wait->flags & ~WQ_FLAG_WOKEN); /* B */
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smp_store_mb(wait->flags, wait->flags & ~WQ_FLAG_WOKEN); /* B */
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return timeout;
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}
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* doesn't imply write barrier and the users expects write
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* barrier semantics on wakeup functions. The following
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* smp_wmb() is equivalent to smp_wmb() in try_to_wake_up()
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* and is paired with set_mb() in wait_woken().
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* and is paired with smp_store_mb() in wait_woken().
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*/
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smp_wmb(); /* C */
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wait->flags |= WQ_FLAG_WOKEN;
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