drm/i915: Pass crtc_state to color management functions.
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1459350996-4957-2-git-send-email-maarten.lankhorst@linux.intel.com
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@ -612,8 +612,8 @@ struct drm_i915_display_funcs {
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/* display clock increase/decrease */
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/* pll clock increase/decrease */
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void (*load_csc_matrix)(struct drm_crtc *crtc);
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void (*load_luts)(struct drm_crtc *crtc);
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void (*load_csc_matrix)(struct drm_crtc_state *crtc_state);
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void (*load_luts)(struct drm_crtc_state *crtc_state);
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};
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enum forcewake_domain_id {
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@ -92,10 +92,10 @@ static void ctm_mult_by_limited(uint64_t *result, int64_t *input)
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}
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/* Set up the pipe CSC unit. */
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static void i9xx_load_csc_matrix(struct drm_crtc *crtc)
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static void i9xx_load_csc_matrix(struct drm_crtc_state *crtc_state)
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{
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struct drm_crtc *crtc = crtc_state->crtc;
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struct drm_device *dev = crtc->dev;
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struct drm_crtc_state *crtc_state = crtc->state;
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
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int i, pipe = intel_crtc->pipe;
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@ -203,10 +203,10 @@ static void i9xx_load_csc_matrix(struct drm_crtc *crtc)
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/*
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* Set up the pipe CSC unit on CherryView.
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*/
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static void cherryview_load_csc_matrix(struct drm_crtc *crtc)
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static void cherryview_load_csc_matrix(struct drm_crtc_state *state)
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{
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struct drm_crtc *crtc = state->crtc;
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struct drm_device *dev = crtc->dev;
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struct drm_crtc_state *state = crtc->state;
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struct drm_i915_private *dev_priv = dev->dev_private;
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int pipe = to_intel_crtc(crtc)->pipe;
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uint32_t mode;
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@ -252,13 +252,13 @@ static void cherryview_load_csc_matrix(struct drm_crtc *crtc)
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I915_WRITE(CGM_PIPE_MODE(pipe), mode);
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}
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void intel_color_set_csc(struct drm_crtc *crtc)
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void intel_color_set_csc(struct drm_crtc_state *crtc_state)
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{
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struct drm_device *dev = crtc->dev;
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struct drm_device *dev = crtc_state->crtc->dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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if (dev_priv->display.load_csc_matrix)
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dev_priv->display.load_csc_matrix(crtc);
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dev_priv->display.load_csc_matrix(crtc_state);
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}
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/* Loads the legacy palette/gamma unit for the CRTC. */
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@ -303,19 +303,20 @@ static void i9xx_load_luts_internal(struct drm_crtc *crtc,
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}
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}
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static void i9xx_load_luts(struct drm_crtc *crtc)
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static void i9xx_load_luts(struct drm_crtc_state *crtc_state)
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{
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i9xx_load_luts_internal(crtc, crtc->state->gamma_lut);
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i9xx_load_luts_internal(crtc_state->crtc, crtc_state->gamma_lut);
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}
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/* Loads the legacy palette/gamma unit for the CRTC on Haswell. */
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static void haswell_load_luts(struct drm_crtc *crtc)
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static void haswell_load_luts(struct drm_crtc_state *crtc_state)
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{
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struct drm_crtc *crtc = crtc_state->crtc;
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struct drm_device *dev = crtc->dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
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struct intel_crtc_state *intel_crtc_state =
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to_intel_crtc_state(crtc->state);
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to_intel_crtc_state(crtc_state);
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bool reenable_ips = false;
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/*
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@ -331,24 +332,24 @@ static void haswell_load_luts(struct drm_crtc *crtc)
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intel_crtc_state->gamma_mode = GAMMA_MODE_MODE_8BIT;
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I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
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i9xx_load_luts(crtc);
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i9xx_load_luts(crtc_state);
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if (reenable_ips)
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hsw_enable_ips(intel_crtc);
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}
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/* Loads the palette/gamma unit for the CRTC on Broadwell+. */
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static void broadwell_load_luts(struct drm_crtc *crtc)
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static void broadwell_load_luts(struct drm_crtc_state *state)
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{
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struct drm_crtc *crtc = state->crtc;
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struct drm_device *dev = crtc->dev;
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struct drm_crtc_state *state = crtc->state;
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct intel_crtc_state *intel_state = to_intel_crtc_state(state);
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enum pipe pipe = to_intel_crtc(crtc)->pipe;
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uint32_t i, lut_size = INTEL_INFO(dev)->color.degamma_lut_size;
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if (crtc_state_is_legacy(state)) {
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haswell_load_luts(crtc);
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haswell_load_luts(state);
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return;
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}
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@ -421,11 +422,11 @@ static void broadwell_load_luts(struct drm_crtc *crtc)
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}
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/* Loads the palette/gamma unit for the CRTC on CherryView. */
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static void cherryview_load_luts(struct drm_crtc *crtc)
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static void cherryview_load_luts(struct drm_crtc_state *state)
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{
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struct drm_crtc *crtc = state->crtc;
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struct drm_device *dev = crtc->dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct drm_crtc_state *state = crtc->state;
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enum pipe pipe = to_intel_crtc(crtc)->pipe;
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struct drm_color_lut *lut;
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uint32_t i, lut_size;
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@ -481,16 +482,16 @@ static void cherryview_load_luts(struct drm_crtc *crtc)
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i9xx_load_luts_internal(crtc, NULL);
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}
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void intel_color_load_luts(struct drm_crtc *crtc)
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void intel_color_load_luts(struct drm_crtc_state *crtc_state)
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{
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struct drm_device *dev = crtc->dev;
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struct drm_device *dev = crtc_state->crtc->dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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/* The clocks have to be on to load the palette. */
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if (!crtc->state->active)
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if (!crtc_state->active)
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return;
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dev_priv->display.load_luts(crtc);
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dev_priv->display.load_luts(crtc_state);
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}
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int intel_color_check(struct drm_crtc *crtc,
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@ -3223,7 +3223,7 @@ static void intel_update_pipe_config(struct intel_crtc *crtc,
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pipe_config->pipe_src_w, pipe_config->pipe_src_h);
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if (HAS_DDI(dev))
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intel_color_set_csc(&crtc->base);
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intel_color_set_csc(&pipe_config->base);
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/*
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* Update pipe size and adjust fitter if needed: the reason for this is
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@ -4723,6 +4723,8 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc)
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struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
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struct intel_encoder *encoder;
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int pipe = intel_crtc->pipe;
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struct intel_crtc_state *pipe_config =
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to_intel_crtc_state(crtc->state);
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if (WARN_ON(intel_crtc->active))
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return;
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@ -4770,7 +4772,7 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc)
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* On ILK+ LUT must be loaded before the pipe is running but with
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* clocks enabled
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*/
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intel_color_load_luts(crtc);
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intel_color_load_luts(&pipe_config->base);
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if (dev_priv->display.initial_watermarks != NULL)
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dev_priv->display.initial_watermarks(intel_crtc->config);
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@ -4845,7 +4847,7 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
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haswell_set_pipemisc(crtc);
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intel_color_set_csc(crtc);
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intel_color_set_csc(&pipe_config->base);
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intel_crtc->active = true;
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@ -4874,7 +4876,7 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
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* On ILK+ LUT must be loaded before the pipe is running but with
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* clocks enabled
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*/
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intel_color_load_luts(crtc);
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intel_color_load_luts(&pipe_config->base);
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intel_ddi_set_pipe_settings(crtc);
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if (!intel_crtc->config->has_dsi_encoder)
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@ -6035,6 +6037,8 @@ static void valleyview_crtc_enable(struct drm_crtc *crtc)
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struct drm_i915_private *dev_priv = to_i915(dev);
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struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
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struct intel_encoder *encoder;
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struct intel_crtc_state *pipe_config =
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to_intel_crtc_state(crtc->state);
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int pipe = intel_crtc->pipe;
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if (WARN_ON(intel_crtc->active))
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@ -6079,7 +6083,7 @@ static void valleyview_crtc_enable(struct drm_crtc *crtc)
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i9xx_pfit_enable(intel_crtc);
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intel_color_load_luts(crtc);
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intel_color_load_luts(&pipe_config->base);
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intel_update_watermarks(crtc);
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intel_enable_pipe(intel_crtc);
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@ -6106,6 +6110,8 @@ static void i9xx_crtc_enable(struct drm_crtc *crtc)
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struct drm_i915_private *dev_priv = to_i915(dev);
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struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
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struct intel_encoder *encoder;
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struct intel_crtc_state *pipe_config =
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to_intel_crtc_state(crtc->state);
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int pipe = intel_crtc->pipe;
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if (WARN_ON(intel_crtc->active))
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i9xx_pfit_enable(intel_crtc);
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intel_color_load_luts(crtc);
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intel_color_load_luts(&pipe_config->base);
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intel_update_watermarks(crtc);
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intel_enable_pipe(intel_crtc);
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* a modeset as this will be done by
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* crtc_enable already.
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*/
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intel_color_set_csc(crtc);
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intel_color_load_luts(crtc);
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intel_color_set_csc(crtc->state);
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intel_color_load_luts(crtc->state);
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}
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if (!modeset)
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@ -1669,7 +1669,7 @@ extern const struct drm_plane_helper_funcs intel_plane_helper_funcs;
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/* intel_color.c */
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void intel_color_init(struct drm_crtc *crtc);
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int intel_color_check(struct drm_crtc *crtc, struct drm_crtc_state *state);
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void intel_color_set_csc(struct drm_crtc *crtc);
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void intel_color_load_luts(struct drm_crtc *crtc);
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void intel_color_set_csc(struct drm_crtc_state *crtc_state);
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void intel_color_load_luts(struct drm_crtc_state *crtc_state);
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#endif /* __INTEL_DRV_H__ */
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