drm/i915: Introduce IS_GEN9_BC for Skylake and Kabylake.
Along with GLK it was introduced the .is_lp and IS_GEN9_LP. So, following the same simplification standard we can put Skylake and Kabylake under the same bucket for most of the things. So let's add the IS_GEN9_BC for "Big Core" (non Atom based platforms). The i915_drv.c was let out of this patch on purpose because that is really a decision per platform, just like other cases where IS_KABYLAKE is different from IS_SKYLAKE. v2: fix conflict with IS_LP and 3 new cases for this big core bucket: - intel_ddi.c: intel_ddi_get_link_dpll - intel_fbc.c: find_compression_threshold - i915_gem_gtt.c: gtt_write_workarounds Cc: Anusha Srivatsa <anusha.srivatsa@intel.com> Cc: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com> Cc: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by: Ander Conselvan de Oliveira <conselvan2@gmail.com> Acked-by: Jani Nikula <jani.nikula@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1485196357-30599-2-git-send-email-rodrigo.vivi@intel.com
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@ -1224,21 +1224,18 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
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max_freq = (IS_GEN9_LP(dev_priv) ? rp_state_cap >> 0 :
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rp_state_cap >> 16) & 0xff;
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max_freq *= (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv) ?
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GEN9_FREQ_SCALER : 1);
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max_freq *= (IS_GEN9_BC(dev_priv) ? GEN9_FREQ_SCALER : 1);
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seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
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intel_gpu_freq(dev_priv, max_freq));
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max_freq = (rp_state_cap & 0xff00) >> 8;
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max_freq *= (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv) ?
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GEN9_FREQ_SCALER : 1);
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max_freq *= (IS_GEN9_BC(dev_priv) ? GEN9_FREQ_SCALER : 1);
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seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
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intel_gpu_freq(dev_priv, max_freq));
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max_freq = (IS_GEN9_LP(dev_priv) ? rp_state_cap >> 16 :
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rp_state_cap >> 0) & 0xff;
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max_freq *= (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv) ?
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GEN9_FREQ_SCALER : 1);
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max_freq *= (IS_GEN9_BC(dev_priv) ? GEN9_FREQ_SCALER : 1);
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seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
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intel_gpu_freq(dev_priv, max_freq));
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seq_printf(m, "Max overclocked frequency: %dMHz\n",
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@ -1814,7 +1811,7 @@ static int i915_ring_freq_table(struct seq_file *m, void *unused)
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if (ret)
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goto out;
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if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
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if (IS_GEN9_BC(dev_priv)) {
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/* Convert GT frequency to 50 HZ units */
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min_gpu_freq =
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dev_priv->rps.min_freq_softlimit / GEN9_FREQ_SCALER;
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@ -1834,8 +1831,8 @@ static int i915_ring_freq_table(struct seq_file *m, void *unused)
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&ia_freq);
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seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",
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intel_gpu_freq(dev_priv, (gpu_freq *
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(IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv) ?
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GEN9_FREQ_SCALER : 1))),
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(IS_GEN9_BC(dev_priv) ?
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GEN9_FREQ_SCALER : 1))),
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((ia_freq >> 0) & 0xff) * 100,
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((ia_freq >> 8) & 0xff) * 100);
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}
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@ -4450,7 +4447,7 @@ static void gen9_sseu_device_status(struct drm_i915_private *dev_priv,
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sseu->slice_mask |= BIT(s);
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if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
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if (IS_GEN9_BC(dev_priv))
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sseu->subslice_mask =
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INTEL_INFO(dev_priv)->sseu.subslice_mask;
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@ -2760,8 +2760,9 @@ intel_info(const struct drm_i915_private *dev_priv)
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#define IS_GEN8(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(7)))
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#define IS_GEN9(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(8)))
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#define IS_GEN9_LP(dev_priv) (IS_GEN9(dev_priv) && INTEL_INFO(dev_priv)->is_lp)
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#define IS_LP(dev_priv) (INTEL_INFO(dev_priv)->is_lp)
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#define IS_GEN9_LP(dev_priv) (IS_GEN9(dev_priv) && IS_LP(dev_priv))
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#define IS_GEN9_BC(dev_priv) (IS_GEN9(dev_priv) && !IS_LP(dev_priv))
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#define ENGINE_MASK(id) BIT(id)
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#define RENDER_RING ENGINE_MASK(RCS)
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@ -2189,7 +2189,7 @@ static void gtt_write_workarounds(struct drm_i915_private *dev_priv)
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I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW);
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else if (IS_CHERRYVIEW(dev_priv))
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I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV);
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else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
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else if (IS_GEN9_BC(dev_priv))
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I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL);
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else if (IS_BROXTON(dev_priv))
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I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT);
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@ -702,7 +702,7 @@ static void i915_audio_component_codec_wake_override(struct device *kdev,
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struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
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u32 tmp;
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if (!IS_SKYLAKE(dev_priv) && !IS_KABYLAKE(dev_priv))
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if (!IS_GEN9_BC(dev_priv))
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return;
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i915_audio_component_get_power(kdev);
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@ -536,8 +536,8 @@ void intel_color_init(struct drm_crtc *crtc)
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} else if (IS_HASWELL(dev_priv)) {
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dev_priv->display.load_csc_matrix = i9xx_load_csc_matrix;
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dev_priv->display.load_luts = haswell_load_luts;
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} else if (IS_BROADWELL(dev_priv) || IS_SKYLAKE(dev_priv) ||
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IS_BROXTON(dev_priv) || IS_KABYLAKE(dev_priv)) {
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} else if (IS_BROADWELL(dev_priv) || IS_GEN9_BC(dev_priv) ||
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IS_BROXTON(dev_priv)) {
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dev_priv->display.load_csc_matrix = i9xx_load_csc_matrix;
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dev_priv->display.load_luts = broadwell_load_luts;
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} else {
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@ -445,7 +445,7 @@ static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port por
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if (IS_GEN9_LP(dev_priv))
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return hdmi_level;
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if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
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if (IS_GEN9_BC(dev_priv)) {
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skl_get_buf_trans_hdmi(dev_priv, &n_hdmi_entries);
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hdmi_default_entry = 8;
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} else if (IS_BROADWELL(dev_priv)) {
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@ -518,7 +518,7 @@ void intel_prepare_dp_ddi_buffers(struct intel_encoder *encoder)
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n_dp_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
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}
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if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
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if (IS_GEN9_BC(dev_priv)) {
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/* If we're boosting the current, set bit 31 of trans1 */
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if (dev_priv->vbt.ddi_port_info[port].dp_boost_level)
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iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE;
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@ -572,7 +572,7 @@ static void intel_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder)
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hdmi_level = intel_ddi_hdmi_level(dev_priv, port);
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if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
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if (IS_GEN9_BC(dev_priv)) {
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ddi_translations_hdmi = skl_get_buf_trans_hdmi(dev_priv, &n_hdmi_entries);
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/* If we're boosting the current, set bit 31 of trans1 */
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@ -1089,7 +1089,7 @@ void intel_ddi_clock_get(struct intel_encoder *encoder,
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if (INTEL_GEN(dev_priv) <= 8)
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hsw_ddi_clock_get(encoder, pipe_config);
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else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
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else if (IS_GEN9_BC(dev_priv))
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skl_ddi_clock_get(encoder, pipe_config);
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else if (IS_GEN9_LP(dev_priv))
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bxt_ddi_clock_get(encoder, pipe_config);
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@ -1150,7 +1150,7 @@ bool intel_ddi_pll_select(struct intel_crtc *intel_crtc,
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struct intel_encoder *intel_encoder =
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intel_ddi_get_crtc_new_encoder(crtc_state);
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if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
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if (IS_GEN9_BC(dev_priv))
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return skl_ddi_pll_select(intel_crtc, crtc_state,
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intel_encoder);
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else if (IS_GEN9_LP(dev_priv))
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@ -1641,7 +1641,7 @@ uint32_t ddi_signal_levels(struct intel_dp *intel_dp)
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level = translate_signal_level(signal_levels);
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if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
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if (IS_GEN9_BC(dev_priv))
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skl_ddi_set_iboost(encoder, level);
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else if (IS_GEN9_LP(dev_priv))
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bxt_ddi_vswing_sequence(dev_priv, level, port, encoder->type);
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@ -1658,7 +1658,7 @@ void intel_ddi_clk_select(struct intel_encoder *encoder,
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if (WARN_ON(!pll))
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return;
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if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
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if (IS_GEN9_BC(dev_priv)) {
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uint32_t val;
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/* DDI -> PLL mapping */
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@ -1714,7 +1714,7 @@ static void intel_ddi_pre_enable_hdmi(struct intel_encoder *encoder,
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intel_dp_dual_mode_set_tmds_output(intel_hdmi, true);
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intel_ddi_clk_select(encoder, pll);
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intel_prepare_hdmi_ddi_buffers(encoder);
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if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
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if (IS_GEN9_BC(dev_priv))
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skl_ddi_set_iboost(encoder, level);
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else if (IS_GEN9_LP(dev_priv))
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bxt_ddi_vswing_sequence(dev_priv, level, port,
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@ -1784,7 +1784,7 @@ static void intel_ddi_post_disable(struct intel_encoder *intel_encoder,
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intel_edp_panel_off(intel_dp);
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}
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if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
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if (IS_GEN9_BC(dev_priv))
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I915_WRITE(DPLL_CTRL2, (I915_READ(DPLL_CTRL2) |
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DPLL_CTRL2_DDI_CLK_OFF(port)));
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else if (INTEL_GEN(dev_priv) < 9)
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@ -2157,7 +2157,7 @@ intel_ddi_get_link_dpll(struct intel_dp *intel_dp, int clock)
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pll->state = tmp_pll_state;
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return NULL;
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}
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} else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
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} else if (IS_GEN9_BC(dev_priv)) {
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pll = skl_find_link_pll(dev_priv, clock);
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} else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
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pll = hsw_ddi_dp_get_dpll(encoder, clock);
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@ -5800,7 +5800,7 @@ static int skl_calc_cdclk(int max_pixclk, int vco);
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static void intel_update_max_cdclk(struct drm_i915_private *dev_priv)
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{
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if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
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if (IS_GEN9_BC(dev_priv)) {
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u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
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int max_cdclk, vco;
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@ -10673,7 +10673,7 @@ static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
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port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
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if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
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if (IS_GEN9_BC(dev_priv))
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skylake_get_ddi_pll(dev_priv, port, pipe_config);
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else if (IS_GEN9_LP(dev_priv))
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bxt_get_ddi_pll(dev_priv, port, pipe_config);
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@ -15681,7 +15681,7 @@ static void intel_setup_outputs(struct drm_i915_private *dev_priv)
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*/
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found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
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/* WaIgnoreDDIAStrap: skl */
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if (found || IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
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if (found || IS_GEN9_BC(dev_priv))
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intel_ddi_init(dev_priv, PORT_A);
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/* DDI B, C and D detection is indicated by the SFUSE_STRAP
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@ -15697,7 +15697,7 @@ static void intel_setup_outputs(struct drm_i915_private *dev_priv)
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/*
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* On SKL we don't have a way to detect DDI-E so we rely on VBT.
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*/
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if ((IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) &&
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if (IS_GEN9_BC(dev_priv) &&
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(dev_priv->vbt.ddi_port_info[PORT_E].supports_dp ||
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dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi ||
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dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi))
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@ -16196,7 +16196,7 @@ void intel_init_display_hooks(struct drm_i915_private *dev_priv)
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}
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/* Returns the core display clock speed */
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if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
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if (IS_GEN9_BC(dev_priv))
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dev_priv->display.get_display_clock_speed =
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skylake_get_display_clock_speed;
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else if (IS_GEN9_LP(dev_priv))
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@ -16277,7 +16277,7 @@ void intel_init_display_hooks(struct drm_i915_private *dev_priv)
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bxt_modeset_commit_cdclk;
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dev_priv->display.modeset_calc_cdclk =
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bxt_modeset_calc_cdclk;
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} else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
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} else if (IS_GEN9_BC(dev_priv)) {
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dev_priv->display.modeset_commit_cdclk =
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skl_modeset_commit_cdclk;
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dev_priv->display.modeset_calc_cdclk =
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@ -226,7 +226,7 @@ intel_dp_source_rates(struct intel_dp *intel_dp, const int **source_rates)
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if (IS_GEN9_LP(dev_priv)) {
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*source_rates = bxt_rates;
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size = ARRAY_SIZE(bxt_rates);
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} else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
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} else if (IS_GEN9_BC(dev_priv)) {
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*source_rates = skl_rates;
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size = ARRAY_SIZE(skl_rates);
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} else {
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@ -1751,8 +1751,7 @@ found:
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* DPLL0 VCO may need to be adjusted to get the correct
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* clock for eDP. This will affect cdclk as well.
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*/
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if (is_edp(intel_dp) &&
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(IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))) {
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if (is_edp(intel_dp) && IS_GEN9_BC(dev_priv)) {
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int vco;
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switch (pipe_config->port_clock / 2) {
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@ -2015,7 +2015,7 @@ void intel_shared_dpll_init(struct drm_device *dev)
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const struct dpll_info *dpll_info;
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int i;
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if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
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if (IS_GEN9_BC(dev_priv))
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dpll_mgr = &skl_pll_mgr;
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else if (IS_GEN9_LP(dev_priv))
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dpll_mgr = &bxt_pll_mgr;
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@ -537,8 +537,7 @@ static int find_compression_threshold(struct drm_i915_private *dev_priv,
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* reserved range size, so it always assumes the maximum (8mb) is used.
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* If we enable FBC using a CFB on that memory range we'll get FIFO
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* underruns, even if that range is not reserved by the BIOS. */
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if (IS_BROADWELL(dev_priv) ||
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IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
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if (IS_BROADWELL(dev_priv) || IS_GEN9_BC(dev_priv))
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end = ggtt->stolen_size - 8 * 1024 * 1024;
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else
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end = U64_MAX;
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@ -74,7 +74,7 @@ static const struct gmbus_pin *get_gmbus_pin(struct drm_i915_private *dev_priv,
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{
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if (IS_GEN9_LP(dev_priv))
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return &gmbus_pins_bxt[pin];
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else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
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else if (IS_GEN9_BC(dev_priv))
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return &gmbus_pins_skl[pin];
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else if (IS_BROADWELL(dev_priv))
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return &gmbus_pins_bdw[pin];
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@ -89,7 +89,7 @@ bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
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if (IS_GEN9_LP(dev_priv))
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size = ARRAY_SIZE(gmbus_pins_bxt);
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else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
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else if (IS_GEN9_BC(dev_priv))
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size = ARRAY_SIZE(gmbus_pins_skl);
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else if (IS_BROADWELL(dev_priv))
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size = ARRAY_SIZE(gmbus_pins_bdw);
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@ -178,7 +178,7 @@ static bool get_mocs_settings(struct drm_i915_private *dev_priv,
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{
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bool result = false;
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if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
|
||||
if (IS_GEN9_BC(dev_priv)) {
|
||||
table->size = ARRAY_SIZE(skylake_mocs_table);
|
||||
table->table = skylake_mocs_table;
|
||||
result = true;
|
||||
|
|
|
@ -2895,8 +2895,7 @@ static bool skl_needs_memory_bw_wa(struct intel_atomic_state *state)
|
|||
{
|
||||
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
|
||||
|
||||
if (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv) ||
|
||||
IS_KABYLAKE(dev_priv))
|
||||
if (IS_GEN9_BC(dev_priv) || IS_BROXTON(dev_priv))
|
||||
return true;
|
||||
|
||||
return false;
|
||||
|
@ -5294,7 +5293,7 @@ static void gen6_init_rps_frequencies(struct drm_i915_private *dev_priv)
|
|||
|
||||
dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq;
|
||||
if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv) ||
|
||||
IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
|
||||
IS_GEN9_BC(dev_priv)) {
|
||||
u32 ddcc_status = 0;
|
||||
|
||||
if (sandybridge_pcode_read(dev_priv,
|
||||
|
@ -5307,7 +5306,7 @@ static void gen6_init_rps_frequencies(struct drm_i915_private *dev_priv)
|
|||
dev_priv->rps.max_freq);
|
||||
}
|
||||
|
||||
if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
|
||||
if (IS_GEN9_BC(dev_priv)) {
|
||||
/* Store the frequency values in 16.66 MHZ units, which is
|
||||
* the natural hardware unit for SKL
|
||||
*/
|
||||
|
@ -5637,7 +5636,7 @@ static void gen6_update_ring_freq(struct drm_i915_private *dev_priv)
|
|||
/* convert DDR frequency from units of 266.6MHz to bandwidth */
|
||||
min_ring_freq = mult_frac(min_ring_freq, 8, 3);
|
||||
|
||||
if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
|
||||
if (IS_GEN9_BC(dev_priv)) {
|
||||
/* Convert GT frequency to 50 HZ units */
|
||||
min_gpu_freq = dev_priv->rps.min_freq / GEN9_FREQ_SCALER;
|
||||
max_gpu_freq = dev_priv->rps.max_freq / GEN9_FREQ_SCALER;
|
||||
|
@ -5655,7 +5654,7 @@ static void gen6_update_ring_freq(struct drm_i915_private *dev_priv)
|
|||
int diff = max_gpu_freq - gpu_freq;
|
||||
unsigned int ia_freq = 0, ring_freq = 0;
|
||||
|
||||
if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
|
||||
if (IS_GEN9_BC(dev_priv)) {
|
||||
/*
|
||||
* ring_freq = 2 * GT. ring_freq is in 100MHz units
|
||||
* No floor required for ring frequency on SKL.
|
||||
|
@ -6775,7 +6774,7 @@ void intel_enable_gt_powersave(struct drm_i915_private *dev_priv)
|
|||
} else if (INTEL_GEN(dev_priv) >= 9) {
|
||||
gen9_enable_rc6(dev_priv);
|
||||
gen9_enable_rps(dev_priv);
|
||||
if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
|
||||
if (IS_GEN9_BC(dev_priv))
|
||||
gen6_update_ring_freq(dev_priv);
|
||||
} else if (IS_BROADWELL(dev_priv)) {
|
||||
gen8_enable_rps(dev_priv);
|
||||
|
|
|
@ -732,7 +732,7 @@ gen9_sanitize_power_well_requests(struct drm_i915_private *dev_priv,
|
|||
* other request bits to be set, so WARN for those.
|
||||
*/
|
||||
if (power_well_id == SKL_DISP_PW_1 ||
|
||||
((IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) &&
|
||||
(IS_GEN9_BC(dev_priv) &&
|
||||
power_well_id == SKL_DISP_PW_MISC_IO))
|
||||
DRM_DEBUG_DRIVER("Clearing auxiliary requests for %s forced on "
|
||||
"by DMC\n", power_well->name);
|
||||
|
@ -2323,7 +2323,7 @@ static uint32_t get_allowed_dc_mask(const struct drm_i915_private *dev_priv,
|
|||
int requested_dc;
|
||||
int max_dc;
|
||||
|
||||
if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
|
||||
if (IS_GEN9_BC(dev_priv)) {
|
||||
max_dc = 2;
|
||||
mask = 0;
|
||||
} else if (IS_GEN9_LP(dev_priv)) {
|
||||
|
@ -2398,7 +2398,7 @@ int intel_power_domains_init(struct drm_i915_private *dev_priv)
|
|||
set_power_wells(power_domains, hsw_power_wells);
|
||||
} else if (IS_BROADWELL(dev_priv)) {
|
||||
set_power_wells(power_domains, bdw_power_wells);
|
||||
} else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
|
||||
} else if (IS_GEN9_BC(dev_priv)) {
|
||||
set_power_wells(power_domains, skl_power_wells);
|
||||
} else if (IS_BROXTON(dev_priv)) {
|
||||
set_power_wells(power_domains, bxt_power_wells);
|
||||
|
@ -2730,7 +2730,7 @@ void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume)
|
|||
|
||||
power_domains->initializing = true;
|
||||
|
||||
if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
|
||||
if (IS_GEN9_BC(dev_priv)) {
|
||||
skl_display_core_init(dev_priv, resume);
|
||||
} else if (IS_GEN9_LP(dev_priv)) {
|
||||
bxt_display_core_init(dev_priv, resume);
|
||||
|
@ -2769,7 +2769,7 @@ void intel_power_domains_suspend(struct drm_i915_private *dev_priv)
|
|||
if (!i915.disable_power_well)
|
||||
intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
|
||||
|
||||
if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
|
||||
if (IS_GEN9_BC(dev_priv))
|
||||
skl_display_core_uninit(dev_priv);
|
||||
else if (IS_GEN9_LP(dev_priv))
|
||||
bxt_display_core_uninit(dev_priv);
|
||||
|
|
Loading…
Reference in a new issue