ARM: dts: STiH410-family: fix wrong parent clock frequency

The clock parent was lower than child clock which is not correct. In some use case, it leads to division by zero. Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
2017-01-06 14:30:21 +01:00 · 2017-01-06 14:30:21 +01:00 · b9ec866d22
parent b005ebf945
commit b9ec866d22
1 changed files with 1 additions and 1 deletions
--- a/arch/arm/boot/dts/stih410.dtsi
+++ b/arch/arm/boot/dts/stih410.dtsi
@ -131,7 +131,7 @@
 						 <&clk_s_d2_quadfs 0>;

 			assigned-clock-rates = <297000000>,
-					       <108000000>,
+					       <297000000>,
 					       <0>,
 					       <400000000>,
 					       <400000000>;