[ARM] S3C2443: Add armdiv and arm clocks
Add the armdiv and arm clocks to the S3C2443 clock framework and ensure they are correctly setup. Signed-off-by: Ben Dooks <ben-linux@fluff.org>
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@ -221,7 +221,6 @@ static struct clk clk_mdivclk = {
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.get_rate = s3c2443_getrate_mdivclk,
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};
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static int s3c2443_setparent_msysclk(struct clk *clk, struct clk *parent)
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{
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unsigned long clksrc = __raw_readl(S3C2443_CLKSRC);
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@ -249,6 +248,46 @@ static struct clk clk_msysclk = {
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.set_parent = s3c2443_setparent_msysclk,
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};
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/* armdiv
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*
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* this clock is sourced from msysclk and can have a number of
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* divider values applied to it to then be fed into armclk.
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*/
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static struct clk clk_armdiv = {
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.name = "armdiv",
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.id = -1,
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.parent = &clk_msysclk,
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};
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/* armclk
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*
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* this is the clock fed into the ARM core itself, either from
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* armdiv or from hclk.
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*/
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static int s3c2443_setparent_armclk(struct clk *clk, struct clk *parent)
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{
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unsigned long clkdiv0;
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clkdiv0 = __raw_readl(S3C2443_CLKDIV0);
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if (parent == &clk_armdiv)
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clkdiv0 &= ~S3C2443_CLKDIV0_DVS;
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else if (parent == &clk_h)
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clkdiv0 |= S3C2443_CLKDIV0_DVS;
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else
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return -EINVAL;
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__raw_writel(clkdiv0, S3C2443_CLKDIV0);
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return 0;
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}
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static struct clk clk_arm = {
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.name = "armclk",
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.id = -1,
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.set_parent = s3c2443_setparent_armclk,
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};
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/* esysclk
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*
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@ -887,6 +926,15 @@ static void __init s3c2443_clk_initparents(void)
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}
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clk_init_set_parent(&clk_msysclk, parent);
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/* arm */
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if (__raw_readl(S3C2443_CLKDIV0) & S3C2443_CLKDIV0_DVS)
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parent = &clk_h;
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else
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parent = &clk_armdiv;
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clk_init_set_parent(&clk_arm, parent);
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}
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/* armdiv divisor table */
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@ -936,6 +984,8 @@ static struct clk *clks[] __initdata = {
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&clk_hsspi,
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&clk_hsmmc_div,
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&clk_hsmmc,
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&clk_armdiv,
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&clk_arm,
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};
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void __init s3c2443_init_clocks(int xtal)
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@ -958,6 +1008,8 @@ void __init s3c2443_init_clocks(int xtal)
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hclk = hclk / ((clkdiv0 & S3C2443_CLKDIV0_HALF_HCLK) ? 2 : 1);
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pclk = hclk / ((clkdiv0 & S3C2443_CLKDIV0_HALF_PCLK) ? 2 : 1);
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clk_armdiv.rate = fclk;
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s3c24xx_setup_clocks(xtal, fclk, hclk, pclk);
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printk("S3C2443: mpll %s %ld.%03ld MHz, cpu %ld.%03ld MHz, mem %ld.%03ld MHz, pclk %ld.%03ld MHz\n",
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