kvm: x86: vmx: reorder some msr writing
The commit 34a1cd60d1
, "x86: vmx: move some vmx setting from
vmx_init() to hardware_setup()", tried to refactor some codes
specific to vmx hardware setting into hardware_setup(), but some
msr writing should depend on our previous setting condition like
enable_apicv, enable_ept and so on.
Reported-by: Jamie Heilman <jamie@audible.transient.net>
Tested-by: Jamie Heilman <jamie@audible.transient.net>
Signed-off-by: Tiejun Chen <tiejun.chen@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
This commit is contained in:
parent
97bf6af1f9
commit
baa035227b
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@ -5840,53 +5840,10 @@ static __init int hardware_setup(void)
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memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
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memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
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vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
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vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
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vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
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vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
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vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
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vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
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vmx_disable_intercept_for_msr(MSR_IA32_BNDCFGS, true);
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memcpy(vmx_msr_bitmap_legacy_x2apic,
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vmx_msr_bitmap_legacy, PAGE_SIZE);
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memcpy(vmx_msr_bitmap_longmode_x2apic,
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vmx_msr_bitmap_longmode, PAGE_SIZE);
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if (enable_apicv) {
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for (msr = 0x800; msr <= 0x8ff; msr++)
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vmx_disable_intercept_msr_read_x2apic(msr);
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/* According SDM, in x2apic mode, the whole id reg is used.
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* But in KVM, it only use the highest eight bits. Need to
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* intercept it */
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vmx_enable_intercept_msr_read_x2apic(0x802);
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/* TMCCT */
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vmx_enable_intercept_msr_read_x2apic(0x839);
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/* TPR */
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vmx_disable_intercept_msr_write_x2apic(0x808);
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/* EOI */
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vmx_disable_intercept_msr_write_x2apic(0x80b);
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/* SELF-IPI */
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vmx_disable_intercept_msr_write_x2apic(0x83f);
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}
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if (enable_ept) {
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kvm_mmu_set_mask_ptes(0ull,
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(enable_ept_ad_bits) ? VMX_EPT_ACCESS_BIT : 0ull,
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(enable_ept_ad_bits) ? VMX_EPT_DIRTY_BIT : 0ull,
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0ull, VMX_EPT_EXECUTABLE_MASK);
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ept_set_mmio_spte_mask();
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kvm_enable_tdp();
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} else
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kvm_disable_tdp();
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update_ple_window_actual_max();
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if (setup_vmcs_config(&vmcs_config) < 0) {
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r = -EIO;
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goto out7;
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}
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}
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if (boot_cpu_has(X86_FEATURE_NX))
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kvm_enable_efer_bits(EFER_NX);
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@ -5945,6 +5902,49 @@ static __init int hardware_setup(void)
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if (nested)
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nested_vmx_setup_ctls_msrs();
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vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
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vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
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vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
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vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
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vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
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vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
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vmx_disable_intercept_for_msr(MSR_IA32_BNDCFGS, true);
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memcpy(vmx_msr_bitmap_legacy_x2apic,
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vmx_msr_bitmap_legacy, PAGE_SIZE);
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memcpy(vmx_msr_bitmap_longmode_x2apic,
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vmx_msr_bitmap_longmode, PAGE_SIZE);
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if (enable_apicv) {
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for (msr = 0x800; msr <= 0x8ff; msr++)
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vmx_disable_intercept_msr_read_x2apic(msr);
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/* According SDM, in x2apic mode, the whole id reg is used.
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* But in KVM, it only use the highest eight bits. Need to
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* intercept it */
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vmx_enable_intercept_msr_read_x2apic(0x802);
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/* TMCCT */
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vmx_enable_intercept_msr_read_x2apic(0x839);
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/* TPR */
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vmx_disable_intercept_msr_write_x2apic(0x808);
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/* EOI */
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vmx_disable_intercept_msr_write_x2apic(0x80b);
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/* SELF-IPI */
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vmx_disable_intercept_msr_write_x2apic(0x83f);
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}
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if (enable_ept) {
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kvm_mmu_set_mask_ptes(0ull,
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(enable_ept_ad_bits) ? VMX_EPT_ACCESS_BIT : 0ull,
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(enable_ept_ad_bits) ? VMX_EPT_DIRTY_BIT : 0ull,
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0ull, VMX_EPT_EXECUTABLE_MASK);
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ept_set_mmio_spte_mask();
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kvm_enable_tdp();
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} else
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kvm_disable_tdp();
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update_ple_window_actual_max();
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return alloc_kvm_area();
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out7:
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