i2c: OMAP2/3: Fix scll/sclh calculations
Fix scll/sclh calculations for HS and fast modes. Currently the driver uses equal (roughly) low/high times which will result in too short low time. OMAP3430 TRM gives the following equations: F/S: tLow = (scll + 7) * internal_clk tHigh = (sclh + 5) * internal_clk HS: tLow = (scll + 7) * fclk tHigh = (sclh + 5) * fclk Furthermore, the I2C specification sets the following minimum values for HS tLow/tHigh for capacitive bus loads 100 pF (maximum speed 3400) and 400 pF (maximum speed 1700): speed tLow tHigh 3400 160 ns 60 ns 1700 320 ns 120 ns and for F/S: speed tLow tHigh 400 1300 ns 600 ns 100 4700 ns 4000 ns By using duty cycles 33/66 (HS, F) and 50/50 (S) we stay above these minimum values. Signed-off-by: Aaro Koskinen <aaro.koskinen@nokia.com> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Ben Dooks <ben-linux@fluff.org>
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@ -343,17 +343,28 @@ static int omap_i2c_init(struct omap_i2c_dev *dev)
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/* If configured for High Speed */
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if (dev->speed > 400) {
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unsigned long scl;
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/* For first phase of HS mode */
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fsscll = internal_clk / (400 * 2) - 6;
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fssclh = internal_clk / (400 * 2) - 6;
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scl = internal_clk / 400;
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fsscll = scl - (scl / 3) - 7;
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fssclh = (scl / 3) - 5;
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/* For second phase of HS mode */
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hsscll = fclk_rate / (dev->speed * 2) - 6;
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hssclh = fclk_rate / (dev->speed * 2) - 6;
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scl = fclk_rate / dev->speed;
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hsscll = scl - (scl / 3) - 7;
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hssclh = (scl / 3) - 5;
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} else if (dev->speed > 100) {
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unsigned long scl;
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/* Fast mode */
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scl = internal_clk / dev->speed;
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fsscll = scl - (scl / 3) - 7;
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fssclh = (scl / 3) - 5;
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} else {
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/* To handle F/S modes */
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fsscll = internal_clk / (dev->speed * 2) - 6;
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fssclh = internal_clk / (dev->speed * 2) - 6;
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/* Standard mode */
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fsscll = internal_clk / (dev->speed * 2) - 7;
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fssclh = internal_clk / (dev->speed * 2) - 5;
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}
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scll = (hsscll << OMAP_I2C_SCLL_HSSCLL) | fsscll;
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sclh = (hssclh << OMAP_I2C_SCLH_HSSCLH) | fssclh;
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