dma: mxs-dma: let dma_is_apbh and apbh_is_old take parameter
Let macros dma_is_apbh and apbh_is_old take mxs_dma as parameter to make the code easy to read. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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@ -38,10 +38,10 @@
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#define MXS_DMA_APBH 0
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#define MXS_DMA_APBX 1
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#define dma_is_apbh() (mxs_dma->dev_id == MXS_DMA_APBH)
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#define dma_is_apbh(mxs_dma) ((mxs_dma)->dev_id == MXS_DMA_APBH)
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#define APBH_VERSION_LATEST 3
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#define apbh_is_old() (mxs_dma->version < APBH_VERSION_LATEST)
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#define apbh_is_old(mxs_dma) ((mxs_dma)->version < APBH_VERSION_LATEST)
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#define HW_APBHX_CTRL0 0x000
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#define BM_APBH_CTRL0_APB_BURST8_EN (1 << 29)
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@ -54,10 +54,14 @@
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#define HW_APBH_VERSION (cpu_is_mx23() ? 0x3f0 : 0x800)
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#define HW_APBX_VERSION 0x800
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#define BP_APBHX_VERSION_MAJOR 24
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#define HW_APBHX_CHn_NXTCMDAR(n) \
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(((dma_is_apbh() && apbh_is_old()) ? 0x050 : 0x110) + (n) * 0x70)
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#define HW_APBHX_CHn_SEMA(n) \
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(((dma_is_apbh() && apbh_is_old()) ? 0x080 : 0x140) + (n) * 0x70)
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/*
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* The offset of NXTCMDAR register is different per both dma type and version,
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* while stride for each channel is all the same 0x70.
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*/
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#define HW_APBHX_CHn_NXTCMDAR(d, n) \
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(((dma_is_apbh(d) && apbh_is_old(d)) ? 0x050 : 0x110) + (n) * 0x70)
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#define HW_APBHX_CHn_SEMA(d, n) \
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(((dma_is_apbh(d) && apbh_is_old(d)) ? 0x080 : 0x140) + (n) * 0x70)
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/*
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* ccw bits definitions
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@ -136,7 +140,7 @@ static void mxs_dma_reset_chan(struct mxs_dma_chan *mxs_chan)
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struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma;
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int chan_id = mxs_chan->chan.chan_id;
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if (dma_is_apbh() && apbh_is_old())
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if (dma_is_apbh(mxs_dma) && apbh_is_old(mxs_dma))
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writel(1 << (chan_id + BP_APBH_CTRL0_RESET_CHANNEL),
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mxs_dma->base + HW_APBHX_CTRL0 + STMP_OFFSET_REG_SET);
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else
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@ -151,10 +155,10 @@ static void mxs_dma_enable_chan(struct mxs_dma_chan *mxs_chan)
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/* set cmd_addr up */
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writel(mxs_chan->ccw_phys,
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mxs_dma->base + HW_APBHX_CHn_NXTCMDAR(chan_id));
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mxs_dma->base + HW_APBHX_CHn_NXTCMDAR(mxs_dma, chan_id));
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/* write 1 to SEMA to kick off the channel */
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writel(1, mxs_dma->base + HW_APBHX_CHn_SEMA(chan_id));
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writel(1, mxs_dma->base + HW_APBHX_CHn_SEMA(mxs_dma, chan_id));
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}
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static void mxs_dma_disable_chan(struct mxs_dma_chan *mxs_chan)
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@ -168,7 +172,7 @@ static void mxs_dma_pause_chan(struct mxs_dma_chan *mxs_chan)
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int chan_id = mxs_chan->chan.chan_id;
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/* freeze the channel */
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if (dma_is_apbh() && apbh_is_old())
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if (dma_is_apbh(mxs_dma) && apbh_is_old(mxs_dma))
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writel(1 << chan_id,
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mxs_dma->base + HW_APBHX_CTRL0 + STMP_OFFSET_REG_SET);
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else
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@ -184,7 +188,7 @@ static void mxs_dma_resume_chan(struct mxs_dma_chan *mxs_chan)
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int chan_id = mxs_chan->chan.chan_id;
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/* unfreeze the channel */
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if (dma_is_apbh() && apbh_is_old())
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if (dma_is_apbh(mxs_dma) && apbh_is_old(mxs_dma))
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writel(1 << chan_id,
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mxs_dma->base + HW_APBHX_CTRL0 + STMP_OFFSET_REG_CLR);
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else
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@ -578,7 +582,7 @@ static int __init mxs_dma_init(struct mxs_dma_engine *mxs_dma)
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BP_APBHX_VERSION_MAJOR;
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/* enable apbh burst */
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if (dma_is_apbh()) {
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if (dma_is_apbh(mxs_dma)) {
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writel(BM_APBH_CTRL0_APB_BURST_EN,
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mxs_dma->base + HW_APBHX_CTRL0 + STMP_OFFSET_REG_SET);
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writel(BM_APBH_CTRL0_APB_BURST8_EN,
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