clk: renesas: rcar-gen3-cpg: Add support for RCLK on R-Car H3 ES2.0
Starting with R-Car H3 ES2.0, the parent of RCLK is selected using MD28. Add support for that, but retain the old behavior for R-Car H3 ES1.x and M3-W ES1.0 using a quirk. Inspired by a patch by Takeshi Kihara in the BSP. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Cc: Takeshi Kihara <takeshi.kihara.df@renesas.com>
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@ -252,11 +252,20 @@ static u32 cpg_mode __initdata;
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static u32 cpg_quirks __initdata;
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#define PLL_ERRATA BIT(0) /* Missing PLL0/2/4 post-divider */
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#define RCKCR_CKSEL BIT(1) /* Manual RCLK parent selection */
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static const struct soc_device_attribute cpg_quirks_match[] __initconst = {
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{
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.soc_id = "r8a7795", .revision = "ES1.0",
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.data = (void *)PLL_ERRATA,
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.data = (void *)(PLL_ERRATA | RCKCR_CKSEL),
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},
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{
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.soc_id = "r8a7795", .revision = "ES1.*",
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.data = (void *)RCKCR_CKSEL,
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},
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{
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.soc_id = "r8a7796", .revision = "ES1.0",
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.data = (void *)RCKCR_CKSEL,
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},
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{ /* sentinel */ }
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};
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@ -330,6 +339,7 @@ struct clk * __init rcar_gen3_cpg_clk_register(struct device *dev,
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return cpg_sd_clk_register(core, base, __clk_get_name(parent));
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case CLK_TYPE_GEN3_R:
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if (cpg_quirks & RCKCR_CKSEL) {
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/*
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* RINT is default.
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* Only if EXTALR is populated, we switch to it.
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@ -343,6 +353,12 @@ struct clk * __init rcar_gen3_cpg_clk_register(struct device *dev,
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writel(value, base + CPG_RCKCR);
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break;
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}
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/* Select parent clock of RCLK by MD28 */
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if (cpg_mode & BIT(28))
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parent = clks[cpg_clk_extalr];
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break;
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default:
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return ERR_PTR(-EINVAL);
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