drm/i915: Removed the read of RP_STATE_CAP from sysfs/debugfs functions
The frequency values(Rp0, Rp1, Rpn) reported by RP_STATE_CAP register are stored, initially by the Driver, inside the dev_priv->rps structure. Since these values are expected to remain same throughout, there is no real need to read this register, on dynamic basis, from certain debugfs/sysfs functions and the values can be instead retrieved from the dev_priv->rps structure when needed. For the i915_frequency_info debugfs interface, the frequency values from the RP_STATE_CAP register only should be used, to indicate the actual Hw state, since it is principally used for the debugging purpose. v2: Reverted the changes in i915_frequency_info function, to continue report back the frequency values, as per the actual Hw state (Chris) Signed-off-by: Akash Goel <akash.goel@intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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@ -4180,7 +4180,7 @@ i915_max_freq_set(void *data, u64 val)
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{
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struct drm_device *dev = data;
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struct drm_i915_private *dev_priv = dev->dev_private;
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u32 rp_state_cap, hw_max, hw_min;
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u32 hw_max, hw_min;
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int ret;
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if (INTEL_INFO(dev)->gen < 6)
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@ -4197,18 +4197,10 @@ i915_max_freq_set(void *data, u64 val)
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/*
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* Turbo will still be enabled, but won't go above the set value.
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*/
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if (IS_VALLEYVIEW(dev)) {
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val = intel_freq_opcode(dev_priv, val);
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val = intel_freq_opcode(dev_priv, val);
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hw_max = dev_priv->rps.max_freq;
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hw_min = dev_priv->rps.min_freq;
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} else {
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val = intel_freq_opcode(dev_priv, val);
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rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
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hw_max = dev_priv->rps.max_freq;
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hw_min = (rp_state_cap >> 16) & 0xff;
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}
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hw_max = dev_priv->rps.max_freq;
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hw_min = dev_priv->rps.min_freq;
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if (val < hw_min || val > hw_max || val < dev_priv->rps.min_freq_softlimit) {
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mutex_unlock(&dev_priv->rps.hw_lock);
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@ -4255,7 +4247,7 @@ i915_min_freq_set(void *data, u64 val)
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{
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struct drm_device *dev = data;
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struct drm_i915_private *dev_priv = dev->dev_private;
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u32 rp_state_cap, hw_max, hw_min;
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u32 hw_max, hw_min;
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int ret;
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if (INTEL_INFO(dev)->gen < 6)
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@ -4272,18 +4264,10 @@ i915_min_freq_set(void *data, u64 val)
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/*
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* Turbo will still be enabled, but won't go below the set value.
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*/
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if (IS_VALLEYVIEW(dev)) {
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val = intel_freq_opcode(dev_priv, val);
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val = intel_freq_opcode(dev_priv, val);
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hw_max = dev_priv->rps.max_freq;
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hw_min = dev_priv->rps.min_freq;
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} else {
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val = intel_freq_opcode(dev_priv, val);
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rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
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hw_max = dev_priv->rps.max_freq;
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hw_min = (rp_state_cap >> 16) & 0xff;
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}
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hw_max = dev_priv->rps.max_freq;
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hw_min = dev_priv->rps.min_freq;
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if (val < hw_min || val > hw_max || val > dev_priv->rps.max_freq_softlimit) {
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mutex_unlock(&dev_priv->rps.hw_lock);
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@ -487,38 +487,17 @@ static ssize_t gt_rp_mhz_show(struct device *kdev, struct device_attribute *attr
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struct drm_minor *minor = dev_to_drm_minor(kdev);
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struct drm_device *dev = minor->dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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u32 val, rp_state_cap;
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ssize_t ret;
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u32 val;
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ret = mutex_lock_interruptible(&dev->struct_mutex);
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if (ret)
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return ret;
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intel_runtime_pm_get(dev_priv);
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rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
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intel_runtime_pm_put(dev_priv);
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mutex_unlock(&dev->struct_mutex);
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if (attr == &dev_attr_gt_RP0_freq_mhz) {
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if (IS_VALLEYVIEW(dev))
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val = intel_gpu_freq(dev_priv, dev_priv->rps.rp0_freq);
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else
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val = intel_gpu_freq(dev_priv,
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((rp_state_cap & 0x0000ff) >> 0));
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} else if (attr == &dev_attr_gt_RP1_freq_mhz) {
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if (IS_VALLEYVIEW(dev))
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val = intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq);
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else
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val = intel_gpu_freq(dev_priv,
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((rp_state_cap & 0x00ff00) >> 8));
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} else if (attr == &dev_attr_gt_RPn_freq_mhz) {
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if (IS_VALLEYVIEW(dev))
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val = intel_gpu_freq(dev_priv, dev_priv->rps.min_freq);
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else
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val = intel_gpu_freq(dev_priv,
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((rp_state_cap & 0xff0000) >> 16));
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} else {
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if (attr == &dev_attr_gt_RP0_freq_mhz)
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val = intel_gpu_freq(dev_priv, dev_priv->rps.rp0_freq);
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else if (attr == &dev_attr_gt_RP1_freq_mhz)
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val = intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq);
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else if (attr == &dev_attr_gt_RPn_freq_mhz)
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val = intel_gpu_freq(dev_priv, dev_priv->rps.min_freq);
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else
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BUG();
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}
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return snprintf(buf, PAGE_SIZE, "%d\n", val);
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}
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