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genirq: Remove irq argument from irq flow handlers 

Most interrupt flow handlers do not use the irq argument. Those few
which use it can retrieve the irq number from the irq descriptor.

Remove the argument.

Search and replace was done with coccinelle and some extra helper
scripts around it. Thanks to Julia for her help!

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Cc: Julia Lawall <Julia.Lawall@lip6.fr>
Cc: Jiang Liu <jiang.liu@linux.intel.com>
steinar/wifi_calib_4_9_kernel
Thomas Gleixner 2015-09-14 10:42:37 +02:00
parent b237721c5d
commit bd0b9ac405
188 changed files with 281 additions and 340 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
arch/alpha/kernel/irq.c
View File

@ -117,6 +117,6 @@ handle_irq(int irq)
}
irq_enter();
generic_handle_irq_desc(irq, desc);
generic_handle_irq_desc(desc);
irq_exit();
}

2
arch/arc/kernel/mcip.c
View File

@ -252,7 +252,7 @@ static struct irq_chip idu_irq_chip = {
static int idu_first_irq;
static void idu_cascade_isr(unsigned int __core_irq, struct irq_desc *desc)
static void idu_cascade_isr(struct irq_desc *desc)
{
struct irq_domain *domain = irq_desc_get_handler_data(desc);
unsigned int core_irq = irq_desc_get_irq(desc);

2
arch/arm/common/it8152.c
View File

@ -95,7 +95,7 @@ void it8152_init_irq(void)
}
}
void it8152_irq_demux(unsigned int irq, struct irq_desc *desc)
void it8152_irq_demux(struct irq_desc *desc)
{
int bits_pd, bits_lp, bits_ld;
int i;

2
arch/arm/common/locomo.c
View File

@ -138,7 +138,7 @@ static struct locomo_dev_info locomo_devices[] = {
},
};
static void locomo_handler(unsigned int __irq, struct irq_desc *desc)
static void locomo_handler(struct irq_desc *desc)
{
struct locomo *lchip = irq_desc_get_chip_data(desc);
int req, i;

6
arch/arm/common/sa1111.c
View File

@ -196,10 +196,8 @@ static struct sa1111_dev_info sa1111_devices[] = {
* active IRQs causes the interrupt output to pulse, the upper levels
* will call us again if there are more interrupts to process.
*/
static void
sa1111_irq_handler(unsigned int __irq, struct irq_desc *desc)
static void sa1111_irq_handler(struct irq_desc *desc)
{
unsigned int irq = irq_desc_get_irq(desc);
unsigned int stat0, stat1, i;
struct sa1111 *sachip = irq_desc_get_handler_data(desc);
void __iomem *mapbase = sachip->base + SA1111_INTC;
@ -214,7 +212,7 @@ sa1111_irq_handler(unsigned int __irq, struct irq_desc *desc)
sa1111_writel(stat1, mapbase + SA1111_INTSTATCLR1);
if (stat0 == 0 && stat1 == 0) {
do_bad_IRQ(irq, desc);
do_bad_IRQ(desc);
return;
}

2
arch/arm/include/asm/hardware/it8152.h
View File

@ -106,7 +106,7 @@ extern void __iomem *it8152_base_address;
struct pci_dev;
struct pci_sys_data;
extern void it8152_irq_demux(unsigned int irq, struct irq_desc *desc);
extern void it8152_irq_demux(struct irq_desc *desc);
extern void it8152_init_irq(void);
extern int it8152_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin);
extern int it8152_pci_setup(int nr, struct pci_sys_data *sys);

4
arch/arm/include/asm/mach/irq.h
View File

@ -23,10 +23,10 @@ extern int show_fiq_list(struct seq_file *, int);
/*
* This is for easy migration, but should be changed in the source
*/
#define do_bad_IRQ(irq,desc) \
#define do_bad_IRQ(desc) \
do { \
raw_spin_lock(&desc->lock); \
handle_bad_irq(irq, desc); \
handle_bad_irq(desc); \
raw_spin_unlock(&desc->lock); \
} while(0)

6
arch/arm/mach-dove/irq.c
View File

@ -69,14 +69,14 @@ static struct irq_chip pmu_irq_chip = {
.irq_ack = pmu_irq_ack,
};
static void pmu_irq_handler(unsigned int __irq, struct irq_desc *desc)
static void pmu_irq_handler(struct irq_desc *desc)
{
unsigned int irq = irq_desc_get_irq(desc);
unsigned long cause = readl(PMU_INTERRUPT_CAUSE);
unsigned int irq;
cause &= readl(PMU_INTERRUPT_MASK);
if (cause == 0) {
do_bad_IRQ(irq, desc);
do_bad_IRQ(desc);
return;
}

5
arch/arm/mach-footbridge/isa-irq.c
View File

@ -87,13 +87,12 @@ static struct irq_chip isa_hi_chip = {
.irq_unmask = isa_unmask_pic_hi_irq,
};
static void
isa_irq_handler(unsigned int irq, struct irq_desc *desc)
static void isa_irq_handler(struct irq_desc *desc)
{
unsigned int isa_irq = *(unsigned char *)PCIIACK_BASE;
if (isa_irq < _ISA_IRQ(0) || isa_irq >= _ISA_IRQ(16)) {
do_bad_IRQ(isa_irq, desc);
do_bad_IRQ(desc);
return;
}

2
arch/arm/mach-gemini/gpio.c
View File

@ -126,7 +126,7 @@ static int gpio_set_irq_type(struct irq_data *d, unsigned int type)
return 0;
}
static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
static void gpio_irq_handler(struct irq_desc *desc)
{
unsigned int port = (unsigned int)irq_desc_get_handler_data(desc);
unsigned int gpio_irq_no, irq_stat;

2
arch/arm/mach-imx/3ds_debugboard.c
View File

@ -85,7 +85,7 @@ static struct platform_device smsc_lan9217_device = {
.resource = smsc911x_resources,
};
static void mxc_expio_irq_handler(u32 irq, struct irq_desc *desc)
static void mxc_expio_irq_handler(struct irq_desc *desc)
{
u32 imr_val;
u32 int_valid;

2
arch/arm/mach-imx/mach-mx31ads.c
View File

@ -154,7 +154,7 @@ static inline void mxc_init_imx_uart(void)
imx31_add_imx_uart0(&uart_pdata);
}
static void mx31ads_expio_irq_handler(u32 irq, struct irq_desc *desc)
static void mx31ads_expio_irq_handler(struct irq_desc *desc)
{
u32 imr_val;
u32 int_valid;

2
arch/arm/mach-iop13xx/msi.c
View File

@ -91,7 +91,7 @@ static void (*write_imipr[])(u32) = {
write_imipr_3,
};
static void iop13xx_msi_handler(unsigned int irq, struct irq_desc *desc)
static void iop13xx_msi_handler(struct irq_desc *desc)
{
int i, j;
unsigned long status;

4
arch/arm/mach-lpc32xx/irq.c
View File

@ -370,7 +370,7 @@ static struct irq_chip lpc32xx_irq_chip = {
.irq_set_wake = lpc32xx_irq_wake
};
static void lpc32xx_sic1_handler(unsigned int irq, struct irq_desc *desc)
static void lpc32xx_sic1_handler(struct irq_desc *desc)
{
unsigned long ints = __raw_readl(LPC32XX_INTC_STAT(LPC32XX_SIC1_BASE));
@ -383,7 +383,7 @@ static void lpc32xx_sic1_handler(unsigned int irq, struct irq_desc *desc)
}
}
static void lpc32xx_sic2_handler(unsigned int irq, struct irq_desc *desc)
static void lpc32xx_sic2_handler(struct irq_desc *desc)
{
unsigned long ints = __raw_readl(LPC32XX_INTC_STAT(LPC32XX_SIC2_BASE));

3
arch/arm/mach-netx/generic.c
View File

@ -69,8 +69,7 @@ static struct platform_device *devices[] __initdata = {
#define DEBUG_IRQ(fmt...) while (0) {}
#endif
static void
netx_hif_demux_handler(unsigned int irq_unused, struct irq_desc *desc)
static void netx_hif_demux_handler(struct irq_desc *desc)
{
unsigned int irq = NETX_IRQ_HIF_CHAINED(0);
unsigned int stat;

2
arch/arm/mach-omap1/fpga.c
View File

@ -87,7 +87,7 @@ static void fpga_mask_ack_irq(struct irq_data *d)
fpga_ack_irq(d);
}
static void innovator_fpga_IRQ_demux(unsigned int irq, struct irq_desc *desc)
static void innovator_fpga_IRQ_demux(struct irq_desc *desc)
{
u32 stat;
int fpga_irq;

2
arch/arm/mach-omap2/prm_common.c
View File

@ -102,7 +102,7 @@ static void omap_prcm_events_filter_priority(unsigned long *events,
* dispatched accordingly. Clearing of the wakeup events should be
* done by the SoC specific individual handlers.
*/
static void omap_prcm_irq_handler(unsigned int irq, struct irq_desc *desc)
static void omap_prcm_irq_handler(struct irq_desc *desc)
{
unsigned long pending[OMAP_PRCM_MAX_NR_PENDING_REG];
unsigned long priority_pending[OMAP_PRCM_MAX_NR_PENDING_REG];

2
arch/arm/mach-pxa/balloon3.c
View File

@ -496,7 +496,7 @@ static struct irq_chip balloon3_irq_chip = {
.irq_unmask = balloon3_unmask_irq,
};
static void balloon3_irq_handler(unsigned int __irq, struct irq_desc *desc)
static void balloon3_irq_handler(struct irq_desc *desc)
{
unsigned long pending = __raw_readl(BALLOON3_INT_CONTROL_REG) &
balloon3_irq_enabled;

5
arch/arm/mach-pxa/cm-x2xx-pci.c
View File

@ -29,13 +29,12 @@
void __iomem *it8152_base_address;
static int cmx2xx_it8152_irq_gpio;
static void cmx2xx_it8152_irq_demux(unsigned int __irq, struct irq_desc *desc)
static void cmx2xx_it8152_irq_demux(struct irq_desc *desc)
{
unsigned int irq = irq_desc_get_irq(desc);
/* clear our parent irq */
desc->irq_data.chip->irq_ack(&desc->irq_data);
it8152_irq_demux(irq, desc);
it8152_irq_demux(desc);
}
void __cmx2xx_pci_init_irq(int irq_gpio)

2
arch/arm/mach-pxa/lpd270.c
View File

@ -120,7 +120,7 @@ static struct irq_chip lpd270_irq_chip = {
.irq_unmask = lpd270_unmask_irq,
};
static void lpd270_irq_handler(unsigned int __irq, struct irq_desc *desc)
static void lpd270_irq_handler(struct irq_desc *desc)
{
unsigned int irq;
unsigned long pending;

2
arch/arm/mach-pxa/pcm990-baseboard.c
View File

@ -284,7 +284,7 @@ static struct irq_chip pcm990_irq_chip = {
.irq_unmask = pcm990_unmask_irq,
};
static void pcm990_irq_handler(unsigned int __irq, struct irq_desc *desc)
static void pcm990_irq_handler(struct irq_desc *desc)
{
unsigned int irq;
unsigned long pending;

2
arch/arm/mach-pxa/viper.c
View File

@ -276,7 +276,7 @@ static inline unsigned long viper_irq_pending(void)
viper_irq_enabled_mask;
}
static void viper_irq_handler(unsigned int __irq, struct irq_desc *desc)
static void viper_irq_handler(struct irq_desc *desc)
{
unsigned int irq;
unsigned long pending;

2
arch/arm/mach-pxa/zeus.c
View File

@ -105,7 +105,7 @@ static inline unsigned long zeus_irq_pending(void)
return __raw_readw(ZEUS_CPLD_ISA_IRQ) & zeus_irq_enabled_mask;
}
static void zeus_irq_handler(unsigned int __irq, struct irq_desc *desc)
static void zeus_irq_handler(struct irq_desc *desc)
{
unsigned int irq;
unsigned long pending;

3
arch/arm/mach-rpc/ecard.c
View File

@ -551,8 +551,7 @@ static void ecard_check_lockup(struct irq_desc *desc)
}
}
static void
ecard_irq_handler(unsigned int irq, struct irq_desc *desc)
static void ecard_irq_handler(struct irq_desc *desc)
{
ecard_t *ec;
int called = 0;

4
arch/arm/mach-s3c24xx/bast-irq.c
View File

@ -100,9 +100,7 @@ static struct irq_chip bast_pc104_chip = {
.irq_ack = bast_pc104_maskack
};
static void
bast_irq_pc104_demux(unsigned int irq,
struct irq_desc *desc)
static void bast_irq_pc104_demux(struct irq_desc *desc)
{
unsigned int stat;
unsigned int irqno;

8
arch/arm/mach-s3c64xx/common.c
View File

@ -388,22 +388,22 @@ static inline void s3c_irq_demux_eint(unsigned int start, unsigned int end)
}
}
static void s3c_irq_demux_eint0_3(unsigned int irq, struct irq_desc *desc)
static void s3c_irq_demux_eint0_3(struct irq_desc *desc)
{
s3c_irq_demux_eint(0, 3);
}
static void s3c_irq_demux_eint4_11(unsigned int irq, struct irq_desc *desc)
static void s3c_irq_demux_eint4_11(struct irq_desc *desc)
{
s3c_irq_demux_eint(4, 11);
}
static void s3c_irq_demux_eint12_19(unsigned int irq, struct irq_desc *desc)
static void s3c_irq_demux_eint12_19(struct irq_desc *desc)
{
s3c_irq_demux_eint(12, 19);
}
static void s3c_irq_demux_eint20_27(unsigned int irq, struct irq_desc *desc)
static void s3c_irq_demux_eint20_27(struct irq_desc *desc)
{
s3c_irq_demux_eint(20, 27);
}

2
arch/arm/mach-sa1100/neponset.c
View File

@ -166,7 +166,7 @@ static struct sa1100_port_fns neponset_port_fns = {
* ensure that the IRQ signal is deasserted before returning. This
* is rather unfortunate.
*/
static void neponset_irq_handler(unsigned int irq, struct irq_desc *desc)
static void neponset_irq_handler(struct irq_desc *desc)
{
struct neponset_drvdata *d = irq_desc_get_handler_data(desc);
unsigned int irr;

2
arch/arm/plat-orion/gpio.c
View File

@ -407,7 +407,7 @@ static int gpio_irq_set_type(struct irq_data *d, u32 type)
return 0;
}
static void gpio_irq_handler(unsigned __irq, struct irq_desc *desc)
static void gpio_irq_handler(struct irq_desc *desc)
{
struct orion_gpio_chip *ochip = irq_desc_get_handler_data(desc);
u32 cause, type;

2
arch/avr32/mach-at32ap/extint.c
View File

@ -144,7 +144,7 @@ static struct irq_chip eic_chip = {
.irq_set_type = eic_set_irq_type,
};
static void demux_eic_irq(unsigned int irq, struct irq_desc *desc)
static void demux_eic_irq(struct irq_desc *desc)
{
struct eic *eic = irq_desc_get_handler_data(desc);
unsigned long status, pending;

2
arch/avr32/mach-at32ap/pio.c
View File

@ -281,7 +281,7 @@ static struct irq_chip gpio_irqchip = {
.irq_set_type = gpio_irq_type,
};
static void gpio_irq_handler(unsigned irq, struct irq_desc *desc)
static void gpio_irq_handler(struct irq_desc *desc)
{
struct pio_device *pio = irq_desc_get_chip_data(desc);
unsigned gpio_irq;

4
arch/blackfin/include/asm/irq_handler.h
View File

@ -60,7 +60,7 @@ extern void bfin_internal_mask_irq(unsigned int irq);
extern void bfin_internal_unmask_irq(unsigned int irq);
struct irq_desc;
extern void bfin_demux_mac_status_irq(unsigned int, struct irq_desc *);
extern void bfin_demux_gpio_irq(unsigned int, struct irq_desc *);
extern void bfin_demux_mac_status_irq(struct irq_desc *);
extern void bfin_demux_gpio_irq(struct irq_desc *);
#endif

2
arch/blackfin/kernel/irqchip.c
View File

@ -107,7 +107,7 @@ asmlinkage void asm_do_IRQ(unsigned int irq, struct pt_regs *regs)
* than crashing, do something sensible.
*/
if (irq >= NR_IRQS)
handle_bad_irq(irq, &bad_irq_desc);
handle_bad_irq(&bad_irq_desc);
else
generic_handle_irq(irq);

10
arch/blackfin/mach-bf537/ints-priority.c
View File

@ -89,8 +89,7 @@ static struct irq_chip bf537_generic_error_irqchip = {
.irq_unmask = bf537_generic_error_unmask_irq,
};
static void bf537_demux_error_irq(unsigned int int_err_irq,
struct irq_desc *inta_desc)
static void bf537_demux_error_irq(struct irq_desc *inta_desc)
{
int irq = 0;
@ -182,15 +181,12 @@ static struct irq_chip bf537_mac_rx_irqchip = {
.irq_unmask = bf537_mac_rx_unmask_irq,
};
static void bf537_demux_mac_rx_irq(unsigned int __int_irq,
struct irq_desc *desc)
static void bf537_demux_mac_rx_irq(struct irq_desc *desc)
{
unsigned int int_irq = irq_desc_get_irq(desc);
if (bfin_read_DMA1_IRQ_STATUS() & (DMA_DONE | DMA_ERR))
bfin_handle_irq(IRQ_MAC_RX);
else
bfin_demux_gpio_irq(int_irq, desc);
bfin_demux_gpio_irq(desc);
}
#endif

5
arch/blackfin/mach-common/ints-priority.c
View File

@ -656,8 +656,7 @@ static struct irq_chip bfin_mac_status_irqchip = {
.irq_set_wake = bfin_mac_status_set_wake,
};
void bfin_demux_mac_status_irq(unsigned int int_err_irq,
struct irq_desc *inta_desc)
void bfin_demux_mac_status_irq(struct irq_desc *inta_desc)
{
int i, irq = 0;
u32 status = bfin_read_EMAC_SYSTAT();
@ -825,7 +824,7 @@ static void bfin_demux_gpio_block(unsigned int irq)
}
}
void bfin_demux_gpio_irq(unsigned int __inta_irq, struct irq_desc *desc)
void bfin_demux_gpio_irq(struct irq_desc *desc)
{
unsigned int inta_irq = irq_desc_get_irq(desc);
unsigned int irq;

2
arch/c6x/platforms/megamod-pic.c
View File

@ -93,7 +93,7 @@ static struct irq_chip megamod_chip = {
.irq_unmask = unmask_megamod,
};
static void megamod_irq_cascade(unsigned int __irq, struct irq_desc *desc)
static void megamod_irq_cascade(struct irq_desc *desc)
{
struct megamod_cascade_data *cascade;
struct megamod_pic *pic;

8
arch/m68k/amiga/amiints.c
View File

@ -46,7 +46,7 @@ static struct irq_chip amiga_irq_chip = {
* The builtin Amiga hardware interrupt handlers.
*/
static void ami_int1(unsigned int irq, struct irq_desc *desc)
static void ami_int1(struct irq_desc *desc)
{
unsigned short ints = amiga_custom.intreqr & amiga_custom.intenar;
@ -69,7 +69,7 @@ static void ami_int1(unsigned int irq, struct irq_desc *desc)
}
}
static void ami_int3(unsigned int irq, struct irq_desc *desc)
static void ami_int3(struct irq_desc *desc)
{
unsigned short ints = amiga_custom.intreqr & amiga_custom.intenar;
@ -92,7 +92,7 @@ static void ami_int3(unsigned int irq, struct irq_desc *desc)
}
}
static void ami_int4(unsigned int irq, struct irq_desc *desc)
static void ami_int4(struct irq_desc *desc)
{
unsigned short ints = amiga_custom.intreqr & amiga_custom.intenar;
@ -121,7 +121,7 @@ static void ami_int4(unsigned int irq, struct irq_desc *desc)
}
}
static void ami_int5(unsigned int irq, struct irq_desc *desc)
static void ami_int5(struct irq_desc *desc)
{
unsigned short ints = amiga_custom.intreqr & amiga_custom.intenar;

6
arch/m68k/coldfire/intc-5272.c
View File

@ -143,12 +143,10 @@ static int intc_irq_set_type(struct irq_data *d, unsigned int type)
* We need to be careful with the masking/acking due to the side effects
* of masking an interrupt.
*/
static void intc_external_irq(unsigned int __irq, struct irq_desc *desc)
static void intc_external_irq(struct irq_desc *desc)
{
unsigned int irq = irq_desc_get_irq(desc);
irq_desc_get_chip(desc)->irq_ack(&desc->irq_data);
handle_simple_irq(irq, desc);
handle_simple_irq(desc);
}
static struct irq_chip intc_irq_chip = {

3
arch/m68k/include/asm/irq.h
View File

@ -64,8 +64,7 @@ extern void m68k_setup_auto_interrupt(void (*handler)(unsigned int,
struct pt_regs *));
extern void m68k_setup_user_interrupt(unsigned int vec, unsigned int cnt);
extern void m68k_setup_irq_controller(struct irq_chip *,
void (*handle)(unsigned int irq,
struct irq_desc *desc),
void (*handle)(struct irq_desc *desc),
unsigned int irq, unsigned int cnt);
extern unsigned int irq_canonicalize(unsigned int irq);

2
arch/m68k/include/asm/mac_via.h
View File

@ -261,7 +261,7 @@ extern void via_irq_enable(int);
extern void via_irq_disable(int);
extern void via_nubus_irq_startup(int irq);
extern void via_nubus_irq_shutdown(int irq);
extern void via1_irq(unsigned int irq, struct irq_desc *desc);
extern void via1_irq(struct irq_desc *desc);
extern void via1_set_head(int);
extern int via2_scsi_drq_pending(void);

2
arch/m68k/mac/baboon.c
View File

@ -45,7 +45,7 @@ void __init baboon_init(void)
* Baboon interrupt handler. This works a lot like a VIA.
*/
static void baboon_irq(unsigned int irq, struct irq_desc *desc)
static void baboon_irq(struct irq_desc *desc)
{
int irq_bit, irq_num;
unsigned char events;

4
arch/m68k/mac/oss.c
View File

@ -63,7 +63,7 @@ void __init oss_nubus_init(void)
* Handle miscellaneous OSS interrupts.
*/
static void oss_irq(unsigned int __irq, struct irq_desc *desc)
static void oss_irq(struct irq_desc *desc)
{
int events = oss->irq_pending &
(OSS_IP_IOPSCC | OSS_IP_SCSI | OSS_IP_IOPISM);
@ -99,7 +99,7 @@ static void oss_irq(unsigned int __irq, struct irq_desc *desc)
* Unlike the VIA/RBV this is on its own autovector interrupt level.
*/
static void oss_nubus_irq(unsigned int irq, struct irq_desc *desc)
static void oss_nubus_irq(struct irq_desc *desc)
{
int events, irq_bit, i;

2
arch/m68k/mac/psc.c
View File

@ -113,7 +113,7 @@ void __init psc_init(void)
* PSC interrupt handler. It's a lot like the VIA interrupt handler.
*/
static void psc_irq(unsigned int __irq, struct irq_desc *desc)
static void psc_irq(struct irq_desc *desc)
{
unsigned int offset = (unsigned int)irq_desc_get_handler_data(desc);
unsigned int irq = irq_desc_get_irq(desc);

6
arch/m68k/mac/via.c
View File

@ -446,7 +446,7 @@ void via_nubus_irq_shutdown(int irq)
* via6522.c :-), disable/pending masks added.
*/
void via1_irq(unsigned int irq, struct irq_desc *desc)
void via1_irq(struct irq_desc *desc)
{
int irq_num;
unsigned char irq_bit, events;
@ -467,7 +467,7 @@ void via1_irq(unsigned int irq, struct irq_desc *desc)
} while (events >= irq_bit);
}
static void via2_irq(unsigned int irq, struct irq_desc *desc)
static void via2_irq(struct irq_desc *desc)
{
int irq_num;
unsigned char irq_bit, events;
@ -493,7 +493,7 @@ static void via2_irq(unsigned int irq, struct irq_desc *desc)
* VIA2 dispatcher as a fast interrupt handler.
*/
void via_nubus_irq(unsigned int irq, struct irq_desc *desc)
static void via_nubus_irq(struct irq_desc *desc)
{
int slot_irq;
unsigned char slot_bit, events;

4
arch/metag/kernel/irq.c
View File

@ -94,13 +94,11 @@ void do_IRQ(int irq, struct pt_regs *regs)
"MOV D0.5,%0\n"
"MOV D1Ar1,%1\n"
"MOV D1RtP,%2\n"
"MOV D0Ar2,%3\n"
"SWAP A0StP,D0.5\n"
"SWAP PC,D1RtP\n"
"MOV A0StP,D0.5\n"
:
: "r" (isp), "r" (irq), "r" (desc->handle_irq),
"r" (desc)
: "r" (isp), "r" (desc), "r" (desc->handle_irq)
: "memory", "cc", "D1Ar1", "D0Ar2", "D1Ar3", "D0Ar4",
"D1Ar5", "D0Ar6", "D0Re0", "D1Re0", "D0.4", "D1RtP",
"D0.5"

4
arch/mips/alchemy/common/irq.c
View File

@ -851,7 +851,7 @@ static struct syscore_ops alchemy_gpic_pmops = {
/* create chained handlers for the 4 IC requests to the MIPS IRQ ctrl */
#define DISP(name, base, addr) \
static void au1000_##name##_dispatch(unsigned int irq, struct irq_desc *d) \
static void au1000_##name##_dispatch(struct irq_desc *d) \
{ \
unsigned long r = __raw_readl((void __iomem *)KSEG1ADDR(addr)); \
if (likely(r)) \
@ -865,7 +865,7 @@ DISP(ic0r1, AU1000_INTC0_INT_BASE, AU1000_IC0_PHYS_ADDR + IC_REQ1INT)
DISP(ic1r0, AU1000_INTC1_INT_BASE, AU1000_IC1_PHYS_ADDR + IC_REQ0INT)
DISP(ic1r1, AU1000_INTC1_INT_BASE, AU1000_IC1_PHYS_ADDR + IC_REQ1INT)
static void alchemy_gpic_dispatch(unsigned int irq, struct irq_desc *d)
static void alchemy_gpic_dispatch(struct irq_desc *d)
{
int i = __raw_readl(AU1300_GPIC_ADDR + AU1300_GPIC_PRIENC);
generic_handle_irq(ALCHEMY_GPIC_INT_BASE + i);

2
arch/mips/alchemy/devboards/bcsr.c
View File

@ -86,7 +86,7 @@ EXPORT_SYMBOL_GPL(bcsr_mod);
/*
* DB1200/PB1200 CPLD IRQ muxer
*/
static void bcsr_csc_handler(unsigned int irq, struct irq_desc *d)
static void bcsr_csc_handler(struct irq_desc *d)
{
unsigned short bisr = __raw_readw(bcsr_virt + BCSR_REG_INTSTAT);
struct irq_chip *chip = irq_desc_get_chip(d);

2
arch/mips/ath25/ar2315.c
View File

@ -69,7 +69,7 @@ static struct irqaction ar2315_ahb_err_interrupt = {
.name = "ar2315-ahb-error",
};
static void ar2315_misc_irq_handler(unsigned irq, struct irq_desc *desc)
static void ar2315_misc_irq_handler(struct irq_desc *desc)
{
u32 pending = ar2315_rst_reg_read(AR2315_ISR) &
ar2315_rst_reg_read(AR2315_IMR);

2
arch/mips/ath25/ar5312.c
View File

@ -73,7 +73,7 @@ static struct irqaction ar5312_ahb_err_interrupt = {
.name = "ar5312-ahb-error",
};
static void ar5312_misc_irq_handler(unsigned irq, struct irq_desc *desc)
static void ar5312_misc_irq_handler(struct irq_desc *desc)
{
u32 pending = ar5312_rst_reg_read(AR5312_ISR) &
ar5312_rst_reg_read(AR5312_IMR);

8
arch/mips/ath79/irq.c
View File

@ -26,7 +26,7 @@
#include "common.h"
#include "machtypes.h"
static void ath79_misc_irq_handler(unsigned int irq, struct irq_desc *desc)
static void ath79_misc_irq_handler(struct irq_desc *desc)
{
void __iomem *base = ath79_reset_base;
u32 pending;
@ -119,7 +119,7 @@ static void __init ath79_misc_irq_init(void)
irq_set_chained_handler(ATH79_CPU_IRQ(6), ath79_misc_irq_handler);
}
static void ar934x_ip2_irq_dispatch(unsigned int irq, struct irq_desc *desc)
static void ar934x_ip2_irq_dispatch(struct irq_desc *desc)
{
u32 status;
@ -148,7 +148,7 @@ static void ar934x_ip2_irq_init(void)
irq_set_chained_handler(ATH79_CPU_IRQ(2), ar934x_ip2_irq_dispatch);
}
static void qca955x_ip2_irq_dispatch(unsigned int irq, struct irq_desc *desc)
static void qca955x_ip2_irq_dispatch(struct irq_desc *desc)
{
u32 status;
@ -171,7 +171,7 @@ static void qca955x_ip2_irq_dispatch(unsigned int irq, struct irq_desc *desc)
}
}
static void qca955x_ip3_irq_dispatch(unsigned int irq, struct irq_desc *desc)
static void qca955x_ip3_irq_dispatch(struct irq_desc *desc)
{
u32 status;

2
arch/mips/cavium-octeon/octeon-irq.c
View File

@ -2221,7 +2221,7 @@ static irqreturn_t octeon_irq_cib_handler(int my_irq, void *data)
if (irqd_get_trigger_type(irq_data) &
IRQ_TYPE_EDGE_BOTH)
cvmx_write_csr(host_data->raw_reg, 1ull << i);
generic_handle_irq_desc(irq, desc);
generic_handle_irq_desc(desc);
}
}

4
arch/mips/include/asm/netlogic/common.h
View File

@ -57,8 +57,8 @@
#include <asm/mach-netlogic/multi-node.h>
struct irq_desc;
void nlm_smp_function_ipi_handler(unsigned int irq, struct irq_desc *desc);
void nlm_smp_resched_ipi_handler(unsigned int irq, struct irq_desc *desc);
void nlm_smp_function_ipi_handler(struct irq_desc *desc);
void nlm_smp_resched_ipi_handler(struct irq_desc *desc);
void nlm_smp_irq_init(int hwcpuid);
void nlm_boot_secondary_cpus(void);
int nlm_wakeup_secondary_cpus(void);

2
arch/mips/jz4740/gpio.c
View File

@ -291,7 +291,7 @@ static void jz_gpio_check_trigger_both(struct jz_gpio_chip *chip, unsigned int i
writel(mask, reg);
}
static void jz_gpio_irq_demux_handler(unsigned int irq, struct irq_desc *desc)
static void jz_gpio_irq_demux_handler(struct irq_desc *desc)
{
uint32_t flag;
unsigned int gpio_irq;

4
arch/mips/netlogic/common/smp.c
View File

@ -82,7 +82,7 @@ void nlm_send_ipi_mask(const struct cpumask *mask, unsigned int action)
}
/* IRQ_IPI_SMP_FUNCTION Handler */
void nlm_smp_function_ipi_handler(unsigned int __irq, struct irq_desc *desc)
void nlm_smp_function_ipi_handler(struct irq_desc *desc)
{
unsigned int irq = irq_desc_get_irq(desc);
clear_c0_eimr(irq);
@ -92,7 +92,7 @@ void nlm_smp_function_ipi_handler(unsigned int __irq, struct irq_desc *desc)
}
/* IRQ_IPI_SMP_RESCHEDULE handler */
void nlm_smp_resched_ipi_handler(unsigned int __irq, struct irq_desc *desc)
void nlm_smp_resched_ipi_handler(struct irq_desc *desc)
{
unsigned int irq = irq_desc_get_irq(desc);
clear_c0_eimr(irq);

2
arch/mips/pci/pci-ar2315.c
View File

@ -318,7 +318,7 @@ static int ar2315_pci_host_setup(struct ar2315_pci_ctrl *apc)
return 0;
}
static void ar2315_pci_irq_handler(unsigned irq, struct irq_desc *desc)
static void ar2315_pci_irq_handler(struct irq_desc *desc)
{
struct ar2315_pci_ctrl *apc = irq_desc_get_handler_data(desc);
u32 pending = ar2315_pci_reg_read(apc, AR2315_PCI_ISR) &

2
arch/mips/pci/pci-ar71xx.c
View File

@ -226,7 +226,7 @@ static struct pci_ops ar71xx_pci_ops = {
.write = ar71xx_pci_write_config,
};
static void ar71xx_pci_irq_handler(unsigned int irq, struct irq_desc *desc)
static void ar71xx_pci_irq_handler(struct irq_desc *desc)
{
struct ar71xx_pci_controller *apc;
void __iomem *base = ath79_reset_base;

2
arch/mips/pci/pci-ar724x.c
View File

@ -225,7 +225,7 @@ static struct pci_ops ar724x_pci_ops = {
.write = ar724x_pci_write,
};
static void ar724x_pci_irq_handler(unsigned int irq, struct irq_desc *desc)
static void ar724x_pci_irq_handler(struct irq_desc *desc)
{
struct ar724x_pci_controller *apc;
void __iomem *base;

2
arch/mips/pci/pci-rt3883.c
View File

@ -129,7 +129,7 @@ static void rt3883_pci_write_cfg32(struct rt3883_pci_controller *rpc,
rt3883_pci_w32(rpc, val, RT3883_PCI_REG_CFGDATA);
}
static void rt3883_pci_irq_handler(unsigned int __irq, struct irq_desc *desc)
static void rt3883_pci_irq_handler(struct irq_desc *desc)
{
struct rt3883_pci_controller *rpc;
u32 pending;

2
arch/mips/ralink/irq.c
View File

@ -96,7 +96,7 @@ unsigned int get_c0_compare_int(void)
return CP0_LEGACY_COMPARE_IRQ;
}
static void ralink_intc_irq_handler(unsigned int irq, struct irq_desc *desc)
static void ralink_intc_irq_handler(struct irq_desc *desc)
{
u32 pending = rt_intc_r32(INTC_REG_STATUS0);

23
arch/powerpc/include/asm/qe_ic.h
View File

@ -59,14 +59,14 @@ enum qe_ic_grp_id {
#ifdef CONFIG_QUICC_ENGINE
void qe_ic_init(struct device_node *node, unsigned int flags,
void (*low_handler)(unsigned int irq, struct irq_desc *desc),
void (*high_handler)(unsigned int irq, struct irq_desc *desc));
void (*low_handler)(struct irq_desc *desc),
void (*high_handler)(struct irq_desc *desc));
unsigned int qe_ic_get_low_irq(struct qe_ic *qe_ic);
unsigned int qe_ic_get_high_irq(struct qe_ic *qe_ic);
#else
static inline void qe_ic_init(struct device_node *node, unsigned int flags,
void (*low_handler)(unsigned int irq, struct irq_desc *desc),
void (*high_handler)(unsigned int irq, struct irq_desc *desc))
void (*low_handler)(struct irq_desc *desc),
void (*high_handler)(struct irq_desc *desc))
{}
static inline unsigned int qe_ic_get_low_irq(struct qe_ic *qe_ic)
{ return 0; }
@ -78,8 +78,7 @@ void qe_ic_set_highest_priority(unsigned int virq, int high);
int qe_ic_set_priority(unsigned int virq, unsigned int priority);
int qe_ic_set_high_priority(unsigned int virq, unsigned int priority, int high);
static inline void qe_ic_cascade_low_ipic(unsigned int irq,
struct irq_desc *desc)
static inline void qe_ic_cascade_low_ipic(struct irq_desc *desc)
{
struct qe_ic *qe_ic = irq_desc_get_handler_data(desc);
unsigned int cascade_irq = qe_ic_get_low_irq(qe_ic);
@ -88,8 +87,7 @@ static inline void qe_ic_cascade_low_ipic(unsigned int irq,
generic_handle_irq(cascade_irq);
}
static inline void qe_ic_cascade_high_ipic(unsigned int irq,
struct irq_desc *desc)
static inline void qe_ic_cascade_high_ipic(struct irq_desc *desc)
{
struct qe_ic *qe_ic = irq_desc_get_handler_data(desc);
unsigned int cascade_irq = qe_ic_get_high_irq(qe_ic);
@ -98,8 +96,7 @@ static inline void qe_ic_cascade_high_ipic(unsigned int irq,
generic_handle_irq(cascade_irq);
}
static inline void qe_ic_cascade_low_mpic(unsigned int irq,
struct irq_desc *desc)
static inline void qe_ic_cascade_low_mpic(struct irq_desc *desc)
{
struct qe_ic *qe_ic = irq_desc_get_handler_data(desc);
unsigned int cascade_irq = qe_ic_get_low_irq(qe_ic);
@ -111,8 +108,7 @@ static inline void qe_ic_cascade_low_mpic(unsigned int irq,
chip->irq_eoi(&desc->irq_data);
}
static inline void qe_ic_cascade_high_mpic(unsigned int irq,
struct irq_desc *desc)
static inline void qe_ic_cascade_high_mpic(struct irq_desc *desc)
{
struct qe_ic *qe_ic = irq_desc_get_handler_data(desc);
unsigned int cascade_irq = qe_ic_get_high_irq(qe_ic);
@ -124,8 +120,7 @@ static inline void qe_ic_cascade_high_mpic(unsigned int irq,
chip->irq_eoi(&desc->irq_data);
}
static inline void qe_ic_cascade_muxed_mpic(unsigned int irq,
struct irq_desc *desc)
static inline void qe_ic_cascade_muxed_mpic(struct irq_desc *desc)
{
struct qe_ic *qe_ic = irq_desc_get_handler_data(desc);
unsigned int cascade_irq;

2
arch/powerpc/include/asm/tsi108_pci.h
View File

@ -39,7 +39,7 @@
extern int tsi108_setup_pci(struct device_node *dev, u32 cfg_phys, int primary);
extern void tsi108_pci_int_init(struct device_node *node);
extern void tsi108_irq_cascade(unsigned int irq, struct irq_desc *desc);
extern void tsi108_irq_cascade(struct irq_desc *desc);
extern void tsi108_clear_pci_cfg_error(void);
#endif /* _ASM_POWERPC_TSI108_PCI_H */

3
arch/powerpc/platforms/512x/mpc5121_ads_cpld.c
View File

@ -104,8 +104,7 @@ cpld_pic_get_irq(int offset, u8 ignore, u8 __iomem *statusp,
return irq_linear_revmap(cpld_pic_host, cpld_irq);
}
static void
cpld_pic_cascade(unsigned int __irq, struct irq_desc *desc)
static void cpld_pic_cascade(struct irq_desc *desc)
{
unsigned int irq;

2
arch/powerpc/platforms/52xx/media5200.c
View File

@ -80,7 +80,7 @@ static struct irq_chip media5200_irq_chip = {
.irq_mask_ack = media5200_irq_mask,
};
void media5200_irq_cascade(unsigned int virq, struct irq_desc *desc)
static void media5200_irq_cascade(struct irq_desc *desc)
{
struct irq_chip *chip = irq_desc_get_chip(desc);
int sub_virq, val;

2
arch/powerpc/platforms/52xx/mpc52xx_gpt.c
View File

@ -191,7 +191,7 @@ static struct irq_chip mpc52xx_gpt_irq_chip = {
.irq_set_type = mpc52xx_gpt_irq_set_type,
};
void mpc52xx_gpt_irq_cascade(unsigned int virq, struct irq_desc *desc)
static void mpc52xx_gpt_irq_cascade(struct irq_desc *desc)
{
struct mpc52xx_gpt_priv *gpt = irq_desc_get_handler_data(desc);
int sub_virq;

2
arch/powerpc/platforms/82xx/pq2ads-pci-pic.c
View File

@ -78,7 +78,7 @@ static struct irq_chip pq2ads_pci_ic = {
.irq_disable = pq2ads_pci_mask_irq
};
static void pq2ads_pci_irq_demux(unsigned int irq, struct irq_desc *desc)
static void pq2ads_pci_irq_demux(struct irq_desc *desc)
{
struct pq2ads_pci_pic *priv = irq_desc_get_handler_data(desc);
u32 stat, mask, pend;

2
arch/powerpc/platforms/85xx/common.c
View File

@ -49,7 +49,7 @@ int __init mpc85xx_common_publish_devices(void)
return of_platform_bus_probe(NULL, mpc85xx_common_ids, NULL);
}
#ifdef CONFIG_CPM2
static void cpm2_cascade(unsigned int irq, struct irq_desc *desc)
static void cpm2_cascade(struct irq_desc *desc)
{
struct irq_chip *chip = irq_desc_get_chip(desc);
int cascade_irq;

6
arch/powerpc/platforms/85xx/mpc85xx_cds.c
View File

@ -192,10 +192,8 @@ void mpc85xx_cds_fixup_bus(struct pci_bus *bus)
}
#ifdef CONFIG_PPC_I8259
static void mpc85xx_8259_cascade_handler(unsigned int __irq,
struct irq_desc *desc)
static void mpc85xx_8259_cascade_handler(struct irq_desc *desc)
{
unsigned int irq = irq_desc_get_irq(desc);
unsigned int cascade_irq = i8259_irq();
if (cascade_irq != NO_IRQ)
@ -203,7 +201,7 @@ static void mpc85xx_8259_cascade_handler(unsigned int __irq,
generic_handle_irq(cascade_irq);
/* check for any interrupts from the shared IRQ line */
handle_fasteoi_irq(irq, desc);
handle_fasteoi_irq(desc);
}
static irqreturn_t mpc85xx_8259_cascade_action(int irq, void *dev_id)

2
arch/powerpc/platforms/85xx/mpc85xx_ds.c
View File

@ -46,7 +46,7 @@
#endif
#ifdef CONFIG_PPC_I8259
static void mpc85xx_8259_cascade(unsigned int irq, struct irq_desc *desc)
static void mpc85xx_8259_cascade(struct irq_desc *desc)
{
struct irq_chip *chip = irq_desc_get_chip(desc);
unsigned int cascade_irq = i8259_irq();

2
arch/powerpc/platforms/85xx/socrates_fpga_pic.c
View File

@ -91,7 +91,7 @@ static inline unsigned int socrates_fpga_pic_get_irq(unsigned int irq)
(irq_hw_number_t)i);
}
void socrates_fpga_pic_cascade(unsigned int __irq, struct irq_desc *desc)
static void socrates_fpga_pic_cascade(struct irq_desc *desc)
{
struct irq_chip *chip = irq_desc_get_chip(desc);
unsigned int irq = irq_desc_get_irq(desc);

2
arch/powerpc/platforms/86xx/pic.c
View File

@ -17,7 +17,7 @@
#include <asm/i8259.h>
#ifdef CONFIG_PPC_I8259
static void mpc86xx_8259_cascade(unsigned int irq, struct irq_desc *desc)
static void mpc86xx_8259_cascade(struct irq_desc *desc)
{
struct irq_chip *chip = irq_desc_get_chip(desc);
unsigned int cascade_irq = i8259_irq();

2
arch/powerpc/platforms/8xx/m8xx_setup.c
View File

@ -214,7 +214,7 @@ void mpc8xx_restart(char *cmd)
panic("Restart failed\n");
}
static void cpm_cascade(unsigned int irq, struct irq_desc *desc)
static void cpm_cascade(struct irq_desc *desc)
{
struct irq_chip *chip = irq_desc_get_chip(desc);
int cascade_irq = cpm_get_irq();

2
arch/powerpc/platforms/cell/axon_msi.c
View File

@ -93,7 +93,7 @@ static void msic_dcr_write(struct axon_msic *msic, unsigned int dcr_n, u32 val)
dcr_write(msic->dcr_host, dcr_n, val);
}
static void axon_msi_cascade(unsigned int irq, struct irq_desc *desc)
static void axon_msi_cascade(struct irq_desc *desc)
{
struct irq_chip *chip = irq_desc_get_chip(desc);
struct axon_msic *msic = irq_desc_get_handler_data(desc);

2
arch/powerpc/platforms/cell/interrupt.c
View File

@ -99,7 +99,7 @@ static void iic_ioexc_eoi(struct irq_data *d)
{
}
static void iic_ioexc_cascade(unsigned int __irq, struct irq_desc *desc)
static void iic_ioexc_cascade(struct irq_desc *desc)
{
struct irq_chip *chip = irq_desc_get_chip(desc);
struct cbe_iic_regs __iomem *node_iic =

2
arch/powerpc/platforms/cell/spider-pic.c
View File

@ -199,7 +199,7 @@ static const struct irq_domain_ops spider_host_ops = {
.xlate = spider_host_xlate,
};
static void spider_irq_cascade(unsigned int irq, struct irq_desc *desc)
static void spider_irq_cascade(struct irq_desc *desc)
{
struct irq_chip *chip = irq_desc_get_chip(desc);
struct spider_pic *pic = irq_desc_get_handler_data(desc);

2
arch/powerpc/platforms/chrp/setup.c
View File

@ -363,7 +363,7 @@ void __init chrp_setup_arch(void)
if (ppc_md.progress) ppc_md.progress("Linux/PPC "UTS_RELEASE"\n", 0x0);
}
static void chrp_8259_cascade(unsigned int irq, struct irq_desc *desc)
static void chrp_8259_cascade(struct irq_desc *desc)
{
struct irq_chip *chip = irq_desc_get_chip(desc);
unsigned int cascade_irq = i8259_irq();

3
arch/powerpc/platforms/embedded6xx/hlwd-pic.c
View File

@ -120,8 +120,7 @@ static unsigned int __hlwd_pic_get_irq(struct irq_domain *h)
return irq_linear_revmap(h, irq);
}
static void hlwd_pic_irq_cascade(unsigned int cascade_virq,
struct irq_desc *desc)
static void hlwd_pic_irq_cascade(struct irq_desc *desc)
{
struct irq_chip *chip = irq_desc_get_chip(desc);
struct irq_domain *irq_domain = irq_desc_get_handler_data(desc);

2
arch/powerpc/platforms/embedded6xx/mvme5100.c
View File

@ -42,7 +42,7 @@
static phys_addr_t pci_membase;
static u_char *restart;
static void mvme5100_8259_cascade(unsigned int irq, struct irq_desc *desc)
static void mvme5100_8259_cascade(struct irq_desc *desc)
{
struct irq_chip *chip = irq_desc_get_chip(desc);
unsigned int cascade_irq = i8259_irq();

2
arch/powerpc/platforms/pseries/setup.c
View File

@ -111,7 +111,7 @@ static void __init fwnmi_init(void)
fwnmi_active = 1;
}
static void pseries_8259_cascade(unsigned int irq, struct irq_desc *desc)
static void pseries_8259_cascade(struct irq_desc *desc)
{
struct irq_chip *chip = irq_desc_get_chip(desc);
unsigned int cascade_irq = i8259_irq();

2
arch/powerpc/sysdev/ge/ge_pic.c
View File

@ -91,7 +91,7 @@ static int gef_pic_cascade_irq;
* should be masked out.
*/
void gef_pic_cascade(unsigned int irq, struct irq_desc *desc)
static void gef_pic_cascade(struct irq_desc *desc)
{
struct irq_chip *chip = irq_desc_get_chip(desc);
unsigned int cascade_irq;

2
arch/powerpc/sysdev/ge/ge_pic.h
View File

@ -1,8 +1,6 @@
#ifndef __GEF_PIC_H__
#define __GEF_PIC_H__
void gef_pic_cascade(unsigned int, struct irq_desc *);
unsigned int gef_pic_get_irq(void);
void gef_pic_init(struct device_node *);

2
arch/powerpc/sysdev/mpic.c
View File

@ -1181,7 +1181,7 @@ static int mpic_host_xlate(struct irq_domain *h, struct device_node *ct,
}
/* IRQ handler for a secondary MPIC cascaded from another IRQ controller */
static void mpic_cascade(unsigned int irq, struct irq_desc *desc)
static void mpic_cascade(struct irq_desc *desc)
{
struct irq_chip *chip = irq_desc_get_chip(desc);
struct mpic *mpic = irq_desc_get_handler_data(desc);

4
arch/powerpc/sysdev/qe_lib/qe_ic.c
View File

@ -311,8 +311,8 @@ unsigned int qe_ic_get_high_irq(struct qe_ic *qe_ic)
}
void __init qe_ic_init(struct device_node *node, unsigned int flags,
void (*low_handler)(unsigned int irq, struct irq_desc *desc),
void (*high_handler)(unsigned int irq, struct irq_desc *desc))
void (*low_handler)(struct irq_desc *desc),
void (*high_handler)(struct irq_desc *desc))
{
struct qe_ic *qe_ic;
struct resource res;

2
arch/powerpc/sysdev/tsi108_pci.c
View File

@ -428,7 +428,7 @@ void __init tsi108_pci_int_init(struct device_node *node)
init_pci_source();
}
void tsi108_irq_cascade(unsigned int irq, struct irq_desc *desc)
void tsi108_irq_cascade(struct irq_desc *desc)
{
struct irq_chip *chip = irq_desc_get_chip(desc);
unsigned int cascade_irq = get_pci_source();

2
arch/powerpc/sysdev/uic.c
View File

@ -194,7 +194,7 @@ static const struct irq_domain_ops uic_host_ops = {
.xlate = irq_domain_xlate_twocell,
};
void uic_irq_cascade(unsigned int virq, struct irq_desc *desc)
static void uic_irq_cascade(struct irq_desc *desc)
{
struct irq_chip *chip = irq_desc_get_chip(desc);
struct irq_data *idata = irq_desc_get_irq_data(desc);

2
arch/powerpc/sysdev/xilinx_intc.c
View File

@ -222,7 +222,7 @@ int xilinx_intc_get_irq(void)
/*
* Support code for cascading to 8259 interrupt controllers
*/
static void xilinx_i8259_cascade(unsigned int irq, struct irq_desc *desc)
static void xilinx_i8259_cascade(struct irq_desc *desc)
{
struct irq_chip *chip = irq_desc_get_chip(desc);
unsigned int cascade_irq = i8259_irq();

2
arch/sh/boards/mach-se/7343/irq.c
View File

@ -29,7 +29,7 @@
static void __iomem *se7343_irq_regs;
struct irq_domain *se7343_irq_domain;
static void se7343_irq_demux(unsigned int irq, struct irq_desc *desc)
static void se7343_irq_demux(struct irq_desc *desc)
{
struct irq_data *data = irq_desc_get_irq_data(desc);
struct irq_chip *chip = irq_data_get_irq_chip(data);

2
arch/sh/boards/mach-se/7722/irq.c
View File

@ -28,7 +28,7 @@
static void __iomem *se7722_irq_regs;
struct irq_domain *se7722_irq_domain;
static void se7722_irq_demux(unsigned int irq, struct irq_desc *desc)
static void se7722_irq_demux(struct irq_desc *desc)
{
struct irq_data *data = irq_desc_get_irq_data(desc);
struct irq_chip *chip = irq_data_get_irq_chip(data);

2
arch/sh/boards/mach-se/7724/irq.c
View File

@ -92,7 +92,7 @@ static struct irq_chip se7724_irq_chip __read_mostly = {
.irq_unmask = enable_se7724_irq,
};
static void se7724_irq_demux(unsigned int __irq, struct irq_desc *desc)
static void se7724_irq_demux(struct irq_desc *desc)
{
unsigned int irq = irq_desc_get_irq(desc);
struct fpga_irq set = get_fpga_irq(irq);

2
arch/sh/boards/mach-x3proto/gpio.c
View File

@ -60,7 +60,7 @@ static int x3proto_gpio_to_irq(struct gpio_chip *chip, unsigned gpio)
return virq;
}
static void x3proto_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
static void x3proto_gpio_irq_handler(struct irq_desc *desc)
{
struct irq_data *data = irq_desc_get_irq_data(desc);
struct irq_chip *chip = irq_data_get_irq_chip(data);

2
arch/sh/cchips/hd6446x/hd64461.c
View File

@ -56,7 +56,7 @@ static struct irq_chip hd64461_irq_chip = {
.irq_unmask = hd64461_unmask_irq,
};
static void hd64461_irq_demux(unsigned int irq, struct irq_desc *desc)
static void hd64461_irq_demux(struct irq_desc *desc)
{
unsigned short intv = __raw_readw(HD64461_NIRR);
unsigned int ext_irq = HD64461_IRQBASE;

2
arch/sparc/kernel/leon_kernel.c
View File

@ -53,7 +53,7 @@ static inline unsigned int leon_eirq_get(int cpu)
}
/* Handle one or multiple IRQs from the extended interrupt controller */
static void leon_handle_ext_irq(unsigned int irq, struct irq_desc *desc)
static void leon_handle_ext_irq(struct irq_desc *desc)
{
unsigned int eirq;
struct irq_bucket *p;

2
arch/sparc/kernel/leon_pci_grpci1.c
View File

@ -357,7 +357,7 @@ static struct irq_chip grpci1_irq = {
};
/* Handle one or multiple IRQs from the PCI core */
static void grpci1_pci_flow_irq(unsigned int irq, struct irq_desc *desc)
static void grpci1_pci_flow_irq(struct irq_desc *desc)
{
struct grpci1_priv *priv = grpci1priv;
int i, ack = 0;

2
arch/sparc/kernel/leon_pci_grpci2.c
View File

@ -498,7 +498,7 @@ static struct irq_chip grpci2_irq = {
};
/* Handle one or multiple IRQs from the PCI core */
static void grpci2_pci_flow_irq(unsigned int irq, struct irq_desc *desc)
static void grpci2_pci_flow_irq(struct irq_desc *desc)
{
struct grpci2_priv *priv = grpci2priv;
int i, ack = 0;

5
arch/tile/kernel/pci_gx.c
View File

@ -304,17 +304,16 @@ static struct irq_chip tilegx_legacy_irq_chip = {
* to Linux which just calls handle_level_irq() after clearing the
* MAC INTx Assert status bit associated with this interrupt.
*/
static void trio_handle_level_irq(unsigned int __irq, struct irq_desc *desc)
static void trio_handle_level_irq(struct irq_desc *desc)
{
struct pci_controller *controller = irq_desc_get_handler_data(desc);
gxio_trio_context_t *trio_context = controller->trio;
uint64_t intx = (uint64_t)irq_desc_get_chip_data(desc);
unsigned int irq = irq_desc_get_irq(desc);
int mac = controller->mac;
unsigned int reg_offset;
uint64_t level_mask;
handle_level_irq(irq, desc);
handle_level_irq(desc);
/*
* Clear the INTx Level status, otherwise future interrupts are

2
arch/unicore32/kernel/irq.c
View File

@ -112,7 +112,7 @@ static struct irq_chip puv3_low_gpio_chip = {
* irq_controller_lock held, and IRQs disabled. Decode the IRQ
* and call the handler.
*/
static void puv3_gpio_handler(unsigned int __irq, struct irq_desc *desc)
static void puv3_gpio_handler(struct irq_desc *desc)
{
unsigned int mask, irq;

19
arch/x86/kernel/irq_32.c
View File

@ -68,11 +68,10 @@ static inline void *current_stack(void)
return (void *)(current_stack_pointer() & ~(THREAD_SIZE - 1));
}
static inline int
execute_on_irq_stack(int overflow, struct irq_desc *desc, int irq)
static inline int execute_on_irq_stack(int overflow, struct irq_desc *desc)
{
struct irq_stack *curstk, *irqstk;
u32 *isp, *prev_esp, arg1, arg2;
u32 *isp, *prev_esp, arg1;
curstk = (struct irq_stack *) current_stack();
irqstk = __this_cpu_read(hardirq_stack);
@ -98,8 +97,8 @@ execute_on_irq_stack(int overflow, struct irq_desc *desc, int irq)
asm volatile("xchgl %%ebx,%%esp \n"
"call *%%edi \n"
"movl %%ebx,%%esp \n"
: "=a" (arg1), "=d" (arg2), "=b" (isp)
: "0" (irq), "1" (desc), "2" (isp),
: "=a" (arg1), "=b" (isp)
: "0" (desc), "1" (isp),
"D" (desc->handle_irq)
: "memory", "cc", "ecx");
return 1;
@ -150,19 +149,15 @@ void do_softirq_own_stack(void)
bool handle_irq(struct irq_desc *desc, struct pt_regs *regs)
{
unsigned int irq;
int overflow;
overflow = check_stack_overflow();
int overflow = check_stack_overflow();
if (IS_ERR_OR_NULL(desc))
return false;
irq = irq_desc_get_irq(desc);
if (user_mode(regs) || !execute_on_irq_stack(overflow, desc, irq)) {
if (user_mode(regs) || !execute_on_irq_stack(overflow, desc)) {
if (unlikely(overflow))
print_stack_overflow();
generic_handle_irq_desc(irq, desc);
generic_handle_irq_desc(desc);
}
return true;

2
arch/x86/kernel/irq_64.c
View File

@ -75,6 +75,6 @@ bool handle_irq(struct irq_desc *desc, struct pt_regs *regs)
if (unlikely(IS_ERR_OR_NULL(desc)))
return false;
generic_handle_irq_desc(irq_desc_get_irq(desc), desc);
generic_handle_irq_desc(desc);
return true;
}

2
arch/x86/lguest/boot.c
View File

@ -1015,7 +1015,7 @@ static struct clock_event_device lguest_clockevent = {
* This is the Guest timer interrupt handler (hardware interrupt 0). We just
* call the clockevent infrastructure and it does whatever needs doing.
*/
static void lguest_time_irq(unsigned int irq, struct irq_desc *desc)
static void lguest_time_irq(struct irq_desc *desc)
{
unsigned long flags;

2
drivers/dma/ipu/ipu_irq.c
View File

@ -266,7 +266,7 @@ int ipu_irq_unmap(unsigned int source)
}
/* Chained IRQ handler for IPU function and error interrupt */
static void ipu_irq_handler(unsigned int __irq, struct irq_desc *desc)
static void ipu_irq_handler(struct irq_desc *desc)
{
struct ipu *ipu = irq_desc_get_handler_data(desc);
u32 status;

6
drivers/gpio/gpio-altera.c
View File

@ -201,8 +201,7 @@ static int altera_gpio_direction_output(struct gpio_chip *gc,
return 0;
}
static void altera_gpio_irq_edge_handler(unsigned int irq,
struct irq_desc *desc)
static void altera_gpio_irq_edge_handler(struct irq_desc *desc)
{
struct altera_gpio_chip *altera_gc;
struct irq_chip *chip;
@ -231,8 +230,7 @@ static void altera_gpio_irq_edge_handler(unsigned int irq,
}
static void altera_gpio_irq_leveL_high_handler(unsigned int irq,
struct irq_desc *desc)
static void altera_gpio_irq_leveL_high_handler(struct irq_desc *desc)
{
struct altera_gpio_chip *altera_gc;
struct irq_chip *chip;

2
drivers/gpio/gpio-bcm-kona.c
View File

@ -433,7 +433,7 @@ static int bcm_kona_gpio_irq_set_type(struct irq_data *d, unsigned int type)
return 0;
}
static void bcm_kona_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
static void bcm_kona_gpio_irq_handler(struct irq_desc *desc)
{
void __iomem *reg_base;
int bit, bank_id;

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