Merge branch 'pci/host-qcom' into next
* pci/host-qcom: PCI: qcom: Limit TLP size to 2K to work around hardware issue PCI: qcom: Fix spelling mistake: "asser" -> "assert" PCI: qcom: Reorder to put v0 functions together, v1 functions together, etc PCI: qcom: Add support for IPQ4019 PCIe controller
This commit is contained in:
Bjorn Helgaas
commit
bec36cfa7b
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@ -8,6 +8,7 @@
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- "qcom,pcie-apq8064" for apq8064
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- "qcom,pcie-apq8084" for apq8084
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- "qcom,pcie-msm8996" for msm8996 or apq8096
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- "qcom,pcie-ipq4019" for ipq4019
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- reg:
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Usage: required
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@ -87,7 +88,7 @@
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- "core" Clocks the pcie hw block
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- "phy" Clocks the pcie PHY block
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- clock-names:
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Usage: required for apq8084
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Usage: required for apq8084/ipq4019
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Value type: <stringlist>
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Definition: Should contain the following entries
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- "aux" Auxiliary (AUX) clock
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@ -126,6 +127,23 @@
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Definition: Should contain the following entries
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- "core" Core reset
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- reset-names:
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Usage: required for ipq/apq8064
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Value type: <stringlist>
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Definition: Should contain the following entries
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- "axi_m" AXI master reset
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- "axi_s" AXI slave reset
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- "pipe" PIPE reset
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- "axi_m_vmid" VMID reset
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- "axi_s_xpu" XPU reset
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- "parf" PARF reset
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- "phy" PHY reset
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- "axi_m_sticky" AXI sticky reset
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- "pipe_sticky" PIPE sticky reset
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- "pwr" PWR reset
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- "ahb" AHB reset
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- "phy_ahb" PHY AHB reset
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- power-domains:
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Usage: required for apq8084 and msm8996/apq8096
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Value type: <prop-encoded-array>
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@ -51,6 +51,12 @@
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#define PCIE20_ELBI_SYS_CTRL 0x04
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#define PCIE20_ELBI_SYS_CTRL_LT_ENABLE BIT(0)
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#define PCIE20_AXI_MSTR_RESP_COMP_CTRL0 0x818
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#define CFG_REMOTE_RD_REQ_BRIDGE_SIZE_2K 0x4
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#define CFG_REMOTE_RD_REQ_BRIDGE_SIZE_4K 0x5
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#define PCIE20_AXI_MSTR_RESP_COMP_CTRL1 0x81c
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#define CFG_BRIDGE_SB_INIT BIT(0)
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#define PCIE20_CAP 0x70
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#define PERST_DELAY_US 1000
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@ -86,10 +92,29 @@ struct qcom_pcie_resources_v2 {
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struct clk *pipe_clk;
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};
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struct qcom_pcie_resources_v3 {
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struct clk *aux_clk;
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struct clk *master_clk;
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struct clk *slave_clk;
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struct reset_control *axi_m_reset;
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struct reset_control *axi_s_reset;
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struct reset_control *pipe_reset;
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struct reset_control *axi_m_vmid_reset;
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struct reset_control *axi_s_xpu_reset;
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struct reset_control *parf_reset;
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struct reset_control *phy_reset;
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struct reset_control *axi_m_sticky_reset;
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struct reset_control *pipe_sticky_reset;
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struct reset_control *pwr_reset;
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struct reset_control *ahb_reset;
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struct reset_control *phy_ahb_reset;
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};
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union qcom_pcie_resources {
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struct qcom_pcie_resources_v0 v0;
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struct qcom_pcie_resources_v1 v1;
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struct qcom_pcie_resources_v2 v2;
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struct qcom_pcie_resources_v3 v3;
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};
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struct qcom_pcie;
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@ -133,26 +158,6 @@ static irqreturn_t qcom_pcie_msi_irq_handler(int irq, void *arg)
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return dw_handle_msi_irq(pp);
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}
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static void qcom_pcie_v0_v1_ltssm_enable(struct qcom_pcie *pcie)
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{
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u32 val;
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/* enable link training */
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val = readl(pcie->elbi + PCIE20_ELBI_SYS_CTRL);
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val |= PCIE20_ELBI_SYS_CTRL_LT_ENABLE;
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writel(val, pcie->elbi + PCIE20_ELBI_SYS_CTRL);
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}
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static void qcom_pcie_v2_ltssm_enable(struct qcom_pcie *pcie)
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{
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u32 val;
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/* enable link training */
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val = readl(pcie->parf + PCIE20_PARF_LTSSM);
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val |= BIT(8);
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writel(val, pcie->parf + PCIE20_PARF_LTSSM);
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}
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static int qcom_pcie_establish_link(struct qcom_pcie *pcie)
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{
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struct dw_pcie *pci = pcie->pci;
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@ -167,6 +172,16 @@ static int qcom_pcie_establish_link(struct qcom_pcie *pcie)
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return dw_pcie_wait_for_link(pci);
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}
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static void qcom_pcie_v0_v1_ltssm_enable(struct qcom_pcie *pcie)
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{
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u32 val;
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/* enable link training */
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val = readl(pcie->elbi + PCIE20_ELBI_SYS_CTRL);
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val |= PCIE20_ELBI_SYS_CTRL_LT_ENABLE;
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writel(val, pcie->elbi + PCIE20_ELBI_SYS_CTRL);
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}
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static int qcom_pcie_get_resources_v0(struct qcom_pcie *pcie)
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{
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struct qcom_pcie_resources_v0 *res = &pcie->res.v0;
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@ -217,36 +232,6 @@ static int qcom_pcie_get_resources_v0(struct qcom_pcie *pcie)
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return PTR_ERR_OR_ZERO(res->phy_reset);
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}
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static int qcom_pcie_get_resources_v1(struct qcom_pcie *pcie)
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{
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struct qcom_pcie_resources_v1 *res = &pcie->res.v1;
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struct dw_pcie *pci = pcie->pci;
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struct device *dev = pci->dev;
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res->vdda = devm_regulator_get(dev, "vdda");
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if (IS_ERR(res->vdda))
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return PTR_ERR(res->vdda);
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res->iface = devm_clk_get(dev, "iface");
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if (IS_ERR(res->iface))
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return PTR_ERR(res->iface);
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res->aux = devm_clk_get(dev, "aux");
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if (IS_ERR(res->aux))
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return PTR_ERR(res->aux);
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res->master_bus = devm_clk_get(dev, "master_bus");
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if (IS_ERR(res->master_bus))
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return PTR_ERR(res->master_bus);
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res->slave_bus = devm_clk_get(dev, "slave_bus");
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if (IS_ERR(res->slave_bus))
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return PTR_ERR(res->slave_bus);
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res->core = devm_reset_control_get(dev, "core");
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return PTR_ERR_OR_ZERO(res->core);
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}
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static void qcom_pcie_deinit_v0(struct qcom_pcie *pcie)
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{
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struct qcom_pcie_resources_v0 *res = &pcie->res.v0;
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@ -357,6 +342,13 @@ static int qcom_pcie_init_v0(struct qcom_pcie *pcie)
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/* wait for clock acquisition */
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usleep_range(1000, 1500);
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/* Set the Max TLP size to 2K, instead of using default of 4K */
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writel(CFG_REMOTE_RD_REQ_BRIDGE_SIZE_2K,
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pci->dbi_base + PCIE20_AXI_MSTR_RESP_COMP_CTRL0);
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writel(CFG_BRIDGE_SB_INIT,
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pci->dbi_base + PCIE20_AXI_MSTR_RESP_COMP_CTRL1);
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return 0;
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err_deassert_ahb:
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@ -375,6 +367,36 @@ err_refclk:
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return ret;
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}
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static int qcom_pcie_get_resources_v1(struct qcom_pcie *pcie)
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{
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struct qcom_pcie_resources_v1 *res = &pcie->res.v1;
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struct dw_pcie *pci = pcie->pci;
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struct device *dev = pci->dev;
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res->vdda = devm_regulator_get(dev, "vdda");
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if (IS_ERR(res->vdda))
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return PTR_ERR(res->vdda);
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res->iface = devm_clk_get(dev, "iface");
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if (IS_ERR(res->iface))
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return PTR_ERR(res->iface);
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res->aux = devm_clk_get(dev, "aux");
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if (IS_ERR(res->aux))
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return PTR_ERR(res->aux);
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res->master_bus = devm_clk_get(dev, "master_bus");
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if (IS_ERR(res->master_bus))
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return PTR_ERR(res->master_bus);
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res->slave_bus = devm_clk_get(dev, "slave_bus");
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if (IS_ERR(res->slave_bus))
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return PTR_ERR(res->slave_bus);
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res->core = devm_reset_control_get(dev, "core");
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return PTR_ERR_OR_ZERO(res->core);
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}
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static void qcom_pcie_deinit_v1(struct qcom_pcie *pcie)
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{
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struct qcom_pcie_resources_v1 *res = &pcie->res.v1;
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@ -455,6 +477,16 @@ err_res:
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return ret;
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}
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static void qcom_pcie_v2_ltssm_enable(struct qcom_pcie *pcie)
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{
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u32 val;
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/* enable link training */
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val = readl(pcie->parf + PCIE20_PARF_LTSSM);
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val |= BIT(8);
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writel(val, pcie->parf + PCIE20_PARF_LTSSM);
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}
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static int qcom_pcie_get_resources_v2(struct qcom_pcie *pcie)
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{
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struct qcom_pcie_resources_v2 *res = &pcie->res.v2;
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@ -481,6 +513,17 @@ static int qcom_pcie_get_resources_v2(struct qcom_pcie *pcie)
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return PTR_ERR_OR_ZERO(res->pipe_clk);
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}
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static void qcom_pcie_deinit_v2(struct qcom_pcie *pcie)
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{
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struct qcom_pcie_resources_v2 *res = &pcie->res.v2;
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clk_disable_unprepare(res->pipe_clk);
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clk_disable_unprepare(res->slave_clk);
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clk_disable_unprepare(res->master_clk);
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clk_disable_unprepare(res->cfg_clk);
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clk_disable_unprepare(res->aux_clk);
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}
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static int qcom_pcie_init_v2(struct qcom_pcie *pcie)
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{
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struct qcom_pcie_resources_v2 *res = &pcie->res.v2;
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@ -562,6 +605,285 @@ static int qcom_pcie_post_init_v2(struct qcom_pcie *pcie)
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return 0;
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}
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static int qcom_pcie_get_resources_v3(struct qcom_pcie *pcie)
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{
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struct qcom_pcie_resources_v3 *res = &pcie->res.v3;
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struct dw_pcie *pci = pcie->pci;
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struct device *dev = pci->dev;
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res->aux_clk = devm_clk_get(dev, "aux");
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if (IS_ERR(res->aux_clk))
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return PTR_ERR(res->aux_clk);
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res->master_clk = devm_clk_get(dev, "master_bus");
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if (IS_ERR(res->master_clk))
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return PTR_ERR(res->master_clk);
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res->slave_clk = devm_clk_get(dev, "slave_bus");
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if (IS_ERR(res->slave_clk))
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return PTR_ERR(res->slave_clk);
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res->axi_m_reset = devm_reset_control_get(dev, "axi_m");
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if (IS_ERR(res->axi_m_reset))
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return PTR_ERR(res->axi_m_reset);
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res->axi_s_reset = devm_reset_control_get(dev, "axi_s");
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if (IS_ERR(res->axi_s_reset))
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return PTR_ERR(res->axi_s_reset);
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res->pipe_reset = devm_reset_control_get(dev, "pipe");
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if (IS_ERR(res->pipe_reset))
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return PTR_ERR(res->pipe_reset);
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res->axi_m_vmid_reset = devm_reset_control_get(dev, "axi_m_vmid");
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if (IS_ERR(res->axi_m_vmid_reset))
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return PTR_ERR(res->axi_m_vmid_reset);
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res->axi_s_xpu_reset = devm_reset_control_get(dev, "axi_s_xpu");
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if (IS_ERR(res->axi_s_xpu_reset))
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return PTR_ERR(res->axi_s_xpu_reset);
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res->parf_reset = devm_reset_control_get(dev, "parf");
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if (IS_ERR(res->parf_reset))
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return PTR_ERR(res->parf_reset);
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|
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res->phy_reset = devm_reset_control_get(dev, "phy");
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if (IS_ERR(res->phy_reset))
|
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return PTR_ERR(res->phy_reset);
|
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|
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res->axi_m_sticky_reset = devm_reset_control_get(dev, "axi_m_sticky");
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if (IS_ERR(res->axi_m_sticky_reset))
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return PTR_ERR(res->axi_m_sticky_reset);
|
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|
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res->pipe_sticky_reset = devm_reset_control_get(dev, "pipe_sticky");
|
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if (IS_ERR(res->pipe_sticky_reset))
|
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return PTR_ERR(res->pipe_sticky_reset);
|
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|
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res->pwr_reset = devm_reset_control_get(dev, "pwr");
|
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if (IS_ERR(res->pwr_reset))
|
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return PTR_ERR(res->pwr_reset);
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|
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res->ahb_reset = devm_reset_control_get(dev, "ahb");
|
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if (IS_ERR(res->ahb_reset))
|
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return PTR_ERR(res->ahb_reset);
|
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|
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res->phy_ahb_reset = devm_reset_control_get(dev, "phy_ahb");
|
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if (IS_ERR(res->phy_ahb_reset))
|
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return PTR_ERR(res->phy_ahb_reset);
|
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|
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return 0;
|
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}
|
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|
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static void qcom_pcie_deinit_v3(struct qcom_pcie *pcie)
|
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{
|
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struct qcom_pcie_resources_v3 *res = &pcie->res.v3;
|
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|
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reset_control_assert(res->axi_m_reset);
|
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reset_control_assert(res->axi_s_reset);
|
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reset_control_assert(res->pipe_reset);
|
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reset_control_assert(res->pipe_sticky_reset);
|
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reset_control_assert(res->phy_reset);
|
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reset_control_assert(res->phy_ahb_reset);
|
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reset_control_assert(res->axi_m_sticky_reset);
|
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reset_control_assert(res->pwr_reset);
|
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reset_control_assert(res->ahb_reset);
|
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clk_disable_unprepare(res->aux_clk);
|
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clk_disable_unprepare(res->master_clk);
|
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clk_disable_unprepare(res->slave_clk);
|
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}
|
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|
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static int qcom_pcie_init_v3(struct qcom_pcie *pcie)
|
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{
|
||||
struct qcom_pcie_resources_v3 *res = &pcie->res.v3;
|
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struct dw_pcie *pci = pcie->pci;
|
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struct device *dev = pci->dev;
|
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u32 val;
|
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int ret;
|
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|
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ret = reset_control_assert(res->axi_m_reset);
|
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if (ret) {
|
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dev_err(dev, "cannot assert axi master reset\n");
|
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return ret;
|
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}
|
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|
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ret = reset_control_assert(res->axi_s_reset);
|
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if (ret) {
|
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dev_err(dev, "cannot assert axi slave reset\n");
|
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return ret;
|
||||
}
|
||||
|
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usleep_range(10000, 12000);
|
||||
|
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ret = reset_control_assert(res->pipe_reset);
|
||||
if (ret) {
|
||||
dev_err(dev, "cannot assert pipe reset\n");
|
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return ret;
|
||||
}
|
||||
|
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ret = reset_control_assert(res->pipe_sticky_reset);
|
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if (ret) {
|
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dev_err(dev, "cannot assert pipe sticky reset\n");
|
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return ret;
|
||||
}
|
||||
|
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ret = reset_control_assert(res->phy_reset);
|
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if (ret) {
|
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dev_err(dev, "cannot assert phy reset\n");
|
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return ret;
|
||||
}
|
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|
||||
ret = reset_control_assert(res->phy_ahb_reset);
|
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if (ret) {
|
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dev_err(dev, "cannot assert phy ahb reset\n");
|
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return ret;
|
||||
}
|
||||
|
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usleep_range(10000, 12000);
|
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|
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ret = reset_control_assert(res->axi_m_sticky_reset);
|
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if (ret) {
|
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dev_err(dev, "cannot assert axi master sticky reset\n");
|
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return ret;
|
||||
}
|
||||
|
||||
ret = reset_control_assert(res->pwr_reset);
|
||||
if (ret) {
|
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dev_err(dev, "cannot assert power reset\n");
|
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return ret;
|
||||
}
|
||||
|
||||
ret = reset_control_assert(res->ahb_reset);
|
||||
if (ret) {
|
||||
dev_err(dev, "cannot assert ahb reset\n");
|
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return ret;
|
||||
}
|
||||
|
||||
usleep_range(10000, 12000);
|
||||
|
||||
ret = reset_control_deassert(res->phy_ahb_reset);
|
||||
if (ret) {
|
||||
dev_err(dev, "cannot deassert phy ahb reset\n");
|
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return ret;
|
||||
}
|
||||
|
||||
ret = reset_control_deassert(res->phy_reset);
|
||||
if (ret) {
|
||||
dev_err(dev, "cannot deassert phy reset\n");
|
||||
goto err_rst_phy;
|
||||
}
|
||||
|
||||
ret = reset_control_deassert(res->pipe_reset);
|
||||
if (ret) {
|
||||
dev_err(dev, "cannot deassert pipe reset\n");
|
||||
goto err_rst_pipe;
|
||||
}
|
||||
|
||||
ret = reset_control_deassert(res->pipe_sticky_reset);
|
||||
if (ret) {
|
||||
dev_err(dev, "cannot deassert pipe sticky reset\n");
|
||||
goto err_rst_pipe_sticky;
|
||||
}
|
||||
|
||||
usleep_range(10000, 12000);
|
||||
|
||||
ret = reset_control_deassert(res->axi_m_reset);
|
||||
if (ret) {
|
||||
dev_err(dev, "cannot deassert axi master reset\n");
|
||||
goto err_rst_axi_m;
|
||||
}
|
||||
|
||||
ret = reset_control_deassert(res->axi_m_sticky_reset);
|
||||
if (ret) {
|
||||
dev_err(dev, "cannot deassert axi master sticky reset\n");
|
||||
goto err_rst_axi_m_sticky;
|
||||
}
|
||||
|
||||
ret = reset_control_deassert(res->axi_s_reset);
|
||||
if (ret) {
|
||||
dev_err(dev, "cannot deassert axi slave reset\n");
|
||||
goto err_rst_axi_s;
|
||||
}
|
||||
|
||||
ret = reset_control_deassert(res->pwr_reset);
|
||||
if (ret) {
|
||||
dev_err(dev, "cannot deassert power reset\n");
|
||||
goto err_rst_pwr;
|
||||
}
|
||||
|
||||
ret = reset_control_deassert(res->ahb_reset);
|
||||
if (ret) {
|
||||
dev_err(dev, "cannot deassert ahb reset\n");
|
||||
goto err_rst_ahb;
|
||||
}
|
||||
|
||||
usleep_range(10000, 12000);
|
||||
|
||||
ret = clk_prepare_enable(res->aux_clk);
|
||||
if (ret) {
|
||||
dev_err(dev, "cannot prepare/enable iface clock\n");
|
||||
goto err_clk_aux;
|
||||
}
|
||||
|
||||
ret = clk_prepare_enable(res->master_clk);
|
||||
if (ret) {
|
||||
dev_err(dev, "cannot prepare/enable core clock\n");
|
||||
goto err_clk_axi_m;
|
||||
}
|
||||
|
||||
ret = clk_prepare_enable(res->slave_clk);
|
||||
if (ret) {
|
||||
dev_err(dev, "cannot prepare/enable phy clock\n");
|
||||
goto err_clk_axi_s;
|
||||
}
|
||||
|
||||
/* enable PCIe clocks and resets */
|
||||
val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL);
|
||||
val &= !BIT(0);
|
||||
writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL);
|
||||
|
||||
/* change DBI base address */
|
||||
writel(0, pcie->parf + PCIE20_PARF_DBI_BASE_ADDR);
|
||||
|
||||
/* MAC PHY_POWERDOWN MUX DISABLE */
|
||||
val = readl(pcie->parf + PCIE20_PARF_SYS_CTRL);
|
||||
val &= ~BIT(29);
|
||||
writel(val, pcie->parf + PCIE20_PARF_SYS_CTRL);
|
||||
|
||||
val = readl(pcie->parf + PCIE20_PARF_MHI_CLOCK_RESET_CTRL);
|
||||
val |= BIT(4);
|
||||
writel(val, pcie->parf + PCIE20_PARF_MHI_CLOCK_RESET_CTRL);
|
||||
|
||||
val = readl(pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT_V2);
|
||||
val |= BIT(31);
|
||||
writel(val, pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT_V2);
|
||||
|
||||
return 0;
|
||||
|
||||
err_clk_axi_s:
|
||||
clk_disable_unprepare(res->master_clk);
|
||||
err_clk_axi_m:
|
||||
clk_disable_unprepare(res->aux_clk);
|
||||
err_clk_aux:
|
||||
reset_control_assert(res->ahb_reset);
|
||||
err_rst_ahb:
|
||||
reset_control_assert(res->pwr_reset);
|
||||
err_rst_pwr:
|
||||
reset_control_assert(res->axi_s_reset);
|
||||
err_rst_axi_s:
|
||||
reset_control_assert(res->axi_m_sticky_reset);
|
||||
err_rst_axi_m_sticky:
|
||||
reset_control_assert(res->axi_m_reset);
|
||||
err_rst_axi_m:
|
||||
reset_control_assert(res->pipe_sticky_reset);
|
||||
err_rst_pipe_sticky:
|
||||
reset_control_assert(res->pipe_reset);
|
||||
err_rst_pipe:
|
||||
reset_control_assert(res->phy_reset);
|
||||
err_rst_phy:
|
||||
reset_control_assert(res->phy_ahb_reset);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int qcom_pcie_link_up(struct dw_pcie *pci)
|
||||
{
|
||||
u16 val = readw(pci->dbi_base + PCIE20_CAP + PCI_EXP_LNKSTA);
|
||||
|
|
@ -569,17 +891,6 @@ static int qcom_pcie_link_up(struct dw_pcie *pci)
|
|||
return !!(val & PCI_EXP_LNKSTA_DLLLA);
|
||||
}
|
||||
|
||||
static void qcom_pcie_deinit_v2(struct qcom_pcie *pcie)
|
||||
{
|
||||
struct qcom_pcie_resources_v2 *res = &pcie->res.v2;
|
||||
|
||||
clk_disable_unprepare(res->pipe_clk);
|
||||
clk_disable_unprepare(res->slave_clk);
|
||||
clk_disable_unprepare(res->master_clk);
|
||||
clk_disable_unprepare(res->cfg_clk);
|
||||
clk_disable_unprepare(res->aux_clk);
|
||||
}
|
||||
|
||||
static void qcom_pcie_host_init(struct pcie_port *pp)
|
||||
{
|
||||
struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
|
||||
|
|
@ -665,6 +976,13 @@ static const struct dw_pcie_ops dw_pcie_ops = {
|
|||
.link_up = qcom_pcie_link_up,
|
||||
};
|
||||
|
||||
static const struct qcom_pcie_ops ops_v3 = {
|
||||
.get_resources = qcom_pcie_get_resources_v3,
|
||||
.init = qcom_pcie_init_v3,
|
||||
.deinit = qcom_pcie_deinit_v3,
|
||||
.ltssm_enable = qcom_pcie_v2_ltssm_enable,
|
||||
};
|
||||
|
||||
static int qcom_pcie_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
|
|
@ -755,6 +1073,7 @@ static const struct of_device_id qcom_pcie_match[] = {
|
|||
{ .compatible = "qcom,pcie-apq8064", .data = &ops_v0 },
|
||||
{ .compatible = "qcom,pcie-apq8084", .data = &ops_v1 },
|
||||
{ .compatible = "qcom,pcie-msm8996", .data = &ops_v2 },
|
||||
{ .compatible = "qcom,pcie-ipq4019", .data = &ops_v3 },
|
||||
{ }
|
||||
};
|
||||
|
||||
|
|
|
|||
Loading…
Reference in a new issue