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MLK-17877 ARM64: dts: imx8qxp: change enet to 1.8v timing setting for B0 silicon 

i.MX8QXP B0 silicon config enet IO voltage as 2.5V setting in default,
but MEK and ARM2 board only support 1.8V IO. So change the IO voltage
as 1.8V setting.

Set the MAC RGMII timing as TX no delay and RX delay mode as the default
setting for MEK and ARM2 board.

Since i.MX8QXP B0 silicon ENET IO timing change, to reach better timing
and avoid CRC error, MEK base board and ARM2 cpu board should remove the
driver device for the secord enet port.

Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
pull/10/head
Fugang Duan 2018-03-12 16:22:31 +08:00 committed by Jason Liu
parent 33df3945cd
commit bec9e9bb36
3 changed files with 62 additions and 52 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

56
arch/arm64/boot/dts/freescale/fsl-imx8qxp-lpddr4-arm2.dts
View File

@ -183,37 +183,39 @@
pinctrl_fec1: fec1grp {
fsl,pins = <
SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD 0x000014a0
SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PAD 0x000014a0
SC_P_ENET0_MDC_CONN_ENET0_MDC 0x06000020
SC_P_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020
SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x06000020
SC_P_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x06000020
SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x06000020
SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x06000020
SC_P_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x06000020
SC_P_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x06000020
SC_P_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x06000020
SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x06000020
SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x06000020
SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x06000020
SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x06000020
SC_P_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x06000020
SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x00000060
SC_P_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x00000060
SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x00000060
SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x00000060
SC_P_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x00000060
SC_P_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x00000060
SC_P_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x00000060
SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x00000060
SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x00000060
SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x00000060
SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x00000060
SC_P_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x00000060
>;
};
pinctrl_fec2: fec2grp {
fsl,pins = <
SC_P_ESAI0_SCKR_CONN_ENET1_RGMII_TX_CTL 0x06000020
SC_P_ESAI0_FSR_CONN_ENET1_RGMII_TXC 0x06000020
SC_P_ESAI0_TX4_RX1_CONN_ENET1_RGMII_TXD0 0x06000020
SC_P_ESAI0_TX5_RX0_CONN_ENET1_RGMII_TXD1 0x06000020
SC_P_ESAI0_FST_CONN_ENET1_RGMII_TXD2 0x06000020
SC_P_ESAI0_SCKT_CONN_ENET1_RGMII_TXD3 0x06000020
SC_P_ESAI0_TX0_CONN_ENET1_RGMII_RXC 0x06000020
SC_P_SPDIF0_TX_CONN_ENET1_RGMII_RX_CTL 0x06000020
SC_P_SPDIF0_RX_CONN_ENET1_RGMII_RXD0 0x06000020
SC_P_ESAI0_TX3_RX2_CONN_ENET1_RGMII_RXD1 0x06000020
SC_P_ESAI0_TX2_RX3_CONN_ENET1_RGMII_RXD2 0x06000020
SC_P_ESAI0_TX1_CONN_ENET1_RGMII_RXD3 0x06000020
SC_P_ESAI0_SCKR_CONN_ENET1_RGMII_TX_CTL 0x00000060
SC_P_ESAI0_FSR_CONN_ENET1_RGMII_TXC 0x00000060
SC_P_ESAI0_TX4_RX1_CONN_ENET1_RGMII_TXD0 0x00000060
SC_P_ESAI0_TX5_RX0_CONN_ENET1_RGMII_TXD1 0x00000060
SC_P_ESAI0_FST_CONN_ENET1_RGMII_TXD2 0x00000060
SC_P_ESAI0_SCKT_CONN_ENET1_RGMII_TXD3 0x00000060
SC_P_ESAI0_TX0_CONN_ENET1_RGMII_RXC 0x00000060
SC_P_SPDIF0_TX_CONN_ENET1_RGMII_RX_CTL 0x00000060
SC_P_SPDIF0_RX_CONN_ENET1_RGMII_RXD0 0x00000060
SC_P_ESAI0_TX3_RX2_CONN_ENET1_RGMII_RXD1 0x00000060
SC_P_ESAI0_TX2_RX3_CONN_ENET1_RGMII_RXD2 0x00000060
SC_P_ESAI0_TX1_CONN_ENET1_RGMII_RXD3 0x00000060
>;
};
@ -403,9 +405,10 @@
&fec1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec1>;
phy-mode = "rgmii-id";
phy-mode = "rgmii-txid";
phy-handle = <&ethphy0>;
fsl,magic-packet;
fsl,rgmii_rxc_dly;
status = "okay";
mdio {
@ -432,10 +435,11 @@
&fec2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec2>;
phy-mode = "rgmii-id";
phy-mode = "rgmii-txid";
phy-handle = <&ethphy1>;
phy-supply = <&reg_fec2_supply>;
fsl,magic-packet;
fsl,rgmii_rxc_dly;
status = "disabled";
};

56
arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek.dts
View File

@ -259,37 +259,39 @@
pinctrl_fec1: fec1grp {
fsl,pins = <
SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD 0x000014a0
SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PAD 0x000014a0
SC_P_ENET0_MDC_CONN_ENET0_MDC 0x06000020
SC_P_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020
SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x06000020
SC_P_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x06000020
SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x06000020
SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x06000020
SC_P_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x06000020
SC_P_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x06000020
SC_P_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x06000020
SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x06000020
SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x06000020
SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x06000020
SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x06000020
SC_P_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x06000020
SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x00000060
SC_P_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x00000060
SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x00000060
SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x00000060
SC_P_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x00000060
SC_P_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x00000060
SC_P_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x00000060
SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x00000060
SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x00000060
SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x00000060
SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x00000060
SC_P_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x00000060
>;
};
pinctrl_fec2: fec2grp {
fsl,pins = <
SC_P_ESAI0_SCKR_CONN_ENET1_RGMII_TX_CTL 0x06000020
SC_P_ESAI0_FSR_CONN_ENET1_RGMII_TXC 0x06000020
SC_P_ESAI0_TX4_RX1_CONN_ENET1_RGMII_TXD0 0x06000020
SC_P_ESAI0_TX5_RX0_CONN_ENET1_RGMII_TXD1 0x06000020
SC_P_ESAI0_FST_CONN_ENET1_RGMII_TXD2 0x06000020
SC_P_ESAI0_SCKT_CONN_ENET1_RGMII_TXD3 0x06000020
SC_P_ESAI0_TX0_CONN_ENET1_RGMII_RXC 0x06000020
SC_P_SPDIF0_TX_CONN_ENET1_RGMII_RX_CTL 0x06000020
SC_P_SPDIF0_RX_CONN_ENET1_RGMII_RXD0 0x06000020
SC_P_ESAI0_TX3_RX2_CONN_ENET1_RGMII_RXD1 0x06000020
SC_P_ESAI0_TX2_RX3_CONN_ENET1_RGMII_RXD2 0x06000020
SC_P_ESAI0_TX1_CONN_ENET1_RGMII_RXD3 0x06000020
SC_P_ESAI0_SCKR_CONN_ENET1_RGMII_TX_CTL 0x00000060
SC_P_ESAI0_FSR_CONN_ENET1_RGMII_TXC 0x00000060
SC_P_ESAI0_TX4_RX1_CONN_ENET1_RGMII_TXD0 0x00000060
SC_P_ESAI0_TX5_RX0_CONN_ENET1_RGMII_TXD1 0x00000060
SC_P_ESAI0_FST_CONN_ENET1_RGMII_TXD2 0x00000060
SC_P_ESAI0_SCKT_CONN_ENET1_RGMII_TXD3 0x00000060
SC_P_ESAI0_TX0_CONN_ENET1_RGMII_RXC 0x00000060
SC_P_SPDIF0_TX_CONN_ENET1_RGMII_RX_CTL 0x00000060
SC_P_SPDIF0_RX_CONN_ENET1_RGMII_RXD0 0x00000060
SC_P_ESAI0_TX3_RX2_CONN_ENET1_RGMII_RXD1 0x00000060
SC_P_ESAI0_TX2_RX3_CONN_ENET1_RGMII_RXD2 0x00000060
SC_P_ESAI0_TX1_CONN_ENET1_RGMII_RXD3 0x00000060
>;
};
@ -499,9 +501,10 @@
&fec1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec1>;
phy-mode = "rgmii-id";
phy-mode = "rgmii-txid";
phy-handle = <&ethphy0>;
fsl,magic-packet;
fsl,rgmii_rxc_dly;
status = "okay";
mdio {
@ -528,10 +531,11 @@
&fec2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec2>;
phy-mode = "rgmii-id";
phy-mode = "rgmii-txid";
phy-handle = <&ethphy1>;
phy-supply = <&reg_fec2_supply>;
fsl,magic-packet;
fsl,rgmii_rxc_dly;
status = "disabled";
};

2
include/dt-bindings/pinctrl/pads-imx8qxp.h
View File

@ -328,6 +328,7 @@
#define SC_P_ENET0_RGMII_TXD3_CONN_MLB_SIG SC_P_ENET0_RGMII_TXD3 1
#define SC_P_ENET0_RGMII_TXD3_CONN_NAND_RE_B SC_P_ENET0_RGMII_TXD3 2
#define SC_P_ENET0_RGMII_TXD3_LSIO_GPIO5_IO02 SC_P_ENET0_RGMII_TXD3 4
#define SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0 0
#define SC_P_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC SC_P_ENET0_RGMII_RXC 0
#define SC_P_ENET0_RGMII_RXC_CONN_MLB_DATA SC_P_ENET0_RGMII_RXC 1
#define SC_P_ENET0_RGMII_RXC_CONN_NAND_WE_B SC_P_ENET0_RGMII_RXC 2
@ -350,6 +351,7 @@
#define SC_P_ENET0_RGMII_RXD3_CONN_NAND_ALE SC_P_ENET0_RGMII_RXD3 2
#define SC_P_ENET0_RGMII_RXD3_CONN_USDHC1_DATA3 SC_P_ENET0_RGMII_RXD3 3
#define SC_P_ENET0_RGMII_RXD3_LSIO_GPIO5_IO08 SC_P_ENET0_RGMII_RXD3 4
#define SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1 0
#define SC_P_ENET0_REFCLK_125M_25M_CONN_ENET0_REFCLK_125M_25M SC_P_ENET0_REFCLK_125M_25M 0
#define SC_P_ENET0_REFCLK_125M_25M_CONN_ENET0_PPS SC_P_ENET0_REFCLK_125M_25M 1
#define SC_P_ENET0_REFCLK_125M_25M_CONN_ENET1_PPS SC_P_ENET0_REFCLK_125M_25M 2