[BNX2]: Fix link change handling
Fix some link-related problems by doing a coalesce_now after link change interrupt to flush out the transient link status. To facilitate this, the host coalesce cmd register value is cached in the device structure. Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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ca6549af77
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@ -313,8 +313,6 @@ bnx2_disable_int(struct bnx2 *bp)
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static void
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bnx2_enable_int(struct bnx2 *bp)
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{
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u32 val;
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REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
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BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
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BNX2_PCICFG_INT_ACK_CMD_MASK_INT | bp->last_status_idx);
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@ -322,8 +320,7 @@ bnx2_enable_int(struct bnx2 *bp)
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REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
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BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | bp->last_status_idx);
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val = REG_RD(bp, BNX2_HC_COMMAND);
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REG_WR(bp, BNX2_HC_COMMAND, val | BNX2_HC_COMMAND_COAL_NOW);
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REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW);
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}
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static void
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@ -1926,6 +1923,13 @@ bnx2_poll(struct net_device *dev, int *budget)
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spin_lock(&bp->phy_lock);
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bnx2_phy_int(bp);
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spin_unlock(&bp->phy_lock);
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/* This is needed to take care of transient status
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* during link changes.
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*/
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REG_WR(bp, BNX2_HC_COMMAND,
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bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
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REG_RD(bp, BNX2_HC_COMMAND);
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}
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if (bp->status_blk->status_tx_quick_consumer_index0 != bp->hw_tx_cons)
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@ -3307,6 +3311,8 @@ bnx2_init_chip(struct bnx2 *bp)
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udelay(20);
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bp->hc_cmd = REG_RD(bp, BNX2_HC_COMMAND);
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return rc;
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}
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@ -3746,7 +3752,6 @@ bnx2_run_loopback(struct bnx2 *bp, int loopback_mode)
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struct sk_buff *skb, *rx_skb;
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unsigned char *packet;
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u16 rx_start_idx, rx_idx;
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u32 val;
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dma_addr_t map;
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struct tx_bd *txbd;
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struct sw_bd *rx_buf;
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@ -3777,8 +3782,9 @@ bnx2_run_loopback(struct bnx2 *bp, int loopback_mode)
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map = pci_map_single(bp->pdev, skb->data, pkt_size,
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PCI_DMA_TODEVICE);
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val = REG_RD(bp, BNX2_HC_COMMAND);
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REG_WR(bp, BNX2_HC_COMMAND, val | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
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REG_WR(bp, BNX2_HC_COMMAND,
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bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
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REG_RD(bp, BNX2_HC_COMMAND);
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udelay(5);
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@ -3802,8 +3808,9 @@ bnx2_run_loopback(struct bnx2 *bp, int loopback_mode)
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udelay(100);
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val = REG_RD(bp, BNX2_HC_COMMAND);
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REG_WR(bp, BNX2_HC_COMMAND, val | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
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REG_WR(bp, BNX2_HC_COMMAND,
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bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
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REG_RD(bp, BNX2_HC_COMMAND);
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udelay(5);
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@ -3939,7 +3946,6 @@ static int
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bnx2_test_intr(struct bnx2 *bp)
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{
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int i;
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u32 val;
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u16 status_idx;
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if (!netif_running(bp->dev))
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@ -3948,8 +3954,7 @@ bnx2_test_intr(struct bnx2 *bp)
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status_idx = REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff;
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/* This register is not touched during run-time. */
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val = REG_RD(bp, BNX2_HC_COMMAND);
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REG_WR(bp, BNX2_HC_COMMAND, val | BNX2_HC_COMMAND_COAL_NOW);
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REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW);
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REG_RD(bp, BNX2_HC_COMMAND);
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for (i = 0; i < 10; i++) {
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@ -4038,6 +4038,7 @@ struct bnx2 {
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struct statistics_block *stats_blk;
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dma_addr_t stats_blk_mapping;
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u32 hc_cmd;
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u32 rx_mode;
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u16 req_line_speed;
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