Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus
Pull MIPS updates from Ralf Baechle:
"This is the main pull request for MIPS for Linux 4.1. Most
noteworthy:
- Add more Octeon-optimized crypto functions
- Octeon crypto preemption and locking fixes
- Little endian support for Octeon
- Use correct CSR to soft reset Octeons
- Support LEDs on the Octeon-based DSR-1000N
- Fix PCI interrupt mapping for the Octeon-based DSR-1000N
- Mark prom_free_prom_memory() as __init for a number of systems
- Support for Imagination's Pistachio SOC. This includes arch and
CLK bits. I'd like to merge pinctrl bits later
- Improve parallelism of csum_partial for certain pipelines
- Organize DTB files in subdirs like other architectures
- Implement read_sched_clock for all MIPS platforms other than
Octeon
- Massive series of 38 fixes and cleanups for the FPU emulator /
kernel
- Further FPU remulator work to support new features. This sits on a
separate branch which also has been pulled into the 4.1 KVM branch
- Clean up and fixes for the SEAD3 eval board; remove unused file
- Various updates for Netlogic platforms
- A number of small updates for Loongson 3 platforms
- Increase the memory limit for ATH79 platforms to 256MB
- A fair number of fixes and updates for BCM47xx platforms
- Finish the implementation of XPA support
- MIPS FDC support. No, not floppy controller but Fast Debug Channel :)
- Detect the R16000 used in SGI legacy platforms
- Fix Kconfig dependencies for the SSB bus support"
* 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (265 commits)
MIPS: Makefile: Fix MIPS ASE detection code
MIPS: asm: elf: Set O32 default FPU flags
MIPS: BCM47XX: Fix detecting Microsoft MN-700 & Asus WL500G
MIPS: Kconfig: Disable SMP/CPS for 64-bit
MIPS: Hibernate: flush TLB entries earlier
MIPS: smp-cps: cpu_set FPU mask if FPU present
MIPS: lose_fpu(): Disable FPU when MSA enabled
MIPS: ralink: add missing symbol for RALINK_ILL_ACC
MIPS: ralink: Fix bad config symbol in PCI makefile.
SSB: fix Kconfig dependencies
MIPS: Malta: Detect and fix bad memsize values
Revert "MIPS: Avoid pipeline stalls on some MIPS32R2 cores."
MIPS: Octeon: Delete override of cpu_has_mips_r2_exec_hazard.
MIPS: Fix cpu_has_mips_r2_exec_hazard.
MIPS: kernel: entry.S: Set correct ISA level for mips_ihb
MIPS: asm: spinlock: Fix addiu instruction for R10000_LLSC_WAR case
MIPS: r4kcache: Use correct base register for MIPS R6 cache flushes
MIPS: Kconfig: Fix typo for the r2-to-r6 emulator kernel parameter
MIPS: unaligned: Fix regular load/store instruction emulation for EVA
MIPS: unaligned: Surround load/store macros in do {} while statements
...
wifi-calibration
Linus Torvalds
commit
bfaf245022
|
|
@ -95,8 +95,7 @@ since it doesn't need to allocate a table as large as the largest
|
|||
hwirq number. The disadvantage is that hwirq to IRQ number lookup is
|
||||
dependent on how many entries are in the table.
|
||||
|
||||
Very few drivers should need this mapping. At the moment, powerpc
|
||||
iseries is the only user.
|
||||
Very few drivers should need this mapping.
|
||||
|
||||
==== No Map ===-
|
||||
irq_domain_add_nomap()
|
||||
|
|
|
|||
|
|
@ -0,0 +1,123 @@
|
|||
Imagination Technologies Pistachio SoC clock controllers
|
||||
========================================================
|
||||
|
||||
Pistachio has four clock controllers (core clock, peripheral clock, peripheral
|
||||
general control, and top general control) which are instantiated individually
|
||||
from the device-tree.
|
||||
|
||||
External clocks:
|
||||
----------------
|
||||
|
||||
There are three external inputs to the clock controllers which should be
|
||||
defined with the following clock-output-names:
|
||||
- "xtal": External 52Mhz oscillator (required)
|
||||
- "audio_clk_in": Alternate audio reference clock (optional)
|
||||
- "enet_clk_in": Alternate ethernet PHY clock (optional)
|
||||
|
||||
Core clock controller:
|
||||
----------------------
|
||||
|
||||
The core clock controller generates clocks for the CPU, RPU (WiFi + BT
|
||||
co-processor), audio, and several peripherals.
|
||||
|
||||
Required properties:
|
||||
- compatible: Must be "img,pistachio-clk".
|
||||
- reg: Must contain the base address and length of the core clock controller.
|
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- #clock-cells: Must be 1. The single cell is the clock identifier.
|
||||
See dt-bindings/clock/pistachio-clk.h for the list of valid identifiers.
|
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- clocks: Must contain an entry for each clock in clock-names.
|
||||
- clock-names: Must include "xtal" (see "External clocks") and
|
||||
"audio_clk_in_gate", "enet_clk_in_gate" which are generated by the
|
||||
top-level general control.
|
||||
|
||||
Example:
|
||||
clk_core: clock-controller@18144000 {
|
||||
compatible = "img,pistachio-clk";
|
||||
reg = <0x18144000 0x800>;
|
||||
clocks = <&xtal>, <&cr_top EXT_CLK_AUDIO_IN>,
|
||||
<&cr_top EXT_CLK_ENET_IN>;
|
||||
clock-names = "xtal", "audio_clk_in_gate", "enet_clk_in_gate";
|
||||
|
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#clock-cells = <1>;
|
||||
};
|
||||
|
||||
Peripheral clock controller:
|
||||
----------------------------
|
||||
|
||||
The peripheral clock controller generates clocks for the DDR, ROM, and other
|
||||
peripherals. The peripheral system clock ("periph_sys") generated by the core
|
||||
clock controller is the input clock to the peripheral clock controller.
|
||||
|
||||
Required properties:
|
||||
- compatible: Must be "img,pistachio-periph-clk".
|
||||
- reg: Must contain the base address and length of the peripheral clock
|
||||
controller.
|
||||
- #clock-cells: Must be 1. The single cell is the clock identifier.
|
||||
See dt-bindings/clock/pistachio-clk.h for the list of valid identifiers.
|
||||
- clocks: Must contain an entry for each clock in clock-names.
|
||||
- clock-names: Must include "periph_sys", the peripheral system clock generated
|
||||
by the core clock controller.
|
||||
|
||||
Example:
|
||||
clk_periph: clock-controller@18144800 {
|
||||
compatible = "img,pistachio-clk-periph";
|
||||
reg = <0x18144800 0x800>;
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||||
clocks = <&clk_core CLK_PERIPH_SYS>;
|
||||
clock-names = "periph_sys";
|
||||
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
Peripheral general control:
|
||||
---------------------------
|
||||
|
||||
The peripheral general control block generates system interface clocks and
|
||||
resets for various peripherals. It also contains miscellaneous peripheral
|
||||
control registers. The system clock ("sys") generated by the peripheral clock
|
||||
controller is the input clock to the system clock controller.
|
||||
|
||||
Required properties:
|
||||
- compatible: Must include "img,pistachio-periph-cr" and "syscon".
|
||||
- reg: Must contain the base address and length of the peripheral general
|
||||
control registers.
|
||||
- #clock-cells: Must be 1. The single cell is the clock identifier.
|
||||
See dt-bindings/clock/pistachio-clk.h for the list of valid identifiers.
|
||||
- clocks: Must contain an entry for each clock in clock-names.
|
||||
- clock-names: Must include "sys", the system clock generated by the peripheral
|
||||
clock controller.
|
||||
|
||||
Example:
|
||||
cr_periph: syscon@18144800 {
|
||||
compatible = "img,pistachio-cr-periph", "syscon";
|
||||
reg = <0x18148000 0x1000>;
|
||||
clocks = <&clock_periph PERIPH_CLK_PERIPH_SYS>;
|
||||
clock-names = "sys";
|
||||
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
Top-level general control:
|
||||
--------------------------
|
||||
|
||||
The top-level general control block contains miscellaneous control registers and
|
||||
gates for the external clocks "audio_clk_in" and "enet_clk_in".
|
||||
|
||||
Required properties:
|
||||
- compatible: Must include "img,pistachio-cr-top" and "syscon".
|
||||
- reg: Must contain the base address and length of the top-level
|
||||
control registers.
|
||||
- clocks: Must contain an entry for each clock in clock-names.
|
||||
- clock-names: Two optional clocks, "audio_clk_in" and "enet_clk_in" (see
|
||||
"External clocks").
|
||||
- #clock-cells: Must be 1. The single cell is the clock identifier.
|
||||
See dt-bindings/clock/pistachio-clk.h for the list of valid identifiers.
|
||||
|
||||
Example:
|
||||
cr_top: syscon@18144800 {
|
||||
compatible = "img,pistachio-cr-top", "syscon";
|
||||
reg = <0x18149000 0x200>;
|
||||
clocks = <&audio_refclk>, <&ext_enet_in>;
|
||||
clock-names = "audio_clk_in", "enet_clk_in";
|
||||
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
|
@ -0,0 +1,41 @@
|
|||
Broadcom BCM3380-style Level 1 / Level 2 interrupt controller
|
||||
|
||||
This interrupt controller shows up in various forms on many BCM338x/BCM63xx
|
||||
chipsets. It has the following properties:
|
||||
|
||||
- outputs a single interrupt signal to its interrupt controller parent
|
||||
|
||||
- contains one or more enable/status word pairs, which often appear at
|
||||
different offsets in different blocks
|
||||
|
||||
- no atomic set/clear operations
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible: should be "brcm,bcm3380-l2-intc"
|
||||
- reg: specifies one or more enable/status pairs, in the following format:
|
||||
<enable_reg 0x4 status_reg 0x4>...
|
||||
- interrupt-controller: identifies the node as an interrupt controller
|
||||
- #interrupt-cells: specifies the number of cells needed to encode an interrupt
|
||||
source, should be 1.
|
||||
- interrupt-parent: specifies the phandle to the parent interrupt controller
|
||||
this one is cascaded from
|
||||
- interrupts: specifies the interrupt line in the interrupt-parent controller
|
||||
node, valid values depend on the type of parent interrupt controller
|
||||
|
||||
Optional properties:
|
||||
|
||||
- brcm,irq-can-wake: if present, this means the L2 controller can be used as a
|
||||
wakeup source for system suspend/resume.
|
||||
|
||||
Example:
|
||||
|
||||
irq0_intc: interrupt-controller@10000020 {
|
||||
compatible = "brcm,bcm3380-l2-intc";
|
||||
reg = <0x10000024 0x4 0x1000002c 0x4>,
|
||||
<0x10000020 0x4 0x10000028 0x4>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-parent = <&cpu_intc>;
|
||||
interrupts = <2>;
|
||||
};
|
||||
|
|
@ -0,0 +1,52 @@
|
|||
Broadcom BCM7038-style Level 1 interrupt controller
|
||||
|
||||
This block is a first level interrupt controller that is typically connected
|
||||
directly to one of the HW INT lines on each CPU. Every BCM7xxx set-top chip
|
||||
since BCM7038 has contained this hardware.
|
||||
|
||||
Key elements of the hardware design include:
|
||||
|
||||
- 64, 96, 128, or 160 incoming level IRQ lines
|
||||
|
||||
- Most onchip peripherals are wired directly to an L1 input
|
||||
|
||||
- A separate instance of the register set for each CPU, allowing individual
|
||||
peripheral IRQs to be routed to any CPU
|
||||
|
||||
- Atomic mask/unmask operations
|
||||
|
||||
- No polarity/level/edge settings
|
||||
|
||||
- No FIFO or priority encoder logic; software is expected to read all
|
||||
2-5 status words to determine which IRQs are pending
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible: should be "brcm,bcm7038-l1-intc"
|
||||
- reg: specifies the base physical address and size of the registers;
|
||||
the number of supported IRQs is inferred from the size argument
|
||||
- interrupt-controller: identifies the node as an interrupt controller
|
||||
- #interrupt-cells: specifies the number of cells needed to encode an interrupt
|
||||
source, should be 1.
|
||||
- interrupt-parent: specifies the phandle to the parent interrupt controller(s)
|
||||
this one is cascaded from
|
||||
- interrupts: specifies the interrupt line(s) in the interrupt-parent controller
|
||||
node; valid values depend on the type of parent interrupt controller
|
||||
|
||||
If multiple reg ranges and interrupt-parent entries are present on an SMP
|
||||
system, the driver will allow IRQ SMP affinity to be set up through the
|
||||
/proc/irq/ interface. In the simplest possible configuration, only one
|
||||
reg range and one interrupt-parent is needed.
|
||||
|
||||
Example:
|
||||
|
||||
periph_intc: periph_intc@1041a400 {
|
||||
compatible = "brcm,bcm7038-l1-intc";
|
||||
reg = <0x1041a400 0x30 0x1041a600 0x30>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
|
||||
interrupt-parent = <&cpu_intc>;
|
||||
interrupts = <2>, <3>;
|
||||
};
|
||||
|
|
@ -13,8 +13,7 @@ Such an interrupt controller has the following hardware design:
|
|||
or if they will output an interrupt signal at this 2nd level interrupt
|
||||
controller, in particular for UARTs
|
||||
|
||||
- typically has one 32-bit enable word and one 32-bit status word, but on
|
||||
some hardware may have more than one enable/status pair
|
||||
- has one 32-bit enable word and one 32-bit status word
|
||||
|
||||
- no atomic set/clear operations
|
||||
|
||||
|
|
@ -53,9 +52,7 @@ The typical hardware layout for this controller is represented below:
|
|||
Required properties:
|
||||
|
||||
- compatible: should be "brcm,bcm7120-l2-intc"
|
||||
- reg: specifies the base physical address and size of the registers;
|
||||
multiple pairs may be specified, with the first pair handling IRQ offsets
|
||||
0..31 and the second pair handling 32..63
|
||||
- reg: specifies the base physical address and size of the registers
|
||||
- interrupt-controller: identifies the node as an interrupt controller
|
||||
- #interrupt-cells: specifies the number of cells needed to encode an interrupt
|
||||
source, should be 1.
|
||||
|
|
@ -66,10 +63,7 @@ Required properties:
|
|||
- brcm,int-map-mask: 32-bits bit mask describing how many and which interrupts
|
||||
are wired to this 2nd level interrupt controller, and how they match their
|
||||
respective interrupt parents. Should match exactly the number of interrupts
|
||||
specified in the 'interrupts' property, multiplied by the number of
|
||||
enable/status register pairs implemented by this controller. For
|
||||
multiple parent IRQs with multiple enable/status words, this looks like:
|
||||
<irq0_w0 irq0_w1 irq1_w0 irq1_w1 ...>
|
||||
specified in the 'interrupts' property.
|
||||
|
||||
Optional properties:
|
||||
|
||||
|
|
|
|||
|
|
@ -27,8 +27,13 @@ Optional properties:
|
|||
Required properties for timer sub-node:
|
||||
- compatible : Should be "mti,gic-timer".
|
||||
- interrupts : Interrupt for the GIC local timer.
|
||||
|
||||
Optional properties for timer sub-node:
|
||||
- clocks : GIC timer operating clock.
|
||||
- clock-frequency : Clock frequency at which the GIC timers operate.
|
||||
|
||||
Note that one of clocks or clock-frequency must be specified.
|
||||
|
||||
Example:
|
||||
|
||||
gic: interrupt-controller@1bdc0000 {
|
||||
|
|
|
|||
|
|
@ -1,37 +0,0 @@
|
|||
* Interrupt Controller
|
||||
|
||||
Properties:
|
||||
- compatible: "brcm,bcm3384-intc"
|
||||
|
||||
Compatibility with BCM3384 and possibly other BCM33xx/BCM63xx SoCs.
|
||||
|
||||
- reg: Address/length pairs for each mask/status register set. Length must
|
||||
be 8. If multiple register sets are specified, the first set will
|
||||
handle IRQ offsets 0..31, the second set 32..63, and so on.
|
||||
|
||||
- interrupt-controller: This is an interrupt controller.
|
||||
|
||||
- #interrupt-cells: Must be <1>. Just a simple IRQ offset; no level/edge
|
||||
or polarity configuration is possible with this controller.
|
||||
|
||||
- interrupt-parent: This controller is cascaded from a MIPS CPU HW IRQ, or
|
||||
from another INTC.
|
||||
|
||||
- interrupts: The IRQ on the parent controller.
|
||||
|
||||
Example:
|
||||
periph_intc: periph_intc@14e00038 {
|
||||
compatible = "brcm,bcm3384-intc";
|
||||
|
||||
/*
|
||||
* IRQs 0..31: mask reg 0x14e00038, status reg 0x14e0003c
|
||||
* IRQs 32..63: mask reg 0x14e00340, status reg 0x14e00344
|
||||
*/
|
||||
reg = <0x14e00038 0x8 0x14e00340 0x8>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
|
||||
interrupt-parent = <&cpu_intc>;
|
||||
interrupts = <4>;
|
||||
};
|
||||
|
|
@ -1,11 +0,0 @@
|
|||
* Broadcom cable/DSL platforms
|
||||
|
||||
SoCs:
|
||||
|
||||
Required properties:
|
||||
- compatible: "brcm,bcm3384", "brcm,bcm33843"
|
||||
|
||||
Boards:
|
||||
|
||||
Required properties:
|
||||
- compatible: "brcm,bcm93384wvg"
|
||||
|
|
@ -0,0 +1,12 @@
|
|||
* Broadcom cable/DSL/settop platforms
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible: "brcm,bcm3384", "brcm,bcm33843"
|
||||
"brcm,bcm3384-viper", "brcm,bcm33843-viper"
|
||||
"brcm,bcm6328", "brcm,bcm6368",
|
||||
"brcm,bcm7125", "brcm,bcm7346", "brcm,bcm7358", "brcm,bcm7360",
|
||||
"brcm,bcm7362", "brcm,bcm7420", "brcm,bcm7425"
|
||||
|
||||
The experimental -viper variants are for running Linux on the 3384's
|
||||
BMIPS4355 cable modem CPU instead of the BMIPS5000 application processor.
|
||||
|
|
@ -0,0 +1,42 @@
|
|||
Imagination Pistachio SoC
|
||||
=========================
|
||||
|
||||
Required properties:
|
||||
--------------------
|
||||
- compatible: Must include "img,pistachio".
|
||||
|
||||
CPU nodes:
|
||||
----------
|
||||
A "cpus" node is required. Required properties:
|
||||
- #address-cells: Must be 1.
|
||||
- #size-cells: Must be 0.
|
||||
A CPU sub-node is also required for at least CPU 0. Since the topology may
|
||||
be probed via CPS, it is not necessary to specify secondary CPUs. Required
|
||||
propertis:
|
||||
- device_type: Must be "cpu".
|
||||
- compatible: Must be "mti,interaptiv".
|
||||
- reg: CPU number.
|
||||
- clocks: Must include the CPU clock. See ../../clock/clock-bindings.txt for
|
||||
details on clock bindings.
|
||||
Example:
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu0: cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "mti,interaptiv";
|
||||
reg = <0>;
|
||||
clocks = <&clk_core CLK_MIPS>;
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
Boot protocol:
|
||||
--------------
|
||||
In accordance with the MIPS UHI specification[1], the bootloader must pass the
|
||||
following arguments to the kernel:
|
||||
- $a0: -2.
|
||||
- $a1: KSEG0 address of the flattened device-tree blob.
|
||||
|
||||
[1] http://prplfoundation.org/wiki/MIPS_documentation
|
||||
|
|
@ -15,6 +15,7 @@ Table of Contents
|
|||
1) Entry point for arch/arm
|
||||
2) Entry point for arch/powerpc
|
||||
3) Entry point for arch/x86
|
||||
4) Entry point for arch/mips/bmips
|
||||
|
||||
II - The DT block format
|
||||
1) Header
|
||||
|
|
@ -288,6 +289,33 @@ it with special cases.
|
|||
or initrd address. It simply holds information which can not be retrieved
|
||||
otherwise like interrupt routing or a list of devices behind an I2C bus.
|
||||
|
||||
4) Entry point for arch/mips/bmips
|
||||
----------------------------------
|
||||
|
||||
Some bootloaders only support a single entry point, at the start of the
|
||||
kernel image. Other bootloaders will jump to the ELF start address.
|
||||
Both schemes are supported; CONFIG_BOOT_RAW=y and CONFIG_NO_EXCEPT_FILL=y,
|
||||
so the first instruction immediately jumps to kernel_entry().
|
||||
|
||||
Similar to the arch/arm case (b), a DT-aware bootloader is expected to
|
||||
set up the following registers:
|
||||
|
||||
a0 : 0
|
||||
|
||||
a1 : 0xffffffff
|
||||
|
||||
a2 : Physical pointer to the device tree block (defined in chapter
|
||||
II) in RAM. The device tree can be located anywhere in the first
|
||||
512MB of the physical address space (0x00000000 - 0x1fffffff),
|
||||
aligned on a 64 bit boundary.
|
||||
|
||||
Legacy bootloaders do not use this convention, and they do not pass in a
|
||||
DT block. In this case, Linux will look for a builtin DTB, selected via
|
||||
CONFIG_DT_*.
|
||||
|
||||
This convention is defined for 32-bit systems only, as there are not
|
||||
currently any 64-bit BMIPS implementations.
|
||||
|
||||
II - The DT block format
|
||||
========================
|
||||
|
||||
|
|
|
|||
|
|
@ -2317,7 +2317,7 @@ bytes respectively. Such letter suffixes can also be entirely omitted.
|
|||
noexec32=off: disable non-executable mappings
|
||||
read implies executable mappings
|
||||
|
||||
nofpu [SH] Disable hardware FPU at boot time.
|
||||
nofpu [MIPS,SH] Disable hardware FPU at boot time.
|
||||
|
||||
nofxsr [BUGS=X86-32] Disables x86 floating point extended
|
||||
register save and restore. The kernel will only save
|
||||
|
|
|
|||
|
|
@ -4,9 +4,9 @@ platforms += alchemy
|
|||
platforms += ar7
|
||||
platforms += ath25
|
||||
platforms += ath79
|
||||
platforms += bcm3384
|
||||
platforms += bcm47xx
|
||||
platforms += bcm63xx
|
||||
platforms += bmips
|
||||
platforms += cavium-octeon
|
||||
platforms += cobalt
|
||||
platforms += dec
|
||||
|
|
@ -21,6 +21,7 @@ platforms += mti-malta
|
|||
platforms += mti-sead3
|
||||
platforms += netlogic
|
||||
platforms += paravirt
|
||||
platforms += pistachio
|
||||
platforms += pmcs-msp71xx
|
||||
platforms += pnx833x
|
||||
platforms += ralink
|
||||
|
|
|
|||
|
|
@ -43,6 +43,7 @@ config MIPS
|
|||
select GENERIC_SMP_IDLE_THREAD
|
||||
select BUILDTIME_EXTABLE_SORT
|
||||
select GENERIC_CLOCKEVENTS
|
||||
select GENERIC_SCHED_CLOCK if !CAVIUM_OCTEON_SOC
|
||||
select GENERIC_CMOS_UPDATE
|
||||
select HAVE_MOD_ARCH_SPECIFIC
|
||||
select VIRT_TO_BUS
|
||||
|
|
@ -55,6 +56,8 @@ config MIPS
|
|||
select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
|
||||
select ARCH_BINFMT_ELF_STATE
|
||||
select SYSCTL_EXCEPTION_TRACE
|
||||
select HAVE_VIRT_CPU_ACCOUNTING_GEN
|
||||
select HAVE_IRQ_TIME_ACCOUNTING
|
||||
|
||||
menu "Machine selection"
|
||||
|
||||
|
|
@ -131,8 +134,8 @@ config ATH79
|
|||
help
|
||||
Support for the Atheros AR71XX/AR724X/AR913X SoCs.
|
||||
|
||||
config BCM3384
|
||||
bool "Broadcom BCM3384 based boards"
|
||||
config BMIPS_GENERIC
|
||||
bool "Broadcom Generic BMIPS kernel"
|
||||
select BOOT_RAW
|
||||
select NO_EXCEPT_FILL
|
||||
select USE_OF
|
||||
|
|
@ -140,22 +143,30 @@ config BCM3384
|
|||
select CSRC_R4K
|
||||
select SYNC_R4K
|
||||
select COMMON_CLK
|
||||
select DMA_NONCOHERENT
|
||||
select BCM7038_L1_IRQ
|
||||
select BCM7120_L2_IRQ
|
||||
select BRCMSTB_L2_IRQ
|
||||
select IRQ_CPU
|
||||
select RAW_IRQ_ACCESSORS
|
||||
select DMA_NONCOHERENT
|
||||
select SYS_SUPPORTS_32BIT_KERNEL
|
||||
select SYS_SUPPORTS_LITTLE_ENDIAN
|
||||
select SYS_SUPPORTS_BIG_ENDIAN
|
||||
select SYS_SUPPORTS_HIGHMEM
|
||||
select SYS_HAS_CPU_BMIPS32_3300
|
||||
select SYS_HAS_CPU_BMIPS4350
|
||||
select SYS_HAS_CPU_BMIPS4380
|
||||
select SYS_HAS_CPU_BMIPS5000
|
||||
select SWAP_IO_SPACE
|
||||
select USB_EHCI_BIG_ENDIAN_DESC
|
||||
select USB_EHCI_BIG_ENDIAN_MMIO
|
||||
select USB_OHCI_BIG_ENDIAN_DESC
|
||||
select USB_OHCI_BIG_ENDIAN_MMIO
|
||||
select USB_EHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
|
||||
select USB_EHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
|
||||
select USB_OHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
|
||||
select USB_OHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
|
||||
help
|
||||
Support for BCM3384 based boards. BCM3384/BCM33843 is a cable modem
|
||||
chipset with a Linux application processor that is often used to
|
||||
provide Samba services, a CUPS print server, and/or advanced routing
|
||||
features.
|
||||
Build a generic DT-based kernel image that boots on select
|
||||
BCM33xx cable modem chips, BCM63xx DSL chips, and BCM7xxx set-top
|
||||
box chips. Note that CONFIG_CPU_BIG_ENDIAN/CONFIG_CPU_LITTLE_ENDIAN
|
||||
must be set appropriately for your board.
|
||||
|
||||
config BCM47XX
|
||||
bool "Broadcom BCM47XX based boards"
|
||||
|
|
@ -352,6 +363,33 @@ config MACH_LOONGSON1
|
|||
the ICT (Institute of Computing Technology) and the Chinese Academy
|
||||
of Sciences.
|
||||
|
||||
config MACH_PISTACHIO
|
||||
bool "IMG Pistachio SoC based boards"
|
||||
select ARCH_REQUIRE_GPIOLIB
|
||||
select BOOT_ELF32
|
||||
select BOOT_RAW
|
||||
select CEVT_R4K
|
||||
select CLKSRC_MIPS_GIC
|
||||
select COMMON_CLK
|
||||
select CSRC_R4K
|
||||
select DMA_MAYBE_COHERENT
|
||||
select IRQ_CPU
|
||||
select LIBFDT
|
||||
select MFD_SYSCON
|
||||
select MIPS_CPU_SCACHE
|
||||
select MIPS_GIC
|
||||
select PINCTRL
|
||||
select REGULATOR
|
||||
select SYS_HAS_CPU_MIPS32_R2
|
||||
select SYS_SUPPORTS_32BIT_KERNEL
|
||||
select SYS_SUPPORTS_LITTLE_ENDIAN
|
||||
select SYS_SUPPORTS_MIPS_CPS
|
||||
select SYS_SUPPORTS_MULTITHREADING
|
||||
select SYS_SUPPORTS_ZBOOT
|
||||
select USE_OF
|
||||
help
|
||||
This enables support for the IMG Pistachio SoC platform.
|
||||
|
||||
config MIPS_MALTA
|
||||
bool "MIPS Malta board"
|
||||
select ARCH_MAY_HAVE_PC_FDC
|
||||
|
|
@ -377,6 +415,7 @@ config MIPS_MALTA
|
|||
select SYS_HAS_CPU_MIPS32_R1
|
||||
select SYS_HAS_CPU_MIPS32_R2
|
||||
select SYS_HAS_CPU_MIPS32_R3_5
|
||||
select SYS_HAS_CPU_MIPS32_R5
|
||||
select SYS_HAS_CPU_MIPS32_R6
|
||||
select SYS_HAS_CPU_MIPS64_R1
|
||||
select SYS_HAS_CPU_MIPS64_R2
|
||||
|
|
@ -386,6 +425,7 @@ config MIPS_MALTA
|
|||
select SYS_SUPPORTS_32BIT_KERNEL
|
||||
select SYS_SUPPORTS_64BIT_KERNEL
|
||||
select SYS_SUPPORTS_BIG_ENDIAN
|
||||
select SYS_SUPPORTS_HIGHMEM
|
||||
select SYS_SUPPORTS_LITTLE_ENDIAN
|
||||
select SYS_SUPPORTS_MICROMIPS
|
||||
select SYS_SUPPORTS_MIPS_CMP
|
||||
|
|
@ -779,7 +819,8 @@ config CAVIUM_OCTEON_SOC
|
|||
select SYS_SUPPORTS_64BIT_KERNEL
|
||||
select SYS_SUPPORTS_BIG_ENDIAN
|
||||
select EDAC_SUPPORT
|
||||
select SYS_SUPPORTS_HOTPLUG_CPU
|
||||
select SYS_SUPPORTS_LITTLE_ENDIAN
|
||||
select SYS_SUPPORTS_HOTPLUG_CPU if CPU_BIG_ENDIAN
|
||||
select SYS_HAS_EARLY_PRINTK
|
||||
select SYS_HAS_CPU_CAVIUM_OCTEON
|
||||
select SWAP_IO_SPACE
|
||||
|
|
@ -793,6 +834,7 @@ config CAVIUM_OCTEON_SOC
|
|||
select SYS_SUPPORTS_SMP
|
||||
select NR_CPUS_DEFAULT_16
|
||||
select BUILTIN_DTB
|
||||
select MTD_COMPLEX_MAPPINGS
|
||||
help
|
||||
This option supports all of the Octeon reference boards from Cavium
|
||||
Networks. It builds a kernel that dynamically determines the Octeon
|
||||
|
|
@ -887,6 +929,7 @@ source "arch/mips/ath25/Kconfig"
|
|||
source "arch/mips/ath79/Kconfig"
|
||||
source "arch/mips/bcm47xx/Kconfig"
|
||||
source "arch/mips/bcm63xx/Kconfig"
|
||||
source "arch/mips/bmips/Kconfig"
|
||||
source "arch/mips/jazz/Kconfig"
|
||||
source "arch/mips/jz4740/Kconfig"
|
||||
source "arch/mips/lantiq/Kconfig"
|
||||
|
|
@ -1202,10 +1245,10 @@ config MIPS_L1_CACHE_SHIFT_7
|
|||
|
||||
config MIPS_L1_CACHE_SHIFT
|
||||
int
|
||||
default "4" if MIPS_L1_CACHE_SHIFT_4
|
||||
default "5" if MIPS_L1_CACHE_SHIFT_5
|
||||
default "6" if MIPS_L1_CACHE_SHIFT_6
|
||||
default "7" if MIPS_L1_CACHE_SHIFT_7
|
||||
default "6" if MIPS_L1_CACHE_SHIFT_6
|
||||
default "5" if MIPS_L1_CACHE_SHIFT_5
|
||||
default "4" if MIPS_L1_CACHE_SHIFT_4
|
||||
default "5"
|
||||
|
||||
config HAVE_STD_PC_SERIAL_PORT
|
||||
|
|
@ -1572,6 +1615,7 @@ config CPU_XLP
|
|||
select WEAK_REORDERING_BEYOND_LLSC
|
||||
select CPU_HAS_PREFETCH
|
||||
select CPU_MIPSR2
|
||||
select CPU_SUPPORTS_HUGEPAGES
|
||||
help
|
||||
Netlogic Microsystems XLP processors.
|
||||
endchoice
|
||||
|
|
@ -1596,6 +1640,33 @@ config CPU_MIPS32_3_5_EVA
|
|||
One of its primary benefits is an increase in the maximum size
|
||||
of lowmem (up to 3GB). If unsure, say 'N' here.
|
||||
|
||||
config CPU_MIPS32_R5_FEATURES
|
||||
bool "MIPS32 Release 5 Features"
|
||||
depends on SYS_HAS_CPU_MIPS32_R5
|
||||
depends on CPU_MIPS32_R2
|
||||
help
|
||||
Choose this option to build a kernel for release 2 or later of the
|
||||
MIPS32 architecture including features from release 5 such as
|
||||
support for Extended Physical Addressing (XPA).
|
||||
|
||||
config CPU_MIPS32_R5_XPA
|
||||
bool "Extended Physical Addressing (XPA)"
|
||||
depends on CPU_MIPS32_R5_FEATURES
|
||||
depends on !EVA
|
||||
depends on !PAGE_SIZE_4KB
|
||||
depends on SYS_SUPPORTS_HIGHMEM
|
||||
select XPA
|
||||
select HIGHMEM
|
||||
select ARCH_PHYS_ADDR_T_64BIT
|
||||
default n
|
||||
help
|
||||
Choose this option if you want to enable the Extended Physical
|
||||
Addressing (XPA) on your MIPS32 core (such as P5600 series). The
|
||||
benefit is to increase physical addressing equal to or greater
|
||||
than 40 bits. Note that this has the side effect of turning on
|
||||
64-bit addressing which in turn makes the PTEs 64-bit in size.
|
||||
If unsure, say 'N' here.
|
||||
|
||||
if CPU_LOONGSON2F
|
||||
config CPU_NOP_WORKAROUNDS
|
||||
bool
|
||||
|
|
@ -1699,6 +1770,9 @@ config SYS_HAS_CPU_MIPS32_R2
|
|||
config SYS_HAS_CPU_MIPS32_R3_5
|
||||
bool
|
||||
|
||||
config SYS_HAS_CPU_MIPS32_R5
|
||||
bool
|
||||
|
||||
config SYS_HAS_CPU_MIPS32_R6
|
||||
bool
|
||||
|
||||
|
|
@ -1836,6 +1910,9 @@ config CPU_MIPSR6
|
|||
config EVA
|
||||
bool
|
||||
|
||||
config XPA
|
||||
bool
|
||||
|
||||
config SYS_SUPPORTS_32BIT_KERNEL
|
||||
bool
|
||||
config SYS_SUPPORTS_64BIT_KERNEL
|
||||
|
|
@ -2072,7 +2149,7 @@ config MIPSR2_TO_R6_EMULATOR
|
|||
help
|
||||
Choose this option if you want to run non-R6 MIPS userland code.
|
||||
Even if you say 'Y' here, the emulator will still be disabled by
|
||||
default. You can enable it using the 'mipsr2emul' kernel option.
|
||||
default. You can enable it using the 'mipsr2emu' kernel option.
|
||||
The only reason this is a build-time option is to save ~14K from the
|
||||
final kernel image.
|
||||
comment "MIPS R2-to-R6 emulator is only available for UP kernels"
|
||||
|
|
@ -2142,7 +2219,7 @@ config MIPS_CMP
|
|||
|
||||
config MIPS_CPS
|
||||
bool "MIPS Coherent Processing System support"
|
||||
depends on SYS_SUPPORTS_MIPS_CPS
|
||||
depends on SYS_SUPPORTS_MIPS_CPS && !64BIT
|
||||
select MIPS_CM
|
||||
select MIPS_CPC
|
||||
select MIPS_CPS_PM if HOTPLUG_CPU
|
||||
|
|
@ -2348,7 +2425,7 @@ config NODES_SHIFT
|
|||
|
||||
config HW_PERF_EVENTS
|
||||
bool "Enable hardware performance counter support for perf events"
|
||||
depends on PERF_EVENTS && OPROFILE=n && (CPU_MIPS32 || CPU_MIPS64 || CPU_R10000 || CPU_SB1 || CPU_CAVIUM_OCTEON || CPU_XLP)
|
||||
depends on PERF_EVENTS && OPROFILE=n && (CPU_MIPS32 || CPU_MIPS64 || CPU_R10000 || CPU_SB1 || CPU_CAVIUM_OCTEON || CPU_XLP || CPU_LOONGSON3)
|
||||
default y
|
||||
help
|
||||
Enable hardware performance counter support for perf events. If
|
||||
|
|
@ -2500,6 +2577,9 @@ config HZ
|
|||
default 1000 if HZ_1000
|
||||
default 1024 if HZ_1024
|
||||
|
||||
config SCHED_HRTICK
|
||||
def_bool HIGH_RES_TIMERS
|
||||
|
||||
source "kernel/Kconfig.preempt"
|
||||
|
||||
config KEXEC
|
||||
|
|
|
|||
|
|
@ -197,11 +197,17 @@ endif
|
|||
# Warning: the 64-bit MIPS architecture does not support the `smartmips' extension
|
||||
# Pass -Wa,--no-warn to disable all assembler warnings until the kernel code has
|
||||
# been fixed properly.
|
||||
mips-cflags := "$(cflags-y)"
|
||||
cflags-$(CONFIG_CPU_HAS_SMARTMIPS) += $(call cc-option,$(mips-cflags),-msmartmips) -Wa,--no-warn
|
||||
cflags-$(CONFIG_CPU_MICROMIPS) += $(call cc-option,$(mips-cflags),-mmicromips)
|
||||
mips-cflags := $(cflags-y)
|
||||
ifeq ($(CONFIG_CPU_HAS_SMARTMIPS),y)
|
||||
smartmips-ase := $(call cc-option-yn,$(mips-cflags) -msmartmips)
|
||||
cflags-$(smartmips-ase) += -msmartmips -Wa,--no-warn
|
||||
endif
|
||||
ifeq ($(CONFIG_CPU_MICROMIPS),y)
|
||||
micromips-ase := $(call cc-option-yn,$(mips-cflags) -mmicromips)
|
||||
cflags-$(micromips-ase) += -mmicromips
|
||||
endif
|
||||
ifeq ($(CONFIG_CPU_HAS_MSA),y)
|
||||
toolchain-msa := $(call cc-option-yn,-$(mips-cflags),mhard-float -mfp64 -Wa$(comma)-mmsa)
|
||||
toolchain-msa := $(call cc-option-yn,$(mips-cflags) -mhard-float -mfp64 -Wa$(comma)-mmsa)
|
||||
cflags-$(toolchain-msa) += -DTOOLCHAIN_SUPPORTS_MSA
|
||||
endif
|
||||
|
||||
|
|
@ -365,7 +371,11 @@ core-$(CONFIG_BUILTIN_DTB) += arch/mips/boot/dts/
|
|||
|
||||
PHONY += dtbs
|
||||
dtbs: scripts
|
||||
$(Q)$(MAKE) $(build)=arch/mips/boot/dts dtbs
|
||||
$(Q)$(MAKE) $(build)=arch/mips/boot/dts
|
||||
|
||||
PHONY += dtbs_install
|
||||
dtbs_install:
|
||||
$(Q)$(MAKE) $(dtbinst)=arch/mips/boot/dts
|
||||
|
||||
archprepare:
|
||||
ifdef CONFIG_MIPS32_N32
|
||||
|
|
@ -407,6 +417,7 @@ define archhelp
|
|||
echo ' uImage.lzma - U-Boot image (lzma)'
|
||||
echo ' uImage.lzo - U-Boot image (lzo)'
|
||||
echo ' dtbs - Device-tree blobs for enabled boards'
|
||||
echo ' dtbs_install - Install dtbs to $(INSTALL_DTBS_PATH)'
|
||||
echo
|
||||
echo ' These will be default as appropriate for a configured platform.'
|
||||
endef
|
||||
|
|
|
|||
|
|
@ -307,10 +307,7 @@ static void __init cpmac_get_mac(int instance, unsigned char *dev_addr)
|
|||
}
|
||||
|
||||
if (mac) {
|
||||
if (sscanf(mac, "%hhx:%hhx:%hhx:%hhx:%hhx:%hhx",
|
||||
&dev_addr[0], &dev_addr[1],
|
||||
&dev_addr[2], &dev_addr[3],
|
||||
&dev_addr[4], &dev_addr[5]) != 6) {
|
||||
if (!mac_pton(mac, dev_addr)) {
|
||||
pr_warn("cannot parse mac address, using random address\n");
|
||||
eth_random_addr(dev_addr);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -17,7 +17,7 @@
|
|||
#include <linux/types.h>
|
||||
|
||||
#define ATH79_MEM_SIZE_MIN (2 * 1024 * 1024)
|
||||
#define ATH79_MEM_SIZE_MAX (128 * 1024 * 1024)
|
||||
#define ATH79_MEM_SIZE_MAX (256 * 1024 * 1024)
|
||||
|
||||
void ath79_clocks_init(void);
|
||||
unsigned long ath79_get_sys_clk_rate(const char *id);
|
||||
|
|
|
|||
|
|
@ -1,7 +0,0 @@
|
|||
#
|
||||
# Broadcom BCM3384 boards
|
||||
#
|
||||
platform-$(CONFIG_BCM3384) += bcm3384/
|
||||
cflags-$(CONFIG_BCM3384) += \
|
||||
-I$(srctree)/arch/mips/include/asm/mach-bcm3384/
|
||||
load-$(CONFIG_BCM3384) := 0xffffffff80010000
|
||||
|
|
@ -1,81 +0,0 @@
|
|||
/*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*
|
||||
* Copyright (C) 2014 Kevin Cernekee <cernekee@gmail.com>
|
||||
*/
|
||||
|
||||
#include <linux/device.h>
|
||||
#include <linux/dma-direction.h>
|
||||
#include <linux/dma-mapping.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/mm.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/pci.h>
|
||||
#include <linux/types.h>
|
||||
#include <dma-coherence.h>
|
||||
|
||||
/*
|
||||
* BCM3384 has configurable address translation windows which allow the
|
||||
* peripherals' DMA addresses to be different from the Zephyr-visible
|
||||
* physical addresses. e.g. usb_dma_addr = zephyr_pa ^ 0x08000000
|
||||
*
|
||||
* If our DT "memory" node has a "dma-xor-mask" property we will enable this
|
||||
* translation using the provided offset.
|
||||
*/
|
||||
static u32 bcm3384_dma_xor_mask;
|
||||
static u32 bcm3384_dma_xor_limit = 0xffffffff;
|
||||
|
||||
/*
|
||||
* PCI collapses the memory hole at 0x10000000 - 0x1fffffff.
|
||||
* On systems with a dma-xor-mask, this range is guaranteed to live above
|
||||
* the dma-xor-limit.
|
||||
*/
|
||||
#define BCM3384_MEM_HOLE_PA 0x10000000
|
||||
#define BCM3384_MEM_HOLE_SIZE 0x10000000
|
||||
|
||||
static dma_addr_t bcm3384_phys_to_dma(struct device *dev, phys_addr_t pa)
|
||||
{
|
||||
if (dev && dev_is_pci(dev) &&
|
||||
pa >= (BCM3384_MEM_HOLE_PA + BCM3384_MEM_HOLE_SIZE))
|
||||
return pa - BCM3384_MEM_HOLE_SIZE;
|
||||
if (pa <= bcm3384_dma_xor_limit)
|
||||
return pa ^ bcm3384_dma_xor_mask;
|
||||
return pa;
|
||||
}
|
||||
|
||||
dma_addr_t plat_map_dma_mem(struct device *dev, void *addr, size_t size)
|
||||
{
|
||||
return bcm3384_phys_to_dma(dev, virt_to_phys(addr));
|
||||
}
|
||||
|
||||
dma_addr_t plat_map_dma_mem_page(struct device *dev, struct page *page)
|
||||
{
|
||||
return bcm3384_phys_to_dma(dev, page_to_phys(page));
|
||||
}
|
||||
|
||||
unsigned long plat_dma_addr_to_phys(struct device *dev, dma_addr_t dma_addr)
|
||||
{
|
||||
if (dev && dev_is_pci(dev) &&
|
||||
dma_addr >= BCM3384_MEM_HOLE_PA)
|
||||
return dma_addr + BCM3384_MEM_HOLE_SIZE;
|
||||
if ((dma_addr ^ bcm3384_dma_xor_mask) <= bcm3384_dma_xor_limit)
|
||||
return dma_addr ^ bcm3384_dma_xor_mask;
|
||||
return dma_addr;
|
||||
}
|
||||
|
||||
static int __init bcm3384_init_dma_xor(void)
|
||||
{
|
||||
struct device_node *np = of_find_node_by_type(NULL, "memory");
|
||||
|
||||
if (!np)
|
||||
return 0;
|
||||
|
||||
of_property_read_u32(np, "dma-xor-mask", &bcm3384_dma_xor_mask);
|
||||
of_property_read_u32(np, "dma-xor-limit", &bcm3384_dma_xor_limit);
|
||||
|
||||
of_node_put(np);
|
||||
return 0;
|
||||
}
|
||||
arch_initcall(bcm3384_init_dma_xor);
|
||||
|
|
@ -1,193 +0,0 @@
|
|||
/*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License version 2 as published
|
||||
* by the Free Software Foundation.
|
||||
*
|
||||
* Partially based on arch/mips/ralink/irq.c
|
||||
*
|
||||
* Copyright (C) 2009 Gabor Juhos <juhosg@openwrt.org>
|
||||
* Copyright (C) 2013 John Crispin <blogic@openwrt.org>
|
||||
* Copyright (C) 2014 Kevin Cernekee <cernekee@gmail.com>
|
||||
*/
|
||||
|
||||
#include <linux/io.h>
|
||||
#include <linux/bitops.h>
|
||||
#include <linux/of_platform.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/of_irq.h>
|
||||
#include <linux/irqdomain.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/spinlock.h>
|
||||
|
||||
#include <asm/bmips.h>
|
||||
#include <asm/irq_cpu.h>
|
||||
#include <asm/mipsregs.h>
|
||||
|
||||
/* INTC register offsets */
|
||||
#define INTC_REG_ENABLE 0x00
|
||||
#define INTC_REG_STATUS 0x04
|
||||
|
||||
#define MAX_WORDS 2
|
||||
#define IRQS_PER_WORD 32
|
||||
|
||||
struct bcm3384_intc {
|
||||
int n_words;
|
||||
void __iomem *reg[MAX_WORDS];
|
||||
u32 enable[MAX_WORDS];
|
||||
spinlock_t lock;
|
||||
};
|
||||
|
||||
static void bcm3384_intc_irq_unmask(struct irq_data *d)
|
||||
{
|
||||
struct bcm3384_intc *priv = d->domain->host_data;
|
||||
unsigned long flags;
|
||||
int idx = d->hwirq / IRQS_PER_WORD;
|
||||
int bit = d->hwirq % IRQS_PER_WORD;
|
||||
|
||||
spin_lock_irqsave(&priv->lock, flags);
|
||||
priv->enable[idx] |= BIT(bit);
|
||||
__raw_writel(priv->enable[idx], priv->reg[idx] + INTC_REG_ENABLE);
|
||||
spin_unlock_irqrestore(&priv->lock, flags);
|
||||
}
|
||||
|
||||
static void bcm3384_intc_irq_mask(struct irq_data *d)
|
||||
{
|
||||
struct bcm3384_intc *priv = d->domain->host_data;
|
||||
unsigned long flags;
|
||||
int idx = d->hwirq / IRQS_PER_WORD;
|
||||
int bit = d->hwirq % IRQS_PER_WORD;
|
||||
|
||||
spin_lock_irqsave(&priv->lock, flags);
|
||||
priv->enable[idx] &= ~BIT(bit);
|
||||
__raw_writel(priv->enable[idx], priv->reg[idx] + INTC_REG_ENABLE);
|
||||
spin_unlock_irqrestore(&priv->lock, flags);
|
||||
}
|
||||
|
||||
static struct irq_chip bcm3384_intc_irq_chip = {
|
||||
.name = "INTC",
|
||||
.irq_unmask = bcm3384_intc_irq_unmask,
|
||||
.irq_mask = bcm3384_intc_irq_mask,
|
||||
.irq_mask_ack = bcm3384_intc_irq_mask,
|
||||
};
|
||||
|
||||
unsigned int get_c0_compare_int(void)
|
||||
{
|
||||
return CP0_LEGACY_COMPARE_IRQ;
|
||||
}
|
||||
|
||||
static void bcm3384_intc_irq_handler(unsigned int irq, struct irq_desc *desc)
|
||||
{
|
||||
struct irq_domain *domain = irq_get_handler_data(irq);
|
||||
struct bcm3384_intc *priv = domain->host_data;
|
||||
unsigned long flags;
|
||||
unsigned int idx;
|
||||
|
||||
for (idx = 0; idx < priv->n_words; idx++) {
|
||||
unsigned long pending;
|
||||
int hwirq;
|
||||
|
||||
spin_lock_irqsave(&priv->lock, flags);
|
||||
pending = __raw_readl(priv->reg[idx] + INTC_REG_STATUS) &
|
||||
priv->enable[idx];
|
||||
spin_unlock_irqrestore(&priv->lock, flags);
|
||||
|
||||
for_each_set_bit(hwirq, &pending, IRQS_PER_WORD) {
|
||||
generic_handle_irq(irq_find_mapping(domain,
|
||||
hwirq + idx * IRQS_PER_WORD));
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
asmlinkage void plat_irq_dispatch(void)
|
||||
{
|
||||
unsigned long pending =
|
||||
(read_c0_status() & read_c0_cause() & ST0_IM) >> STATUSB_IP0;
|
||||
int bit;
|
||||
|
||||
for_each_set_bit(bit, &pending, 8)
|
||||
do_IRQ(MIPS_CPU_IRQ_BASE + bit);
|
||||
}
|
||||
|
||||
static int intc_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
|
||||
{
|
||||
irq_set_chip_and_handler(irq, &bcm3384_intc_irq_chip, handle_level_irq);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct irq_domain_ops irq_domain_ops = {
|
||||
.xlate = irq_domain_xlate_onecell,
|
||||
.map = intc_map,
|
||||
};
|
||||
|
||||
static int __init ioremap_one_pair(struct bcm3384_intc *priv,
|
||||
struct device_node *node,
|
||||
int idx)
|
||||
{
|
||||
struct resource res;
|
||||
|
||||
if (of_address_to_resource(node, idx, &res))
|
||||
return 0;
|
||||
|
||||
if (request_mem_region(res.start, resource_size(&res),
|
||||
res.name) < 0)
|
||||
pr_err("Failed to request INTC register region\n");
|
||||
|
||||
priv->reg[idx] = ioremap_nocache(res.start, resource_size(&res));
|
||||
if (!priv->reg[idx])
|
||||
panic("Failed to ioremap INTC register range");
|
||||
|
||||
/* start up with everything masked before we hook the parent IRQ */
|
||||
__raw_writel(0, priv->reg[idx] + INTC_REG_ENABLE);
|
||||
priv->enable[idx] = 0;
|
||||
|
||||
return IRQS_PER_WORD;
|
||||
}
|
||||
|
||||
static int __init intc_of_init(struct device_node *node,
|
||||
struct device_node *parent)
|
||||
{
|
||||
struct irq_domain *domain;
|
||||
unsigned int parent_irq, n_irqs = 0;
|
||||
struct bcm3384_intc *priv;
|
||||
|
||||
priv = kzalloc(sizeof(*priv), GFP_KERNEL);
|
||||
if (!priv)
|
||||
panic("Failed to allocate bcm3384_intc struct");
|
||||
|
||||
spin_lock_init(&priv->lock);
|
||||
|
||||
parent_irq = irq_of_parse_and_map(node, 0);
|
||||
if (!parent_irq)
|
||||
panic("Failed to get INTC IRQ");
|
||||
|
||||
n_irqs += ioremap_one_pair(priv, node, 0);
|
||||
n_irqs += ioremap_one_pair(priv, node, 1);
|
||||
|
||||
if (!n_irqs)
|
||||
panic("Failed to map INTC registers");
|
||||
|
||||
priv->n_words = n_irqs / IRQS_PER_WORD;
|
||||
domain = irq_domain_add_linear(node, n_irqs, &irq_domain_ops, priv);
|
||||
if (!domain)
|
||||
panic("Failed to add irqdomain");
|
||||
|
||||
irq_set_chained_handler(parent_irq, bcm3384_intc_irq_handler);
|
||||
irq_set_handler_data(parent_irq, domain);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct of_device_id of_irq_ids[] __initdata = {
|
||||
{ .compatible = "mti,cpu-interrupt-controller",
|
||||
.data = mips_cpu_irq_of_init },
|
||||
{ .compatible = "brcm,bcm3384-intc",
|
||||
.data = intc_of_init },
|
||||
{},
|
||||
};
|
||||
|
||||
void __init arch_init_irq(void)
|
||||
{
|
||||
bmips_tp1_irqs = 0;
|
||||
of_irq_init(of_irq_ids);
|
||||
}
|
||||
|
|
@ -1,97 +0,0 @@
|
|||
/*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*
|
||||
* Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
|
||||
* Copyright (C) 2014 Kevin Cernekee <cernekee@gmail.com>
|
||||
*/
|
||||
|
||||
#include <linux/init.h>
|
||||
#include <linux/bootmem.h>
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/ioport.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_fdt.h>
|
||||
#include <linux/of_platform.h>
|
||||
#include <linux/smp.h>
|
||||
#include <asm/addrspace.h>
|
||||
#include <asm/bmips.h>
|
||||
#include <asm/bootinfo.h>
|
||||
#include <asm/prom.h>
|
||||
#include <asm/smp-ops.h>
|
||||
#include <asm/time.h>
|
||||
|
||||
void __init prom_init(void)
|
||||
{
|
||||
register_bmips_smp_ops();
|
||||
}
|
||||
|
||||
void __init prom_free_prom_memory(void)
|
||||
{
|
||||
}
|
||||
|
||||
const char *get_system_type(void)
|
||||
{
|
||||
return "BCM3384";
|
||||
}
|
||||
|
||||
void __init plat_time_init(void)
|
||||
{
|
||||
struct device_node *np;
|
||||
u32 freq;
|
||||
|
||||
np = of_find_node_by_name(NULL, "cpus");
|
||||
if (!np)
|
||||
panic("missing 'cpus' DT node");
|
||||
if (of_property_read_u32(np, "mips-hpt-frequency", &freq) < 0)
|
||||
panic("missing 'mips-hpt-frequency' property");
|
||||
of_node_put(np);
|
||||
|
||||
mips_hpt_frequency = freq;
|
||||
}
|
||||
|
||||
void __init plat_mem_setup(void)
|
||||
{
|
||||
void *dtb = __dtb_start;
|
||||
|
||||
set_io_port_base(0);
|
||||
ioport_resource.start = 0;
|
||||
ioport_resource.end = ~0;
|
||||
|
||||
/* intended to somewhat resemble ARM; see Documentation/arm/Booting */
|
||||
if (fw_arg0 == 0 && fw_arg1 == 0xffffffff)
|
||||
dtb = phys_to_virt(fw_arg2);
|
||||
|
||||
__dt_setup_arch(dtb);
|
||||
|
||||
strlcpy(arcs_cmdline, boot_command_line, COMMAND_LINE_SIZE);
|
||||
}
|
||||
|
||||
void __init device_tree_init(void)
|
||||
{
|
||||
struct device_node *np;
|
||||
|
||||
unflatten_and_copy_device_tree();
|
||||
|
||||
/* Disable SMP boot unless both CPUs are listed in DT and !disabled */
|
||||
np = of_find_node_by_name(NULL, "cpus");
|
||||
if (np && of_get_available_child_count(np) <= 1)
|
||||
bmips_smp_enabled = 0;
|
||||
of_node_put(np);
|
||||
}
|
||||
|
||||
int __init plat_of_setup(void)
|
||||
{
|
||||
return __dt_register_buses("brcm,bcm3384", "simple-bus");
|
||||
}
|
||||
|
||||
arch_initcall(plat_of_setup);
|
||||
|
||||
static int __init plat_dev_init(void)
|
||||
{
|
||||
of_clk_init(NULL);
|
||||
return 0;
|
||||
}
|
||||
|
||||
device_initcall(plat_dev_init);
|
||||
|
|
@ -1,6 +1,10 @@
|
|||
#ifndef LINUX_BCM47XX_PRIVATE_H_
|
||||
#define LINUX_BCM47XX_PRIVATE_H_
|
||||
|
||||
#ifndef pr_fmt
|
||||
#define pr_fmt(fmt) "bcm47xx: " fmt
|
||||
#endif
|
||||
|
||||
#include <linux/kernel.h>
|
||||
|
||||
/* prom.c */
|
||||
|
|
|
|||
|
|
@ -1,8 +1,8 @@
|
|||
#include <linux/errno.h>
|
||||
#include <linux/export.h>
|
||||
#include <linux/string.h>
|
||||
#include <bcm47xx.h>
|
||||
#include <bcm47xx_board.h>
|
||||
#include <bcm47xx_nvram.h>
|
||||
|
||||
struct bcm47xx_board_type {
|
||||
const enum bcm47xx_board board;
|
||||
|
|
@ -40,20 +40,6 @@ struct bcm47xx_board_type_list1 bcm47xx_board_list_model_name[] __initconst = {
|
|||
{ {0}, NULL},
|
||||
};
|
||||
|
||||
/* model_no */
|
||||
static const
|
||||
struct bcm47xx_board_type_list1 bcm47xx_board_list_model_no[] __initconst = {
|
||||
{{BCM47XX_BOARD_ASUS_WL700GE, "Asus WL700"}, "WL700"},
|
||||
{ {0}, NULL},
|
||||
};
|
||||
|
||||
/* machine_name */
|
||||
static const
|
||||
struct bcm47xx_board_type_list1 bcm47xx_board_list_machine_name[] __initconst = {
|
||||
{{BCM47XX_BOARD_LINKSYS_WRTSL54GS, "Linksys WRTSL54GS"}, "WRTSL54GS"},
|
||||
{ {0}, NULL},
|
||||
};
|
||||
|
||||
/* hardware_version */
|
||||
static const
|
||||
struct bcm47xx_board_type_list1 bcm47xx_board_list_hardware_version[] __initconst = {
|
||||
|
|
@ -165,9 +151,11 @@ static const
|
|||
struct bcm47xx_board_type_list1 bcm47xx_board_list_board_id[] __initconst = {
|
||||
{{BCM47XX_BOARD_NETGEAR_WGR614V8, "Netgear WGR614 V8"}, "U12H072T00_NETGEAR"},
|
||||
{{BCM47XX_BOARD_NETGEAR_WGR614V9, "Netgear WGR614 V9"}, "U12H094T00_NETGEAR"},
|
||||
{{BCM47XX_BOARD_NETGEAR_WGR614_V10, "Netgear WGR614 V10"}, "U12H139T01_NETGEAR"},
|
||||
{{BCM47XX_BOARD_NETGEAR_WNDR3300, "Netgear WNDR3300"}, "U12H093T00_NETGEAR"},
|
||||
{{BCM47XX_BOARD_NETGEAR_WNDR3400V1, "Netgear WNDR3400 V1"}, "U12H155T00_NETGEAR"},
|
||||
{{BCM47XX_BOARD_NETGEAR_WNDR3400V2, "Netgear WNDR3400 V2"}, "U12H187T00_NETGEAR"},
|
||||
{{BCM47XX_BOARD_NETGEAR_WNDR3400_V3, "Netgear WNDR3400 V3"}, "U12H208T00_NETGEAR"},
|
||||
{{BCM47XX_BOARD_NETGEAR_WNDR3400VCNA, "Netgear WNDR3400 Vcna"}, "U12H155T01_NETGEAR"},
|
||||
{{BCM47XX_BOARD_NETGEAR_WNDR3700V3, "Netgear WNDR3700 V3"}, "U12H194T00_NETGEAR"},
|
||||
{{BCM47XX_BOARD_NETGEAR_WNDR4000, "Netgear WNDR4000"}, "U12H181T00_NETGEAR"},
|
||||
|
|
@ -202,6 +190,20 @@ struct bcm47xx_board_type_list2 bcm47xx_board_list_board_type_rev[] __initconst
|
|||
{ {0}, NULL},
|
||||
};
|
||||
|
||||
/*
|
||||
* Some devices don't use any common NVRAM entry for identification and they
|
||||
* have only one model specific variable.
|
||||
* They don't deserve own arrays, let's group them there using key-value array.
|
||||
*/
|
||||
static const
|
||||
struct bcm47xx_board_type_list2 bcm47xx_board_list_key_value[] __initconst = {
|
||||
{{BCM47XX_BOARD_ASUS_WL700GE, "Asus WL700"}, "model_no", "WL700"},
|
||||
{{BCM47XX_BOARD_LINKSYS_WRT300N_V1, "Linksys WRT300N V1"}, "router_name", "WRT300N"},
|
||||
{{BCM47XX_BOARD_LINKSYS_WRT600N_V11, "Linksys WRT600N V1.1"}, "Model_Name", "WRT600N"},
|
||||
{{BCM47XX_BOARD_LINKSYS_WRTSL54GS, "Linksys WRTSL54GS"}, "machine_name", "WRTSL54GS"},
|
||||
{ {0}, NULL},
|
||||
};
|
||||
|
||||
static const
|
||||
struct bcm47xx_board_type bcm47xx_board_unknown[] __initconst = {
|
||||
{BCM47XX_BOARD_UNKNOWN, "Unknown Board"},
|
||||
|
|
@ -225,20 +227,6 @@ static __init const struct bcm47xx_board_type *bcm47xx_board_get_nvram(void)
|
|||
}
|
||||
}
|
||||
|
||||
if (bcm47xx_nvram_getenv("model_no", buf1, sizeof(buf1)) >= 0) {
|
||||
for (e1 = bcm47xx_board_list_model_no; e1->value1; e1++) {
|
||||
if (strstarts(buf1, e1->value1))
|
||||
return &e1->board;
|
||||
}
|
||||
}
|
||||
|
||||
if (bcm47xx_nvram_getenv("machine_name", buf1, sizeof(buf1)) >= 0) {
|
||||
for (e1 = bcm47xx_board_list_machine_name; e1->value1; e1++) {
|
||||
if (strstarts(buf1, e1->value1))
|
||||
return &e1->board;
|
||||
}
|
||||
}
|
||||
|
||||
if (bcm47xx_nvram_getenv("hardware_version", buf1, sizeof(buf1)) >= 0) {
|
||||
for (e1 = bcm47xx_board_list_hardware_version; e1->value1; e1++) {
|
||||
if (strstarts(buf1, e1->value1))
|
||||
|
|
@ -247,8 +235,8 @@ static __init const struct bcm47xx_board_type *bcm47xx_board_get_nvram(void)
|
|||
}
|
||||
|
||||
if (bcm47xx_nvram_getenv("hardware_version", buf1, sizeof(buf1)) >= 0 &&
|
||||
bcm47xx_nvram_getenv("boardtype", buf2, sizeof(buf2)) >= 0) {
|
||||
for (e2 = bcm47xx_board_list_boot_hw; e2->value1; e2++) {
|
||||
bcm47xx_nvram_getenv("boardnum", buf2, sizeof(buf2)) >= 0) {
|
||||
for (e2 = bcm47xx_board_list_hw_version_num; e2->value1; e2++) {
|
||||
if (!strstarts(buf1, e2->value1) &&
|
||||
!strcmp(buf2, e2->value2))
|
||||
return &e2->board;
|
||||
|
|
@ -314,6 +302,14 @@ static __init const struct bcm47xx_board_type *bcm47xx_board_get_nvram(void)
|
|||
return &e2->board;
|
||||
}
|
||||
}
|
||||
|
||||
for (e2 = bcm47xx_board_list_key_value; e2->value1; e2++) {
|
||||
if (bcm47xx_nvram_getenv(e2->value1, buf1, sizeof(buf1)) >= 0) {
|
||||
if (!strcmp(buf1, e2->value2))
|
||||
return &e2->board;
|
||||
}
|
||||
}
|
||||
|
||||
return bcm47xx_board_unknown;
|
||||
}
|
||||
|
||||
|
|
@ -330,9 +326,8 @@ void __init bcm47xx_board_detect(void)
|
|||
err = bcm47xx_nvram_getenv("boardtype", buf, sizeof(buf));
|
||||
|
||||
/* init of nvram failed, probably too early now */
|
||||
if (err == -ENXIO) {
|
||||
if (err == -ENXIO)
|
||||
return;
|
||||
}
|
||||
|
||||
board_detected = bcm47xx_board_get_nvram();
|
||||
bcm47xx_board.board = board_detected->board;
|
||||
|
|
|
|||
|
|
@ -251,6 +251,12 @@ bcm47xx_buttons_linksys_wrt160nv3[] __initconst = {
|
|||
BCM47XX_GPIO_KEY(6, KEY_RESTART),
|
||||
};
|
||||
|
||||
static const struct gpio_keys_button
|
||||
bcm47xx_buttons_linksys_wrt300n_v1[] __initconst = {
|
||||
BCM47XX_GPIO_KEY(4, KEY_WPS_BUTTON),
|
||||
BCM47XX_GPIO_KEY(6, KEY_RESTART),
|
||||
};
|
||||
|
||||
static const struct gpio_keys_button
|
||||
bcm47xx_buttons_linksys_wrt300nv11[] __initconst = {
|
||||
BCM47XX_GPIO_KEY(4, KEY_UNKNOWN),
|
||||
|
|
@ -326,6 +332,12 @@ bcm47xx_buttons_netgear_wndr3400v1[] __initconst = {
|
|||
BCM47XX_GPIO_KEY(8, KEY_RFKILL),
|
||||
};
|
||||
|
||||
static const struct gpio_keys_button
|
||||
bcm47xx_buttons_netgear_wndr3400_v3[] __initconst = {
|
||||
BCM47XX_GPIO_KEY(12, KEY_RESTART),
|
||||
BCM47XX_GPIO_KEY(23, KEY_WPS_BUTTON),
|
||||
};
|
||||
|
||||
static const struct gpio_keys_button
|
||||
bcm47xx_buttons_netgear_wndr3700v3[] __initconst = {
|
||||
BCM47XX_GPIO_KEY(2, KEY_RFKILL),
|
||||
|
|
@ -516,6 +528,9 @@ int __init bcm47xx_buttons_register(void)
|
|||
case BCM47XX_BOARD_LINKSYS_WRT160NV3:
|
||||
err = bcm47xx_copy_bdata(bcm47xx_buttons_linksys_wrt160nv3);
|
||||
break;
|
||||
case BCM47XX_BOARD_LINKSYS_WRT300N_V1:
|
||||
err = bcm47xx_copy_bdata(bcm47xx_buttons_linksys_wrt300n_v1);
|
||||
break;
|
||||
case BCM47XX_BOARD_LINKSYS_WRT300NV11:
|
||||
err = bcm47xx_copy_bdata(bcm47xx_buttons_linksys_wrt300nv11);
|
||||
break;
|
||||
|
|
@ -557,6 +572,9 @@ int __init bcm47xx_buttons_register(void)
|
|||
case BCM47XX_BOARD_NETGEAR_WNDR3400V1:
|
||||
err = bcm47xx_copy_bdata(bcm47xx_buttons_netgear_wndr3400v1);
|
||||
break;
|
||||
case BCM47XX_BOARD_NETGEAR_WNDR3400_V3:
|
||||
err = bcm47xx_copy_bdata(bcm47xx_buttons_netgear_wndr3400_v3);
|
||||
break;
|
||||
case BCM47XX_BOARD_NETGEAR_WNDR3700V3:
|
||||
err = bcm47xx_copy_bdata(bcm47xx_buttons_netgear_wndr3700v3);
|
||||
break;
|
||||
|
|
|
|||
|
|
@ -291,6 +291,13 @@ bcm47xx_leds_linksys_wrt160nv3[] __initconst = {
|
|||
BCM47XX_GPIO_LED(4, "blue", "wps", 1, LEDS_GPIO_DEFSTATE_OFF),
|
||||
};
|
||||
|
||||
static const struct gpio_led
|
||||
bcm47xx_leds_linksys_wrt300n_v1[] __initconst = {
|
||||
BCM47XX_GPIO_LED(1, "green", "power", 0, LEDS_GPIO_DEFSTATE_ON),
|
||||
BCM47XX_GPIO_LED(3, "amber", "wps", 1, LEDS_GPIO_DEFSTATE_OFF),
|
||||
BCM47XX_GPIO_LED(5, "green", "wps", 1, LEDS_GPIO_DEFSTATE_OFF),
|
||||
};
|
||||
|
||||
static const struct gpio_led
|
||||
bcm47xx_leds_linksys_wrt300nv11[] __initconst = {
|
||||
BCM47XX_GPIO_LED(1, "unk", "power", 0, LEDS_GPIO_DEFSTATE_ON),
|
||||
|
|
@ -585,6 +592,9 @@ void __init bcm47xx_leds_register(void)
|
|||
case BCM47XX_BOARD_LINKSYS_WRT160NV3:
|
||||
bcm47xx_set_pdata(bcm47xx_leds_linksys_wrt160nv3);
|
||||
break;
|
||||
case BCM47XX_BOARD_LINKSYS_WRT300N_V1:
|
||||
bcm47xx_set_pdata(bcm47xx_leds_linksys_wrt300n_v1);
|
||||
break;
|
||||
case BCM47XX_BOARD_LINKSYS_WRT300NV11:
|
||||
bcm47xx_set_pdata(bcm47xx_leds_linksys_wrt300nv11);
|
||||
break;
|
||||
|
|
|
|||
|
|
@ -11,15 +11,18 @@
|
|||
* option) any later version.
|
||||
*/
|
||||
|
||||
#include <linux/io.h>
|
||||
#include <linux/types.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/string.h>
|
||||
#include <linux/mtd/mtd.h>
|
||||
#include <bcm47xx_nvram.h>
|
||||
#include <linux/bcm47xx_nvram.h>
|
||||
|
||||
#define NVRAM_MAGIC 0x48534C46 /* 'FLSH' */
|
||||
#define NVRAM_SPACE 0x8000
|
||||
#define NVRAM_MAGIC 0x48534C46 /* 'FLSH' */
|
||||
#define NVRAM_SPACE 0x10000
|
||||
#define NVRAM_MAX_GPIO_ENTRIES 32
|
||||
#define NVRAM_MAX_GPIO_VALUE_LEN 30
|
||||
|
||||
#define FLASH_MIN 0x00020000 /* Minimum flash size */
|
||||
|
||||
|
|
@ -91,20 +94,18 @@ static int nvram_find_and_copy(void __iomem *iobase, u32 lim)
|
|||
return -ENXIO;
|
||||
|
||||
found:
|
||||
|
||||
if (header->len > size)
|
||||
pr_err("The nvram size accoridng to the header seems to be bigger than the partition on flash\n");
|
||||
if (header->len > NVRAM_SPACE)
|
||||
pr_err("nvram on flash (%i bytes) is bigger than the reserved space in memory, will just copy the first %i bytes\n",
|
||||
header->len, NVRAM_SPACE);
|
||||
|
||||
src = (u32 *) header;
|
||||
dst = (u32 *) nvram_buf;
|
||||
src = (u32 *)header;
|
||||
dst = (u32 *)nvram_buf;
|
||||
for (i = 0; i < sizeof(struct nvram_header); i += 4)
|
||||
*dst++ = *src++;
|
||||
*dst++ = __raw_readl(src++);
|
||||
for (; i < header->len && i < NVRAM_SPACE && i < size; i += 4)
|
||||
*dst++ = le32_to_cpu(*src++);
|
||||
memset(dst, 0x0, NVRAM_SPACE - i);
|
||||
*dst++ = readl(src++);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -138,37 +139,28 @@ static int nvram_init(void)
|
|||
struct mtd_info *mtd;
|
||||
struct nvram_header header;
|
||||
size_t bytes_read;
|
||||
int err, i;
|
||||
int err;
|
||||
|
||||
mtd = get_mtd_device_nm("nvram");
|
||||
if (IS_ERR(mtd))
|
||||
return -ENODEV;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(nvram_sizes); i++) {
|
||||
loff_t from = mtd->size - nvram_sizes[i];
|
||||
err = mtd_read(mtd, 0, sizeof(header), &bytes_read, (uint8_t *)&header);
|
||||
if (!err && header.magic == NVRAM_MAGIC) {
|
||||
u8 *dst = (uint8_t *)nvram_buf;
|
||||
size_t len = header.len;
|
||||
|
||||
if (from < 0)
|
||||
continue;
|
||||
|
||||
err = mtd_read(mtd, from, sizeof(header), &bytes_read,
|
||||
(uint8_t *)&header);
|
||||
if (!err && header.magic == NVRAM_MAGIC) {
|
||||
u8 *dst = (uint8_t *)nvram_buf;
|
||||
size_t len = header.len;
|
||||
|
||||
if (header.len > NVRAM_SPACE) {
|
||||
pr_err("nvram on flash (%i bytes) is bigger than the reserved space in memory, will just copy the first %i bytes\n",
|
||||
header.len, NVRAM_SPACE);
|
||||
len = NVRAM_SPACE;
|
||||
}
|
||||
|
||||
err = mtd_read(mtd, from, len, &bytes_read, dst);
|
||||
if (err)
|
||||
return err;
|
||||
memset(dst + bytes_read, 0x0, NVRAM_SPACE - bytes_read);
|
||||
|
||||
return 0;
|
||||
if (header.len > NVRAM_SPACE) {
|
||||
pr_err("nvram on flash (%i bytes) is bigger than the reserved space in memory, will just copy the first %i bytes\n",
|
||||
header.len, NVRAM_SPACE);
|
||||
len = NVRAM_SPACE;
|
||||
}
|
||||
|
||||
err = mtd_read(mtd, 0, len, &bytes_read, dst);
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
|
|
@ -178,7 +170,7 @@ static int nvram_init(void)
|
|||
int bcm47xx_nvram_getenv(const char *name, char *val, size_t val_len)
|
||||
{
|
||||
char *var, *value, *end, *eq;
|
||||
int err;
|
||||
int data_left, err;
|
||||
|
||||
if (!name)
|
||||
return -EINVAL;
|
||||
|
|
@ -192,16 +184,18 @@ int bcm47xx_nvram_getenv(const char *name, char *val, size_t val_len)
|
|||
/* Look for name=value and return value */
|
||||
var = &nvram_buf[sizeof(struct nvram_header)];
|
||||
end = nvram_buf + sizeof(nvram_buf) - 2;
|
||||
end[0] = end[1] = '\0';
|
||||
end[0] = '\0';
|
||||
end[1] = '\0';
|
||||
for (; *var; var = value + strlen(value) + 1) {
|
||||
eq = strchr(var, '=');
|
||||
data_left = end - var;
|
||||
|
||||
eq = strnchr(var, data_left, '=');
|
||||
if (!eq)
|
||||
break;
|
||||
value = eq + 1;
|
||||
if ((eq - var) == strlen(name) &&
|
||||
strncmp(var, name, (eq - var)) == 0) {
|
||||
if (eq - var == strlen(name) &&
|
||||
strncmp(var, name, eq - var) == 0)
|
||||
return snprintf(val, val_len, "%s", value);
|
||||
}
|
||||
}
|
||||
return -ENOENT;
|
||||
}
|
||||
|
|
@ -210,10 +204,11 @@ EXPORT_SYMBOL(bcm47xx_nvram_getenv);
|
|||
int bcm47xx_nvram_gpio_pin(const char *name)
|
||||
{
|
||||
int i, err;
|
||||
char nvram_var[10];
|
||||
char buf[30];
|
||||
char nvram_var[] = "gpioXX";
|
||||
char buf[NVRAM_MAX_GPIO_VALUE_LEN];
|
||||
|
||||
for (i = 0; i < 32; i++) {
|
||||
/* TODO: Optimize it to don't call getenv so many times */
|
||||
for (i = 0; i < NVRAM_MAX_GPIO_ENTRIES; i++) {
|
||||
err = snprintf(nvram_var, sizeof(nvram_var), "gpio%i", i);
|
||||
if (err <= 0)
|
||||
continue;
|
||||
|
|
|
|||
|
|
@ -35,7 +35,6 @@
|
|||
#include <bcm47xx.h>
|
||||
#include <bcm47xx_board.h>
|
||||
|
||||
|
||||
static char bcm47xx_system_type[20] = "Broadcom BCM47XX";
|
||||
|
||||
const char *get_system_type(void)
|
||||
|
|
@ -83,7 +82,7 @@ static __init void prom_init_mem(void)
|
|||
/* Loop condition may be not enough, off may be over 1 MiB */
|
||||
if (off + mem >= max) {
|
||||
mem = max;
|
||||
printk(KERN_DEBUG "assume 128MB RAM\n");
|
||||
pr_debug("Assume 128MB RAM\n");
|
||||
break;
|
||||
}
|
||||
if (!memcmp(prom_init, prom_init + mem, 32))
|
||||
|
|
|
|||
|
|
@ -36,8 +36,8 @@ static int __init uart8250_init_ssb(void)
|
|||
struct plat_serial8250_port *p = &(uart8250_data[i]);
|
||||
struct ssb_serial_port *ssb_port = &(mcore->serial_ports[i]);
|
||||
|
||||
p->mapbase = (unsigned int) ssb_port->regs;
|
||||
p->membase = (void *) ssb_port->regs;
|
||||
p->mapbase = (unsigned int)ssb_port->regs;
|
||||
p->membase = (void *)ssb_port->regs;
|
||||
p->irq = ssb_port->irq + 2;
|
||||
p->uartclk = ssb_port->baud_base;
|
||||
p->regshift = ssb_port->reg_shift;
|
||||
|
|
@ -62,8 +62,8 @@ static int __init uart8250_init_bcma(void)
|
|||
struct bcma_serial_port *bcma_port;
|
||||
bcma_port = &(cc->serial_ports[i]);
|
||||
|
||||
p->mapbase = (unsigned int) bcma_port->regs;
|
||||
p->membase = (void *) bcma_port->regs;
|
||||
p->mapbase = (unsigned int)bcma_port->regs;
|
||||
p->membase = (void *)bcma_port->regs;
|
||||
p->irq = bcma_port->irq;
|
||||
p->uartclk = bcma_port->baud_base;
|
||||
p->regshift = bcma_port->reg_shift;
|
||||
|
|
|
|||
|
|
@ -42,7 +42,6 @@
|
|||
#include <asm/reboot.h>
|
||||
#include <asm/time.h>
|
||||
#include <bcm47xx.h>
|
||||
#include <bcm47xx_nvram.h>
|
||||
#include <bcm47xx_board.h>
|
||||
|
||||
union bcm47xx_bus bcm47xx_bus;
|
||||
|
|
@ -53,7 +52,7 @@ EXPORT_SYMBOL(bcm47xx_bus_type);
|
|||
|
||||
static void bcm47xx_machine_restart(char *command)
|
||||
{
|
||||
printk(KERN_ALERT "Please stand by while rebooting the system...\n");
|
||||
pr_alert("Please stand by while rebooting the system...\n");
|
||||
local_irq_disable();
|
||||
/* Set the watchdog timer to reset immediately */
|
||||
switch (bcm47xx_bus_type) {
|
||||
|
|
@ -108,7 +107,7 @@ static int bcm47xx_get_invariants(struct ssb_bus *bus,
|
|||
char buf[20];
|
||||
|
||||
/* Fill boardinfo structure */
|
||||
memset(&(iv->boardinfo), 0 , sizeof(struct ssb_boardinfo));
|
||||
memset(&iv->boardinfo, 0 , sizeof(struct ssb_boardinfo));
|
||||
|
||||
bcm47xx_fill_ssb_boardinfo(&iv->boardinfo, NULL);
|
||||
|
||||
|
|
@ -127,7 +126,7 @@ static void __init bcm47xx_register_ssb(void)
|
|||
char buf[100];
|
||||
struct ssb_mipscore *mcore;
|
||||
|
||||
err = ssb_bus_ssbbus_register(&(bcm47xx_bus.ssb), SSB_ENUM_BASE,
|
||||
err = ssb_bus_ssbbus_register(&bcm47xx_bus.ssb, SSB_ENUM_BASE,
|
||||
bcm47xx_get_invariants);
|
||||
if (err)
|
||||
panic("Failed to initialize SSB bus (err %d)", err);
|
||||
|
|
@ -137,7 +136,7 @@ static void __init bcm47xx_register_ssb(void)
|
|||
if (strstr(buf, "console=ttyS1")) {
|
||||
struct ssb_serial_port port;
|
||||
|
||||
printk(KERN_DEBUG "Swapping serial ports!\n");
|
||||
pr_debug("Swapping serial ports!\n");
|
||||
/* swap serial ports */
|
||||
memcpy(&port, &mcore->serial_ports[0], sizeof(port));
|
||||
memcpy(&mcore->serial_ports[0], &mcore->serial_ports[1],
|
||||
|
|
@ -169,7 +168,7 @@ void __init plat_mem_setup(void)
|
|||
struct cpuinfo_mips *c = ¤t_cpu_data;
|
||||
|
||||
if ((c->cputype == CPU_74K) || (c->cputype == CPU_1074K)) {
|
||||
printk(KERN_INFO "bcm47xx: using bcma bus\n");
|
||||
pr_info("Using bcma bus\n");
|
||||
#ifdef CONFIG_BCM47XX_BCMA
|
||||
bcm47xx_bus_type = BCM47XX_BUS_TYPE_BCMA;
|
||||
bcm47xx_sprom_register_fallbacks();
|
||||
|
|
@ -180,7 +179,7 @@ void __init plat_mem_setup(void)
|
|||
#endif
|
||||
#endif
|
||||
} else {
|
||||
printk(KERN_INFO "bcm47xx: using ssb bus\n");
|
||||
pr_info("Using ssb bus\n");
|
||||
#ifdef CONFIG_BCM47XX_SSB
|
||||
bcm47xx_bus_type = BCM47XX_BUS_TYPE_SSB;
|
||||
bcm47xx_sprom_register_fallbacks();
|
||||
|
|
|
|||
|
|
@ -27,7 +27,6 @@
|
|||
*/
|
||||
|
||||
#include <bcm47xx.h>
|
||||
#include <bcm47xx_nvram.h>
|
||||
#include <linux/if_ether.h>
|
||||
#include <linux/etherdevice.h>
|
||||
|
||||
|
|
@ -181,94 +180,245 @@ static void nvram_read_alpha2(const char *prefix, const char *name,
|
|||
memcpy(val, buf, 2);
|
||||
}
|
||||
|
||||
/* This is one-function-only macro, it uses local "sprom" variable! */
|
||||
#define ENTRY(_revmask, _type, _prefix, _name, _val, _allset, _fallback) \
|
||||
if (_revmask & BIT(sprom->revision)) \
|
||||
nvram_read_ ## _type(_prefix, NULL, _name, &sprom->_val, \
|
||||
_allset, _fallback)
|
||||
/*
|
||||
* Special version of filling function that can be safely called for any SPROM
|
||||
* revision. For every NVRAM to SPROM mapping it contains bitmask of revisions
|
||||
* for which the mapping is valid.
|
||||
* It obviously requires some hexadecimal/bitmasks knowledge, but allows
|
||||
* writing cleaner code (easy revisions handling).
|
||||
* Note that while SPROM revision 0 was never used, we still keep BIT(0)
|
||||
* reserved for it, just to keep numbering sane.
|
||||
*/
|
||||
static void bcm47xx_sprom_fill_auto(struct ssb_sprom *sprom,
|
||||
const char *prefix, bool fallback)
|
||||
{
|
||||
const char *pre = prefix;
|
||||
bool fb = fallback;
|
||||
|
||||
ENTRY(0xfffffffe, u16, pre, "boardrev", board_rev, 0, true);
|
||||
ENTRY(0x00000002, u16, pre, "boardflags", boardflags_lo, 0, fb);
|
||||
ENTRY(0xfffffffc, u16, pre, "boardtype", board_type, 0, true);
|
||||
ENTRY(0xfffffffe, u16, pre, "boardnum", board_num, 0, fb);
|
||||
ENTRY(0x00000002, u8, pre, "cc", country_code, 0, fb);
|
||||
ENTRY(0xfffffff8, u8, pre, "regrev", regrev, 0, fb);
|
||||
|
||||
ENTRY(0xfffffffe, u8, pre, "ledbh0", gpio0, 0xff, fb);
|
||||
ENTRY(0xfffffffe, u8, pre, "ledbh1", gpio1, 0xff, fb);
|
||||
ENTRY(0xfffffffe, u8, pre, "ledbh2", gpio2, 0xff, fb);
|
||||
ENTRY(0xfffffffe, u8, pre, "ledbh3", gpio3, 0xff, fb);
|
||||
|
||||
ENTRY(0x0000070e, u16, pre, "pa0b0", pa0b0, 0, fb);
|
||||
ENTRY(0x0000070e, u16, pre, "pa0b1", pa0b1, 0, fb);
|
||||
ENTRY(0x0000070e, u16, pre, "pa0b2", pa0b2, 0, fb);
|
||||
ENTRY(0x0000070e, u8, pre, "pa0itssit", itssi_bg, 0, fb);
|
||||
ENTRY(0x0000070e, u8, pre, "pa0maxpwr", maxpwr_bg, 0, fb);
|
||||
|
||||
ENTRY(0x0000070c, u8, pre, "opo", opo, 0, fb);
|
||||
ENTRY(0xfffffffe, u8, pre, "aa2g", ant_available_bg, 0, fb);
|
||||
ENTRY(0xfffffffe, u8, pre, "aa5g", ant_available_a, 0, fb);
|
||||
ENTRY(0x000007fe, s8, pre, "ag0", antenna_gain.a0, 0, fb);
|
||||
ENTRY(0x000007fe, s8, pre, "ag1", antenna_gain.a1, 0, fb);
|
||||
ENTRY(0x000007f0, s8, pre, "ag2", antenna_gain.a2, 0, fb);
|
||||
ENTRY(0x000007f0, s8, pre, "ag3", antenna_gain.a3, 0, fb);
|
||||
|
||||
ENTRY(0x0000070e, u16, pre, "pa1b0", pa1b0, 0, fb);
|
||||
ENTRY(0x0000070e, u16, pre, "pa1b1", pa1b1, 0, fb);
|
||||
ENTRY(0x0000070e, u16, pre, "pa1b2", pa1b2, 0, fb);
|
||||
ENTRY(0x0000070c, u16, pre, "pa1lob0", pa1lob0, 0, fb);
|
||||
ENTRY(0x0000070c, u16, pre, "pa1lob1", pa1lob1, 0, fb);
|
||||
ENTRY(0x0000070c, u16, pre, "pa1lob2", pa1lob2, 0, fb);
|
||||
ENTRY(0x0000070c, u16, pre, "pa1hib0", pa1hib0, 0, fb);
|
||||
ENTRY(0x0000070c, u16, pre, "pa1hib1", pa1hib1, 0, fb);
|
||||
ENTRY(0x0000070c, u16, pre, "pa1hib2", pa1hib2, 0, fb);
|
||||
ENTRY(0x0000070e, u8, pre, "pa1itssit", itssi_a, 0, fb);
|
||||
ENTRY(0x0000070e, u8, pre, "pa1maxpwr", maxpwr_a, 0, fb);
|
||||
ENTRY(0x0000070c, u8, pre, "pa1lomaxpwr", maxpwr_al, 0, fb);
|
||||
ENTRY(0x0000070c, u8, pre, "pa1himaxpwr", maxpwr_ah, 0, fb);
|
||||
|
||||
ENTRY(0x00000708, u8, pre, "bxa2g", bxa2g, 0, fb);
|
||||
ENTRY(0x00000708, u8, pre, "rssisav2g", rssisav2g, 0, fb);
|
||||
ENTRY(0x00000708, u8, pre, "rssismc2g", rssismc2g, 0, fb);
|
||||
ENTRY(0x00000708, u8, pre, "rssismf2g", rssismf2g, 0, fb);
|
||||
ENTRY(0x00000708, u8, pre, "bxa5g", bxa5g, 0, fb);
|
||||
ENTRY(0x00000708, u8, pre, "rssisav5g", rssisav5g, 0, fb);
|
||||
ENTRY(0x00000708, u8, pre, "rssismc5g", rssismc5g, 0, fb);
|
||||
ENTRY(0x00000708, u8, pre, "rssismf5g", rssismf5g, 0, fb);
|
||||
ENTRY(0x00000708, u8, pre, "tri2g", tri2g, 0, fb);
|
||||
ENTRY(0x00000708, u8, pre, "tri5g", tri5g, 0, fb);
|
||||
ENTRY(0x00000708, u8, pre, "tri5gl", tri5gl, 0, fb);
|
||||
ENTRY(0x00000708, u8, pre, "tri5gh", tri5gh, 0, fb);
|
||||
ENTRY(0x00000708, s8, pre, "rxpo2g", rxpo2g, 0, fb);
|
||||
ENTRY(0x00000708, s8, pre, "rxpo5g", rxpo5g, 0, fb);
|
||||
ENTRY(0xfffffff0, u8, pre, "txchain", txchain, 0xf, fb);
|
||||
ENTRY(0xfffffff0, u8, pre, "rxchain", rxchain, 0xf, fb);
|
||||
ENTRY(0xfffffff0, u8, pre, "antswitch", antswitch, 0xff, fb);
|
||||
ENTRY(0x00000700, u8, pre, "tssipos2g", fem.ghz2.tssipos, 0, fb);
|
||||
ENTRY(0x00000700, u8, pre, "extpagain2g", fem.ghz2.extpa_gain, 0, fb);
|
||||
ENTRY(0x00000700, u8, pre, "pdetrange2g", fem.ghz2.pdet_range, 0, fb);
|
||||
ENTRY(0x00000700, u8, pre, "triso2g", fem.ghz2.tr_iso, 0, fb);
|
||||
ENTRY(0x00000700, u8, pre, "antswctl2g", fem.ghz2.antswlut, 0, fb);
|
||||
ENTRY(0x00000700, u8, pre, "tssipos5g", fem.ghz5.tssipos, 0, fb);
|
||||
ENTRY(0x00000700, u8, pre, "extpagain5g", fem.ghz5.extpa_gain, 0, fb);
|
||||
ENTRY(0x00000700, u8, pre, "pdetrange5g", fem.ghz5.pdet_range, 0, fb);
|
||||
ENTRY(0x00000700, u8, pre, "triso5g", fem.ghz5.tr_iso, 0, fb);
|
||||
ENTRY(0x00000700, u8, pre, "antswctl5g", fem.ghz5.antswlut, 0, fb);
|
||||
ENTRY(0x000000f0, u8, pre, "txpid2ga0", txpid2g[0], 0, fb);
|
||||
ENTRY(0x000000f0, u8, pre, "txpid2ga1", txpid2g[1], 0, fb);
|
||||
ENTRY(0x000000f0, u8, pre, "txpid2ga2", txpid2g[2], 0, fb);
|
||||
ENTRY(0x000000f0, u8, pre, "txpid2ga3", txpid2g[3], 0, fb);
|
||||
ENTRY(0x000000f0, u8, pre, "txpid5ga0", txpid5g[0], 0, fb);
|
||||
ENTRY(0x000000f0, u8, pre, "txpid5ga1", txpid5g[1], 0, fb);
|
||||
ENTRY(0x000000f0, u8, pre, "txpid5ga2", txpid5g[2], 0, fb);
|
||||
ENTRY(0x000000f0, u8, pre, "txpid5ga3", txpid5g[3], 0, fb);
|
||||
ENTRY(0x000000f0, u8, pre, "txpid5gla0", txpid5gl[0], 0, fb);
|
||||
ENTRY(0x000000f0, u8, pre, "txpid5gla1", txpid5gl[1], 0, fb);
|
||||
ENTRY(0x000000f0, u8, pre, "txpid5gla2", txpid5gl[2], 0, fb);
|
||||
ENTRY(0x000000f0, u8, pre, "txpid5gla3", txpid5gl[3], 0, fb);
|
||||
ENTRY(0x000000f0, u8, pre, "txpid5gha0", txpid5gh[0], 0, fb);
|
||||
ENTRY(0x000000f0, u8, pre, "txpid5gha1", txpid5gh[1], 0, fb);
|
||||
ENTRY(0x000000f0, u8, pre, "txpid5gha2", txpid5gh[2], 0, fb);
|
||||
ENTRY(0x000000f0, u8, pre, "txpid5gha3", txpid5gh[3], 0, fb);
|
||||
|
||||
ENTRY(0xffffff00, u8, pre, "tempthresh", tempthresh, 0, fb);
|
||||
ENTRY(0xffffff00, u8, pre, "tempoffset", tempoffset, 0, fb);
|
||||
ENTRY(0xffffff00, u16, pre, "rawtempsense", rawtempsense, 0, fb);
|
||||
ENTRY(0xffffff00, u8, pre, "measpower", measpower, 0, fb);
|
||||
ENTRY(0xffffff00, u8, pre, "tempsense_slope", tempsense_slope, 0, fb);
|
||||
ENTRY(0xffffff00, u8, pre, "tempcorrx", tempcorrx, 0, fb);
|
||||
ENTRY(0xffffff00, u8, pre, "tempsense_option", tempsense_option, 0, fb);
|
||||
ENTRY(0x00000700, u8, pre, "freqoffset_corr", freqoffset_corr, 0, fb);
|
||||
ENTRY(0x00000700, u8, pre, "iqcal_swp_dis", iqcal_swp_dis, 0, fb);
|
||||
ENTRY(0x00000700, u8, pre, "hw_iqcal_en", hw_iqcal_en, 0, fb);
|
||||
ENTRY(0x00000700, u8, pre, "elna2g", elna2g, 0, fb);
|
||||
ENTRY(0x00000700, u8, pre, "elna5g", elna5g, 0, fb);
|
||||
ENTRY(0xffffff00, u8, pre, "phycal_tempdelta", phycal_tempdelta, 0, fb);
|
||||
ENTRY(0xffffff00, u8, pre, "temps_period", temps_period, 0, fb);
|
||||
ENTRY(0xffffff00, u8, pre, "temps_hysteresis", temps_hysteresis, 0, fb);
|
||||
ENTRY(0xffffff00, u8, pre, "measpower1", measpower1, 0, fb);
|
||||
ENTRY(0xffffff00, u8, pre, "measpower2", measpower2, 0, fb);
|
||||
|
||||
ENTRY(0x000001f0, u16, pre, "cck2gpo", cck2gpo, 0, fb);
|
||||
ENTRY(0x000001f0, u32, pre, "ofdm2gpo", ofdm2gpo, 0, fb);
|
||||
ENTRY(0x000001f0, u32, pre, "ofdm5gpo", ofdm5gpo, 0, fb);
|
||||
ENTRY(0x000001f0, u32, pre, "ofdm5glpo", ofdm5glpo, 0, fb);
|
||||
ENTRY(0x000001f0, u32, pre, "ofdm5ghpo", ofdm5ghpo, 0, fb);
|
||||
ENTRY(0x000001f0, u16, pre, "mcs2gpo0", mcs2gpo[0], 0, fb);
|
||||
ENTRY(0x000001f0, u16, pre, "mcs2gpo1", mcs2gpo[1], 0, fb);
|
||||
ENTRY(0x000001f0, u16, pre, "mcs2gpo2", mcs2gpo[2], 0, fb);
|
||||
ENTRY(0x000001f0, u16, pre, "mcs2gpo3", mcs2gpo[3], 0, fb);
|
||||
ENTRY(0x000001f0, u16, pre, "mcs2gpo4", mcs2gpo[4], 0, fb);
|
||||
ENTRY(0x000001f0, u16, pre, "mcs2gpo5", mcs2gpo[5], 0, fb);
|
||||
ENTRY(0x000001f0, u16, pre, "mcs2gpo6", mcs2gpo[6], 0, fb);
|
||||
ENTRY(0x000001f0, u16, pre, "mcs2gpo7", mcs2gpo[7], 0, fb);
|
||||
ENTRY(0x000001f0, u16, pre, "mcs5gpo0", mcs5gpo[0], 0, fb);
|
||||
ENTRY(0x000001f0, u16, pre, "mcs5gpo1", mcs5gpo[1], 0, fb);
|
||||
ENTRY(0x000001f0, u16, pre, "mcs5gpo2", mcs5gpo[2], 0, fb);
|
||||
ENTRY(0x000001f0, u16, pre, "mcs5gpo3", mcs5gpo[3], 0, fb);
|
||||
ENTRY(0x000001f0, u16, pre, "mcs5gpo4", mcs5gpo[4], 0, fb);
|
||||
ENTRY(0x000001f0, u16, pre, "mcs5gpo5", mcs5gpo[5], 0, fb);
|
||||
ENTRY(0x000001f0, u16, pre, "mcs5gpo6", mcs5gpo[6], 0, fb);
|
||||
ENTRY(0x000001f0, u16, pre, "mcs5gpo7", mcs5gpo[7], 0, fb);
|
||||
ENTRY(0x000001f0, u16, pre, "mcs5glpo0", mcs5glpo[0], 0, fb);
|
||||
ENTRY(0x000001f0, u16, pre, "mcs5glpo1", mcs5glpo[1], 0, fb);
|
||||
ENTRY(0x000001f0, u16, pre, "mcs5glpo2", mcs5glpo[2], 0, fb);
|
||||
ENTRY(0x000001f0, u16, pre, "mcs5glpo3", mcs5glpo[3], 0, fb);
|
||||
ENTRY(0x000001f0, u16, pre, "mcs5glpo4", mcs5glpo[4], 0, fb);
|
||||
ENTRY(0x000001f0, u16, pre, "mcs5glpo5", mcs5glpo[5], 0, fb);
|
||||
ENTRY(0x000001f0, u16, pre, "mcs5glpo6", mcs5glpo[6], 0, fb);
|
||||
ENTRY(0x000001f0, u16, pre, "mcs5glpo7", mcs5glpo[7], 0, fb);
|
||||
ENTRY(0x000001f0, u16, pre, "mcs5ghpo0", mcs5ghpo[0], 0, fb);
|
||||
ENTRY(0x000001f0, u16, pre, "mcs5ghpo1", mcs5ghpo[1], 0, fb);
|
||||
ENTRY(0x000001f0, u16, pre, "mcs5ghpo2", mcs5ghpo[2], 0, fb);
|
||||
ENTRY(0x000001f0, u16, pre, "mcs5ghpo3", mcs5ghpo[3], 0, fb);
|
||||
ENTRY(0x000001f0, u16, pre, "mcs5ghpo4", mcs5ghpo[4], 0, fb);
|
||||
ENTRY(0x000001f0, u16, pre, "mcs5ghpo5", mcs5ghpo[5], 0, fb);
|
||||
ENTRY(0x000001f0, u16, pre, "mcs5ghpo6", mcs5ghpo[6], 0, fb);
|
||||
ENTRY(0x000001f0, u16, pre, "mcs5ghpo7", mcs5ghpo[7], 0, fb);
|
||||
ENTRY(0x000001f0, u16, pre, "cddpo", cddpo, 0, fb);
|
||||
ENTRY(0x000001f0, u16, pre, "stbcpo", stbcpo, 0, fb);
|
||||
ENTRY(0x000001f0, u16, pre, "bw40po", bw40po, 0, fb);
|
||||
ENTRY(0x000001f0, u16, pre, "bwduppo", bwduppo, 0, fb);
|
||||
|
||||
ENTRY(0xfffffe00, u16, pre, "cckbw202gpo", cckbw202gpo, 0, fb);
|
||||
ENTRY(0xfffffe00, u16, pre, "cckbw20ul2gpo", cckbw20ul2gpo, 0, fb);
|
||||
ENTRY(0x00000600, u32, pre, "legofdmbw202gpo", legofdmbw202gpo, 0, fb);
|
||||
ENTRY(0x00000600, u32, pre, "legofdmbw20ul2gpo", legofdmbw20ul2gpo, 0, fb);
|
||||
ENTRY(0x00000600, u32, pre, "legofdmbw205glpo", legofdmbw205glpo, 0, fb);
|
||||
ENTRY(0x00000600, u32, pre, "legofdmbw20ul5glpo", legofdmbw20ul5glpo, 0, fb);
|
||||
ENTRY(0x00000600, u32, pre, "legofdmbw205gmpo", legofdmbw205gmpo, 0, fb);
|
||||
ENTRY(0x00000600, u32, pre, "legofdmbw20ul5gmpo", legofdmbw20ul5gmpo, 0, fb);
|
||||
ENTRY(0x00000600, u32, pre, "legofdmbw205ghpo", legofdmbw205ghpo, 0, fb);
|
||||
ENTRY(0x00000600, u32, pre, "legofdmbw20ul5ghpo", legofdmbw20ul5ghpo, 0, fb);
|
||||
ENTRY(0xfffffe00, u32, pre, "mcsbw202gpo", mcsbw202gpo, 0, fb);
|
||||
ENTRY(0x00000600, u32, pre, "mcsbw20ul2gpo", mcsbw20ul2gpo, 0, fb);
|
||||
ENTRY(0xfffffe00, u32, pre, "mcsbw402gpo", mcsbw402gpo, 0, fb);
|
||||
ENTRY(0xfffffe00, u32, pre, "mcsbw205glpo", mcsbw205glpo, 0, fb);
|
||||
ENTRY(0x00000600, u32, pre, "mcsbw20ul5glpo", mcsbw20ul5glpo, 0, fb);
|
||||
ENTRY(0xfffffe00, u32, pre, "mcsbw405glpo", mcsbw405glpo, 0, fb);
|
||||
ENTRY(0xfffffe00, u32, pre, "mcsbw205gmpo", mcsbw205gmpo, 0, fb);
|
||||
ENTRY(0x00000600, u32, pre, "mcsbw20ul5gmpo", mcsbw20ul5gmpo, 0, fb);
|
||||
ENTRY(0xfffffe00, u32, pre, "mcsbw405gmpo", mcsbw405gmpo, 0, fb);
|
||||
ENTRY(0xfffffe00, u32, pre, "mcsbw205ghpo", mcsbw205ghpo, 0, fb);
|
||||
ENTRY(0x00000600, u32, pre, "mcsbw20ul5ghpo", mcsbw20ul5ghpo, 0, fb);
|
||||
ENTRY(0xfffffe00, u32, pre, "mcsbw405ghpo", mcsbw405ghpo, 0, fb);
|
||||
ENTRY(0x00000600, u16, pre, "mcs32po", mcs32po, 0, fb);
|
||||
ENTRY(0x00000600, u16, pre, "legofdm40duppo", legofdm40duppo, 0, fb);
|
||||
ENTRY(0x00000700, u8, pre, "pcieingress_war", pcieingress_war, 0, fb);
|
||||
|
||||
/* TODO: rev 11 support */
|
||||
ENTRY(0x00000700, u8, pre, "rxgainerr2ga0", rxgainerr2ga[0], 0, fb);
|
||||
ENTRY(0x00000700, u8, pre, "rxgainerr2ga1", rxgainerr2ga[1], 0, fb);
|
||||
ENTRY(0x00000700, u8, pre, "rxgainerr2ga2", rxgainerr2ga[2], 0, fb);
|
||||
ENTRY(0x00000700, u8, pre, "rxgainerr5gla0", rxgainerr5gla[0], 0, fb);
|
||||
ENTRY(0x00000700, u8, pre, "rxgainerr5gla1", rxgainerr5gla[1], 0, fb);
|
||||
ENTRY(0x00000700, u8, pre, "rxgainerr5gla2", rxgainerr5gla[2], 0, fb);
|
||||
ENTRY(0x00000700, u8, pre, "rxgainerr5gma0", rxgainerr5gma[0], 0, fb);
|
||||
ENTRY(0x00000700, u8, pre, "rxgainerr5gma1", rxgainerr5gma[1], 0, fb);
|
||||
ENTRY(0x00000700, u8, pre, "rxgainerr5gma2", rxgainerr5gma[2], 0, fb);
|
||||
ENTRY(0x00000700, u8, pre, "rxgainerr5gha0", rxgainerr5gha[0], 0, fb);
|
||||
ENTRY(0x00000700, u8, pre, "rxgainerr5gha1", rxgainerr5gha[1], 0, fb);
|
||||
ENTRY(0x00000700, u8, pre, "rxgainerr5gha2", rxgainerr5gha[2], 0, fb);
|
||||
ENTRY(0x00000700, u8, pre, "rxgainerr5gua0", rxgainerr5gua[0], 0, fb);
|
||||
ENTRY(0x00000700, u8, pre, "rxgainerr5gua1", rxgainerr5gua[1], 0, fb);
|
||||
ENTRY(0x00000700, u8, pre, "rxgainerr5gua2", rxgainerr5gua[2], 0, fb);
|
||||
|
||||
ENTRY(0xfffffe00, u8, pre, "sar2g", sar2g, 0, fb);
|
||||
ENTRY(0xfffffe00, u8, pre, "sar5g", sar5g, 0, fb);
|
||||
|
||||
/* TODO: rev 11 support */
|
||||
ENTRY(0x00000700, u8, pre, "noiselvl2ga0", noiselvl2ga[0], 0, fb);
|
||||
ENTRY(0x00000700, u8, pre, "noiselvl2ga1", noiselvl2ga[1], 0, fb);
|
||||
ENTRY(0x00000700, u8, pre, "noiselvl2ga2", noiselvl2ga[2], 0, fb);
|
||||
ENTRY(0x00000700, u8, pre, "noiselvl5gla0", noiselvl5gla[0], 0, fb);
|
||||
ENTRY(0x00000700, u8, pre, "noiselvl5gla1", noiselvl5gla[1], 0, fb);
|
||||
ENTRY(0x00000700, u8, pre, "noiselvl5gla2", noiselvl5gla[2], 0, fb);
|
||||
ENTRY(0x00000700, u8, pre, "noiselvl5gma0", noiselvl5gma[0], 0, fb);
|
||||
ENTRY(0x00000700, u8, pre, "noiselvl5gma1", noiselvl5gma[1], 0, fb);
|
||||
ENTRY(0x00000700, u8, pre, "noiselvl5gma2", noiselvl5gma[2], 0, fb);
|
||||
ENTRY(0x00000700, u8, pre, "noiselvl5gha0", noiselvl5gha[0], 0, fb);
|
||||
ENTRY(0x00000700, u8, pre, "noiselvl5gha1", noiselvl5gha[1], 0, fb);
|
||||
ENTRY(0x00000700, u8, pre, "noiselvl5gha2", noiselvl5gha[2], 0, fb);
|
||||
ENTRY(0x00000700, u8, pre, "noiselvl5gua0", noiselvl5gua[0], 0, fb);
|
||||
ENTRY(0x00000700, u8, pre, "noiselvl5gua1", noiselvl5gua[1], 0, fb);
|
||||
ENTRY(0x00000700, u8, pre, "noiselvl5gua2", noiselvl5gua[2], 0, fb);
|
||||
}
|
||||
#undef ENTRY /* It's specififc, uses local variable, don't use it (again). */
|
||||
|
||||
static void bcm47xx_fill_sprom_r1234589(struct ssb_sprom *sprom,
|
||||
const char *prefix, bool fallback)
|
||||
{
|
||||
nvram_read_u16(prefix, NULL, "devid", &sprom->dev_id, 0, fallback);
|
||||
nvram_read_u8(prefix, NULL, "ledbh0", &sprom->gpio0, 0xff, fallback);
|
||||
nvram_read_u8(prefix, NULL, "ledbh1", &sprom->gpio1, 0xff, fallback);
|
||||
nvram_read_u8(prefix, NULL, "ledbh2", &sprom->gpio2, 0xff, fallback);
|
||||
nvram_read_u8(prefix, NULL, "ledbh3", &sprom->gpio3, 0xff, fallback);
|
||||
nvram_read_u8(prefix, NULL, "aa2g", &sprom->ant_available_bg, 0,
|
||||
fallback);
|
||||
nvram_read_u8(prefix, NULL, "aa5g", &sprom->ant_available_a, 0,
|
||||
fallback);
|
||||
nvram_read_s8(prefix, NULL, "ag0", &sprom->antenna_gain.a0, 0,
|
||||
fallback);
|
||||
nvram_read_s8(prefix, NULL, "ag1", &sprom->antenna_gain.a1, 0,
|
||||
fallback);
|
||||
nvram_read_alpha2(prefix, "ccode", sprom->alpha2, fallback);
|
||||
}
|
||||
|
||||
static void bcm47xx_fill_sprom_r12389(struct ssb_sprom *sprom,
|
||||
const char *prefix, bool fallback)
|
||||
{
|
||||
nvram_read_u16(prefix, NULL, "pa0b0", &sprom->pa0b0, 0, fallback);
|
||||
nvram_read_u16(prefix, NULL, "pa0b1", &sprom->pa0b1, 0, fallback);
|
||||
nvram_read_u16(prefix, NULL, "pa0b2", &sprom->pa0b2, 0, fallback);
|
||||
nvram_read_u8(prefix, NULL, "pa0itssit", &sprom->itssi_bg, 0, fallback);
|
||||
nvram_read_u8(prefix, NULL, "pa0maxpwr", &sprom->maxpwr_bg, 0,
|
||||
fallback);
|
||||
nvram_read_u16(prefix, NULL, "pa1b0", &sprom->pa1b0, 0, fallback);
|
||||
nvram_read_u16(prefix, NULL, "pa1b1", &sprom->pa1b1, 0, fallback);
|
||||
nvram_read_u16(prefix, NULL, "pa1b2", &sprom->pa1b2, 0, fallback);
|
||||
nvram_read_u8(prefix, NULL, "pa1itssit", &sprom->itssi_a, 0, fallback);
|
||||
nvram_read_u8(prefix, NULL, "pa1maxpwr", &sprom->maxpwr_a, 0, fallback);
|
||||
}
|
||||
|
||||
static void bcm47xx_fill_sprom_r1(struct ssb_sprom *sprom, const char *prefix,
|
||||
bool fallback)
|
||||
{
|
||||
nvram_read_u16(prefix, NULL, "boardflags", &sprom->boardflags_lo, 0,
|
||||
fallback);
|
||||
nvram_read_u8(prefix, NULL, "cc", &sprom->country_code, 0, fallback);
|
||||
}
|
||||
|
||||
static void bcm47xx_fill_sprom_r2389(struct ssb_sprom *sprom,
|
||||
const char *prefix, bool fallback)
|
||||
{
|
||||
nvram_read_u8(prefix, NULL, "opo", &sprom->opo, 0, fallback);
|
||||
nvram_read_u16(prefix, NULL, "pa1lob0", &sprom->pa1lob0, 0, fallback);
|
||||
nvram_read_u16(prefix, NULL, "pa1lob1", &sprom->pa1lob1, 0, fallback);
|
||||
nvram_read_u16(prefix, NULL, "pa1lob2", &sprom->pa1lob2, 0, fallback);
|
||||
nvram_read_u16(prefix, NULL, "pa1hib0", &sprom->pa1hib0, 0, fallback);
|
||||
nvram_read_u16(prefix, NULL, "pa1hib1", &sprom->pa1hib1, 0, fallback);
|
||||
nvram_read_u16(prefix, NULL, "pa1hib2", &sprom->pa1hib2, 0, fallback);
|
||||
nvram_read_u8(prefix, NULL, "pa1lomaxpwr", &sprom->maxpwr_al, 0,
|
||||
fallback);
|
||||
nvram_read_u8(prefix, NULL, "pa1himaxpwr", &sprom->maxpwr_ah, 0,
|
||||
fallback);
|
||||
}
|
||||
|
||||
static void bcm47xx_fill_sprom_r389(struct ssb_sprom *sprom, const char *prefix,
|
||||
bool fallback)
|
||||
{
|
||||
nvram_read_u8(prefix, NULL, "bxa2g", &sprom->bxa2g, 0, fallback);
|
||||
nvram_read_u8(prefix, NULL, "rssisav2g", &sprom->rssisav2g, 0,
|
||||
fallback);
|
||||
nvram_read_u8(prefix, NULL, "rssismc2g", &sprom->rssismc2g, 0,
|
||||
fallback);
|
||||
nvram_read_u8(prefix, NULL, "rssismf2g", &sprom->rssismf2g, 0,
|
||||
fallback);
|
||||
nvram_read_u8(prefix, NULL, "bxa5g", &sprom->bxa5g, 0, fallback);
|
||||
nvram_read_u8(prefix, NULL, "rssisav5g", &sprom->rssisav5g, 0,
|
||||
fallback);
|
||||
nvram_read_u8(prefix, NULL, "rssismc5g", &sprom->rssismc5g, 0,
|
||||
fallback);
|
||||
nvram_read_u8(prefix, NULL, "rssismf5g", &sprom->rssismf5g, 0,
|
||||
fallback);
|
||||
nvram_read_u8(prefix, NULL, "tri2g", &sprom->tri2g, 0, fallback);
|
||||
nvram_read_u8(prefix, NULL, "tri5g", &sprom->tri5g, 0, fallback);
|
||||
nvram_read_u8(prefix, NULL, "tri5gl", &sprom->tri5gl, 0, fallback);
|
||||
nvram_read_u8(prefix, NULL, "tri5gh", &sprom->tri5gh, 0, fallback);
|
||||
nvram_read_s8(prefix, NULL, "rxpo2g", &sprom->rxpo2g, 0, fallback);
|
||||
nvram_read_s8(prefix, NULL, "rxpo5g", &sprom->rxpo5g, 0, fallback);
|
||||
}
|
||||
|
||||
static void bcm47xx_fill_sprom_r3(struct ssb_sprom *sprom, const char *prefix,
|
||||
bool fallback)
|
||||
{
|
||||
nvram_read_u8(prefix, NULL, "regrev", &sprom->regrev, 0, fallback);
|
||||
nvram_read_leddc(prefix, "leddc", &sprom->leddc_on_time,
|
||||
&sprom->leddc_off_time, fallback);
|
||||
}
|
||||
|
|
@ -276,309 +426,10 @@ static void bcm47xx_fill_sprom_r3(struct ssb_sprom *sprom, const char *prefix,
|
|||
static void bcm47xx_fill_sprom_r4589(struct ssb_sprom *sprom,
|
||||
const char *prefix, bool fallback)
|
||||
{
|
||||
nvram_read_u8(prefix, NULL, "regrev", &sprom->regrev, 0, fallback);
|
||||
nvram_read_s8(prefix, NULL, "ag2", &sprom->antenna_gain.a2, 0,
|
||||
fallback);
|
||||
nvram_read_s8(prefix, NULL, "ag3", &sprom->antenna_gain.a3, 0,
|
||||
fallback);
|
||||
nvram_read_u8(prefix, NULL, "txchain", &sprom->txchain, 0xf, fallback);
|
||||
nvram_read_u8(prefix, NULL, "rxchain", &sprom->rxchain, 0xf, fallback);
|
||||
nvram_read_u8(prefix, NULL, "antswitch", &sprom->antswitch, 0xff,
|
||||
fallback);
|
||||
nvram_read_leddc(prefix, "leddc", &sprom->leddc_on_time,
|
||||
&sprom->leddc_off_time, fallback);
|
||||
}
|
||||
|
||||
static void bcm47xx_fill_sprom_r458(struct ssb_sprom *sprom, const char *prefix,
|
||||
bool fallback)
|
||||
{
|
||||
nvram_read_u16(prefix, NULL, "cck2gpo", &sprom->cck2gpo, 0, fallback);
|
||||
nvram_read_u32(prefix, NULL, "ofdm2gpo", &sprom->ofdm2gpo, 0, fallback);
|
||||
nvram_read_u32(prefix, NULL, "ofdm5gpo", &sprom->ofdm5gpo, 0, fallback);
|
||||
nvram_read_u32(prefix, NULL, "ofdm5glpo", &sprom->ofdm5glpo, 0,
|
||||
fallback);
|
||||
nvram_read_u32(prefix, NULL, "ofdm5ghpo", &sprom->ofdm5ghpo, 0,
|
||||
fallback);
|
||||
nvram_read_u16(prefix, NULL, "cddpo", &sprom->cddpo, 0, fallback);
|
||||
nvram_read_u16(prefix, NULL, "stbcpo", &sprom->stbcpo, 0, fallback);
|
||||
nvram_read_u16(prefix, NULL, "bw40po", &sprom->bw40po, 0, fallback);
|
||||
nvram_read_u16(prefix, NULL, "bwduppo", &sprom->bwduppo, 0, fallback);
|
||||
nvram_read_u16(prefix, NULL, "mcs2gpo0", &sprom->mcs2gpo[0], 0,
|
||||
fallback);
|
||||
nvram_read_u16(prefix, NULL, "mcs2gpo1", &sprom->mcs2gpo[1], 0,
|
||||
fallback);
|
||||
nvram_read_u16(prefix, NULL, "mcs2gpo2", &sprom->mcs2gpo[2], 0,
|
||||
fallback);
|
||||
nvram_read_u16(prefix, NULL, "mcs2gpo3", &sprom->mcs2gpo[3], 0,
|
||||
fallback);
|
||||
nvram_read_u16(prefix, NULL, "mcs2gpo4", &sprom->mcs2gpo[4], 0,
|
||||
fallback);
|
||||
nvram_read_u16(prefix, NULL, "mcs2gpo5", &sprom->mcs2gpo[5], 0,
|
||||
fallback);
|
||||
nvram_read_u16(prefix, NULL, "mcs2gpo6", &sprom->mcs2gpo[6], 0,
|
||||
fallback);
|
||||
nvram_read_u16(prefix, NULL, "mcs2gpo7", &sprom->mcs2gpo[7], 0,
|
||||
fallback);
|
||||
nvram_read_u16(prefix, NULL, "mcs5gpo0", &sprom->mcs5gpo[0], 0,
|
||||
fallback);
|
||||
nvram_read_u16(prefix, NULL, "mcs5gpo1", &sprom->mcs5gpo[1], 0,
|
||||
fallback);
|
||||
nvram_read_u16(prefix, NULL, "mcs5gpo2", &sprom->mcs5gpo[2], 0,
|
||||
fallback);
|
||||
nvram_read_u16(prefix, NULL, "mcs5gpo3", &sprom->mcs5gpo[3], 0,
|
||||
fallback);
|
||||
nvram_read_u16(prefix, NULL, "mcs5gpo4", &sprom->mcs5gpo[4], 0,
|
||||
fallback);
|
||||
nvram_read_u16(prefix, NULL, "mcs5gpo5", &sprom->mcs5gpo[5], 0,
|
||||
fallback);
|
||||
nvram_read_u16(prefix, NULL, "mcs5gpo6", &sprom->mcs5gpo[6], 0,
|
||||
fallback);
|
||||
nvram_read_u16(prefix, NULL, "mcs5gpo7", &sprom->mcs5gpo[7], 0,
|
||||
fallback);
|
||||
nvram_read_u16(prefix, NULL, "mcs5glpo0", &sprom->mcs5glpo[0], 0,
|
||||
fallback);
|
||||
nvram_read_u16(prefix, NULL, "mcs5glpo1", &sprom->mcs5glpo[1], 0,
|
||||
fallback);
|
||||
nvram_read_u16(prefix, NULL, "mcs5glpo2", &sprom->mcs5glpo[2], 0,
|
||||
fallback);
|
||||
nvram_read_u16(prefix, NULL, "mcs5glpo3", &sprom->mcs5glpo[3], 0,
|
||||
fallback);
|
||||
nvram_read_u16(prefix, NULL, "mcs5glpo4", &sprom->mcs5glpo[4], 0,
|
||||
fallback);
|
||||
nvram_read_u16(prefix, NULL, "mcs5glpo5", &sprom->mcs5glpo[5], 0,
|
||||
fallback);
|
||||
nvram_read_u16(prefix, NULL, "mcs5glpo6", &sprom->mcs5glpo[6], 0,
|
||||
fallback);
|
||||
nvram_read_u16(prefix, NULL, "mcs5glpo7", &sprom->mcs5glpo[7], 0,
|
||||
fallback);
|
||||
nvram_read_u16(prefix, NULL, "mcs5ghpo0", &sprom->mcs5ghpo[0], 0,
|
||||
fallback);
|
||||
nvram_read_u16(prefix, NULL, "mcs5ghpo1", &sprom->mcs5ghpo[1], 0,
|
||||
fallback);
|
||||
nvram_read_u16(prefix, NULL, "mcs5ghpo2", &sprom->mcs5ghpo[2], 0,
|
||||
fallback);
|
||||
nvram_read_u16(prefix, NULL, "mcs5ghpo3", &sprom->mcs5ghpo[3], 0,
|
||||
fallback);
|
||||
nvram_read_u16(prefix, NULL, "mcs5ghpo4", &sprom->mcs5ghpo[4], 0,
|
||||
fallback);
|
||||
nvram_read_u16(prefix, NULL, "mcs5ghpo5", &sprom->mcs5ghpo[5], 0,
|
||||
fallback);
|
||||
nvram_read_u16(prefix, NULL, "mcs5ghpo6", &sprom->mcs5ghpo[6], 0,
|
||||
fallback);
|
||||
nvram_read_u16(prefix, NULL, "mcs5ghpo7", &sprom->mcs5ghpo[7], 0,
|
||||
fallback);
|
||||
}
|
||||
|
||||
static void bcm47xx_fill_sprom_r45(struct ssb_sprom *sprom, const char *prefix,
|
||||
bool fallback)
|
||||
{
|
||||
nvram_read_u8(prefix, NULL, "txpid2ga0", &sprom->txpid2g[0], 0,
|
||||
fallback);
|
||||
nvram_read_u8(prefix, NULL, "txpid2ga1", &sprom->txpid2g[1], 0,
|
||||
fallback);
|
||||
nvram_read_u8(prefix, NULL, "txpid2ga2", &sprom->txpid2g[2], 0,
|
||||
fallback);
|
||||
nvram_read_u8(prefix, NULL, "txpid2ga3", &sprom->txpid2g[3], 0,
|
||||
fallback);
|
||||
nvram_read_u8(prefix, NULL, "txpid5ga0", &sprom->txpid5g[0], 0,
|
||||
fallback);
|
||||
nvram_read_u8(prefix, NULL, "txpid5ga1", &sprom->txpid5g[1], 0,
|
||||
fallback);
|
||||
nvram_read_u8(prefix, NULL, "txpid5ga2", &sprom->txpid5g[2], 0,
|
||||
fallback);
|
||||
nvram_read_u8(prefix, NULL, "txpid5ga3", &sprom->txpid5g[3], 0,
|
||||
fallback);
|
||||
nvram_read_u8(prefix, NULL, "txpid5gla0", &sprom->txpid5gl[0], 0,
|
||||
fallback);
|
||||
nvram_read_u8(prefix, NULL, "txpid5gla1", &sprom->txpid5gl[1], 0,
|
||||
fallback);
|
||||
nvram_read_u8(prefix, NULL, "txpid5gla2", &sprom->txpid5gl[2], 0,
|
||||
fallback);
|
||||
nvram_read_u8(prefix, NULL, "txpid5gla3", &sprom->txpid5gl[3], 0,
|
||||
fallback);
|
||||
nvram_read_u8(prefix, NULL, "txpid5gha0", &sprom->txpid5gh[0], 0,
|
||||
fallback);
|
||||
nvram_read_u8(prefix, NULL, "txpid5gha1", &sprom->txpid5gh[1], 0,
|
||||
fallback);
|
||||
nvram_read_u8(prefix, NULL, "txpid5gha2", &sprom->txpid5gh[2], 0,
|
||||
fallback);
|
||||
nvram_read_u8(prefix, NULL, "txpid5gha3", &sprom->txpid5gh[3], 0,
|
||||
fallback);
|
||||
}
|
||||
|
||||
static void bcm47xx_fill_sprom_r89(struct ssb_sprom *sprom, const char *prefix,
|
||||
bool fallback)
|
||||
{
|
||||
nvram_read_u8(prefix, NULL, "tssipos2g", &sprom->fem.ghz2.tssipos, 0,
|
||||
fallback);
|
||||
nvram_read_u8(prefix, NULL, "extpagain2g",
|
||||
&sprom->fem.ghz2.extpa_gain, 0, fallback);
|
||||
nvram_read_u8(prefix, NULL, "pdetrange2g",
|
||||
&sprom->fem.ghz2.pdet_range, 0, fallback);
|
||||
nvram_read_u8(prefix, NULL, "triso2g", &sprom->fem.ghz2.tr_iso, 0,
|
||||
fallback);
|
||||
nvram_read_u8(prefix, NULL, "antswctl2g", &sprom->fem.ghz2.antswlut, 0,
|
||||
fallback);
|
||||
nvram_read_u8(prefix, NULL, "tssipos5g", &sprom->fem.ghz5.tssipos, 0,
|
||||
fallback);
|
||||
nvram_read_u8(prefix, NULL, "extpagain5g",
|
||||
&sprom->fem.ghz5.extpa_gain, 0, fallback);
|
||||
nvram_read_u8(prefix, NULL, "pdetrange5g",
|
||||
&sprom->fem.ghz5.pdet_range, 0, fallback);
|
||||
nvram_read_u8(prefix, NULL, "triso5g", &sprom->fem.ghz5.tr_iso, 0,
|
||||
fallback);
|
||||
nvram_read_u8(prefix, NULL, "antswctl5g", &sprom->fem.ghz5.antswlut, 0,
|
||||
fallback);
|
||||
nvram_read_u8(prefix, NULL, "tempthresh", &sprom->tempthresh, 0,
|
||||
fallback);
|
||||
nvram_read_u8(prefix, NULL, "tempoffset", &sprom->tempoffset, 0,
|
||||
fallback);
|
||||
nvram_read_u16(prefix, NULL, "rawtempsense", &sprom->rawtempsense, 0,
|
||||
fallback);
|
||||
nvram_read_u8(prefix, NULL, "measpower", &sprom->measpower, 0,
|
||||
fallback);
|
||||
nvram_read_u8(prefix, NULL, "tempsense_slope",
|
||||
&sprom->tempsense_slope, 0, fallback);
|
||||
nvram_read_u8(prefix, NULL, "tempcorrx", &sprom->tempcorrx, 0,
|
||||
fallback);
|
||||
nvram_read_u8(prefix, NULL, "tempsense_option",
|
||||
&sprom->tempsense_option, 0, fallback);
|
||||
nvram_read_u8(prefix, NULL, "freqoffset_corr",
|
||||
&sprom->freqoffset_corr, 0, fallback);
|
||||
nvram_read_u8(prefix, NULL, "iqcal_swp_dis", &sprom->iqcal_swp_dis, 0,
|
||||
fallback);
|
||||
nvram_read_u8(prefix, NULL, "hw_iqcal_en", &sprom->hw_iqcal_en, 0,
|
||||
fallback);
|
||||
nvram_read_u8(prefix, NULL, "elna2g", &sprom->elna2g, 0, fallback);
|
||||
nvram_read_u8(prefix, NULL, "elna5g", &sprom->elna5g, 0, fallback);
|
||||
nvram_read_u8(prefix, NULL, "phycal_tempdelta",
|
||||
&sprom->phycal_tempdelta, 0, fallback);
|
||||
nvram_read_u8(prefix, NULL, "temps_period", &sprom->temps_period, 0,
|
||||
fallback);
|
||||
nvram_read_u8(prefix, NULL, "temps_hysteresis",
|
||||
&sprom->temps_hysteresis, 0, fallback);
|
||||
nvram_read_u8(prefix, NULL, "measpower1", &sprom->measpower1, 0,
|
||||
fallback);
|
||||
nvram_read_u8(prefix, NULL, "measpower2", &sprom->measpower2, 0,
|
||||
fallback);
|
||||
nvram_read_u8(prefix, NULL, "rxgainerr2ga0",
|
||||
&sprom->rxgainerr2ga[0], 0, fallback);
|
||||
nvram_read_u8(prefix, NULL, "rxgainerr2ga1",
|
||||
&sprom->rxgainerr2ga[1], 0, fallback);
|
||||
nvram_read_u8(prefix, NULL, "rxgainerr2ga2",
|
||||
&sprom->rxgainerr2ga[2], 0, fallback);
|
||||
nvram_read_u8(prefix, NULL, "rxgainerr5gla0",
|
||||
&sprom->rxgainerr5gla[0], 0, fallback);
|
||||
nvram_read_u8(prefix, NULL, "rxgainerr5gla1",
|
||||
&sprom->rxgainerr5gla[1], 0, fallback);
|
||||
nvram_read_u8(prefix, NULL, "rxgainerr5gla2",
|
||||
&sprom->rxgainerr5gla[2], 0, fallback);
|
||||
nvram_read_u8(prefix, NULL, "rxgainerr5gma0",
|
||||
&sprom->rxgainerr5gma[0], 0, fallback);
|
||||
nvram_read_u8(prefix, NULL, "rxgainerr5gma1",
|
||||
&sprom->rxgainerr5gma[1], 0, fallback);
|
||||
nvram_read_u8(prefix, NULL, "rxgainerr5gma2",
|
||||
&sprom->rxgainerr5gma[2], 0, fallback);
|
||||
nvram_read_u8(prefix, NULL, "rxgainerr5gha0",
|
||||
&sprom->rxgainerr5gha[0], 0, fallback);
|
||||
nvram_read_u8(prefix, NULL, "rxgainerr5gha1",
|
||||
&sprom->rxgainerr5gha[1], 0, fallback);
|
||||
nvram_read_u8(prefix, NULL, "rxgainerr5gha2",
|
||||
&sprom->rxgainerr5gha[2], 0, fallback);
|
||||
nvram_read_u8(prefix, NULL, "rxgainerr5gua0",
|
||||
&sprom->rxgainerr5gua[0], 0, fallback);
|
||||
nvram_read_u8(prefix, NULL, "rxgainerr5gua1",
|
||||
&sprom->rxgainerr5gua[1], 0, fallback);
|
||||
nvram_read_u8(prefix, NULL, "rxgainerr5gua2",
|
||||
&sprom->rxgainerr5gua[2], 0, fallback);
|
||||
nvram_read_u8(prefix, NULL, "noiselvl2ga0", &sprom->noiselvl2ga[0], 0,
|
||||
fallback);
|
||||
nvram_read_u8(prefix, NULL, "noiselvl2ga1", &sprom->noiselvl2ga[1], 0,
|
||||
fallback);
|
||||
nvram_read_u8(prefix, NULL, "noiselvl2ga2", &sprom->noiselvl2ga[2], 0,
|
||||
fallback);
|
||||
nvram_read_u8(prefix, NULL, "noiselvl5gla0",
|
||||
&sprom->noiselvl5gla[0], 0, fallback);
|
||||
nvram_read_u8(prefix, NULL, "noiselvl5gla1",
|
||||
&sprom->noiselvl5gla[1], 0, fallback);
|
||||
nvram_read_u8(prefix, NULL, "noiselvl5gla2",
|
||||
&sprom->noiselvl5gla[2], 0, fallback);
|
||||
nvram_read_u8(prefix, NULL, "noiselvl5gma0",
|
||||
&sprom->noiselvl5gma[0], 0, fallback);
|
||||
nvram_read_u8(prefix, NULL, "noiselvl5gma1",
|
||||
&sprom->noiselvl5gma[1], 0, fallback);
|
||||
nvram_read_u8(prefix, NULL, "noiselvl5gma2",
|
||||
&sprom->noiselvl5gma[2], 0, fallback);
|
||||
nvram_read_u8(prefix, NULL, "noiselvl5gha0",
|
||||
&sprom->noiselvl5gha[0], 0, fallback);
|
||||
nvram_read_u8(prefix, NULL, "noiselvl5gha1",
|
||||
&sprom->noiselvl5gha[1], 0, fallback);
|
||||
nvram_read_u8(prefix, NULL, "noiselvl5gha2",
|
||||
&sprom->noiselvl5gha[2], 0, fallback);
|
||||
nvram_read_u8(prefix, NULL, "noiselvl5gua0",
|
||||
&sprom->noiselvl5gua[0], 0, fallback);
|
||||
nvram_read_u8(prefix, NULL, "noiselvl5gua1",
|
||||
&sprom->noiselvl5gua[1], 0, fallback);
|
||||
nvram_read_u8(prefix, NULL, "noiselvl5gua2",
|
||||
&sprom->noiselvl5gua[2], 0, fallback);
|
||||
nvram_read_u8(prefix, NULL, "pcieingress_war",
|
||||
&sprom->pcieingress_war, 0, fallback);
|
||||
}
|
||||
|
||||
static void bcm47xx_fill_sprom_r9(struct ssb_sprom *sprom, const char *prefix,
|
||||
bool fallback)
|
||||
{
|
||||
nvram_read_u16(prefix, NULL, "cckbw202gpo", &sprom->cckbw202gpo, 0,
|
||||
fallback);
|
||||
nvram_read_u16(prefix, NULL, "cckbw20ul2gpo", &sprom->cckbw20ul2gpo, 0,
|
||||
fallback);
|
||||
nvram_read_u32(prefix, NULL, "legofdmbw202gpo",
|
||||
&sprom->legofdmbw202gpo, 0, fallback);
|
||||
nvram_read_u32(prefix, NULL, "legofdmbw20ul2gpo",
|
||||
&sprom->legofdmbw20ul2gpo, 0, fallback);
|
||||
nvram_read_u32(prefix, NULL, "legofdmbw205glpo",
|
||||
&sprom->legofdmbw205glpo, 0, fallback);
|
||||
nvram_read_u32(prefix, NULL, "legofdmbw20ul5glpo",
|
||||
&sprom->legofdmbw20ul5glpo, 0, fallback);
|
||||
nvram_read_u32(prefix, NULL, "legofdmbw205gmpo",
|
||||
&sprom->legofdmbw205gmpo, 0, fallback);
|
||||
nvram_read_u32(prefix, NULL, "legofdmbw20ul5gmpo",
|
||||
&sprom->legofdmbw20ul5gmpo, 0, fallback);
|
||||
nvram_read_u32(prefix, NULL, "legofdmbw205ghpo",
|
||||
&sprom->legofdmbw205ghpo, 0, fallback);
|
||||
nvram_read_u32(prefix, NULL, "legofdmbw20ul5ghpo",
|
||||
&sprom->legofdmbw20ul5ghpo, 0, fallback);
|
||||
nvram_read_u32(prefix, NULL, "mcsbw202gpo", &sprom->mcsbw202gpo, 0,
|
||||
fallback);
|
||||
nvram_read_u32(prefix, NULL, "mcsbw20ul2gpo", &sprom->mcsbw20ul2gpo, 0,
|
||||
fallback);
|
||||
nvram_read_u32(prefix, NULL, "mcsbw402gpo", &sprom->mcsbw402gpo, 0,
|
||||
fallback);
|
||||
nvram_read_u32(prefix, NULL, "mcsbw205glpo", &sprom->mcsbw205glpo, 0,
|
||||
fallback);
|
||||
nvram_read_u32(prefix, NULL, "mcsbw20ul5glpo",
|
||||
&sprom->mcsbw20ul5glpo, 0, fallback);
|
||||
nvram_read_u32(prefix, NULL, "mcsbw405glpo", &sprom->mcsbw405glpo, 0,
|
||||
fallback);
|
||||
nvram_read_u32(prefix, NULL, "mcsbw205gmpo", &sprom->mcsbw205gmpo, 0,
|
||||
fallback);
|
||||
nvram_read_u32(prefix, NULL, "mcsbw20ul5gmpo",
|
||||
&sprom->mcsbw20ul5gmpo, 0, fallback);
|
||||
nvram_read_u32(prefix, NULL, "mcsbw405gmpo", &sprom->mcsbw405gmpo, 0,
|
||||
fallback);
|
||||
nvram_read_u32(prefix, NULL, "mcsbw205ghpo", &sprom->mcsbw205ghpo, 0,
|
||||
fallback);
|
||||
nvram_read_u32(prefix, NULL, "mcsbw20ul5ghpo",
|
||||
&sprom->mcsbw20ul5ghpo, 0, fallback);
|
||||
nvram_read_u32(prefix, NULL, "mcsbw405ghpo", &sprom->mcsbw405ghpo, 0,
|
||||
fallback);
|
||||
nvram_read_u16(prefix, NULL, "mcs32po", &sprom->mcs32po, 0, fallback);
|
||||
nvram_read_u16(prefix, NULL, "legofdm40duppo",
|
||||
&sprom->legofdm40duppo, 0, fallback);
|
||||
nvram_read_u8(prefix, NULL, "sar2g", &sprom->sar2g, 0, fallback);
|
||||
nvram_read_u8(prefix, NULL, "sar5g", &sprom->sar5g, 0, fallback);
|
||||
}
|
||||
|
||||
static void bcm47xx_fill_sprom_path_r4589(struct ssb_sprom *sprom,
|
||||
const char *prefix, bool fallback)
|
||||
{
|
||||
|
|
@ -715,10 +566,6 @@ static void bcm47xx_fill_sprom_ethernet(struct ssb_sprom *sprom,
|
|||
static void bcm47xx_fill_board_data(struct ssb_sprom *sprom, const char *prefix,
|
||||
bool fallback)
|
||||
{
|
||||
nvram_read_u16(prefix, NULL, "boardrev", &sprom->board_rev, 0, true);
|
||||
nvram_read_u16(prefix, NULL, "boardnum", &sprom->board_num, 0,
|
||||
fallback);
|
||||
nvram_read_u16(prefix, NULL, "boardtype", &sprom->board_type, 0, true);
|
||||
nvram_read_u32_2(prefix, "boardflags", &sprom->boardflags_lo,
|
||||
&sprom->boardflags_hi, fallback);
|
||||
nvram_read_u32_2(prefix, "boardflags2", &sprom->boardflags2_lo,
|
||||
|
|
@ -736,58 +583,39 @@ void bcm47xx_fill_sprom(struct ssb_sprom *sprom, const char *prefix,
|
|||
switch (sprom->revision) {
|
||||
case 1:
|
||||
bcm47xx_fill_sprom_r1234589(sprom, prefix, fallback);
|
||||
bcm47xx_fill_sprom_r12389(sprom, prefix, fallback);
|
||||
bcm47xx_fill_sprom_r1(sprom, prefix, fallback);
|
||||
break;
|
||||
case 2:
|
||||
bcm47xx_fill_sprom_r1234589(sprom, prefix, fallback);
|
||||
bcm47xx_fill_sprom_r12389(sprom, prefix, fallback);
|
||||
bcm47xx_fill_sprom_r2389(sprom, prefix, fallback);
|
||||
break;
|
||||
case 3:
|
||||
bcm47xx_fill_sprom_r1234589(sprom, prefix, fallback);
|
||||
bcm47xx_fill_sprom_r12389(sprom, prefix, fallback);
|
||||
bcm47xx_fill_sprom_r2389(sprom, prefix, fallback);
|
||||
bcm47xx_fill_sprom_r389(sprom, prefix, fallback);
|
||||
bcm47xx_fill_sprom_r3(sprom, prefix, fallback);
|
||||
break;
|
||||
case 4:
|
||||
case 5:
|
||||
bcm47xx_fill_sprom_r1234589(sprom, prefix, fallback);
|
||||
bcm47xx_fill_sprom_r4589(sprom, prefix, fallback);
|
||||
bcm47xx_fill_sprom_r458(sprom, prefix, fallback);
|
||||
bcm47xx_fill_sprom_r45(sprom, prefix, fallback);
|
||||
bcm47xx_fill_sprom_path_r4589(sprom, prefix, fallback);
|
||||
bcm47xx_fill_sprom_path_r45(sprom, prefix, fallback);
|
||||
break;
|
||||
case 8:
|
||||
bcm47xx_fill_sprom_r1234589(sprom, prefix, fallback);
|
||||
bcm47xx_fill_sprom_r12389(sprom, prefix, fallback);
|
||||
bcm47xx_fill_sprom_r2389(sprom, prefix, fallback);
|
||||
bcm47xx_fill_sprom_r389(sprom, prefix, fallback);
|
||||
bcm47xx_fill_sprom_r4589(sprom, prefix, fallback);
|
||||
bcm47xx_fill_sprom_r458(sprom, prefix, fallback);
|
||||
bcm47xx_fill_sprom_r89(sprom, prefix, fallback);
|
||||
bcm47xx_fill_sprom_path_r4589(sprom, prefix, fallback);
|
||||
break;
|
||||
case 9:
|
||||
bcm47xx_fill_sprom_r1234589(sprom, prefix, fallback);
|
||||
bcm47xx_fill_sprom_r12389(sprom, prefix, fallback);
|
||||
bcm47xx_fill_sprom_r2389(sprom, prefix, fallback);
|
||||
bcm47xx_fill_sprom_r389(sprom, prefix, fallback);
|
||||
bcm47xx_fill_sprom_r4589(sprom, prefix, fallback);
|
||||
bcm47xx_fill_sprom_r89(sprom, prefix, fallback);
|
||||
bcm47xx_fill_sprom_r9(sprom, prefix, fallback);
|
||||
bcm47xx_fill_sprom_path_r4589(sprom, prefix, fallback);
|
||||
break;
|
||||
default:
|
||||
pr_warn("Unsupported SPROM revision %d detected. Will extract"
|
||||
" v1\n", sprom->revision);
|
||||
pr_warn("Unsupported SPROM revision %d detected. Will extract v1\n",
|
||||
sprom->revision);
|
||||
sprom->revision = 1;
|
||||
bcm47xx_fill_sprom_r1234589(sprom, prefix, fallback);
|
||||
bcm47xx_fill_sprom_r12389(sprom, prefix, fallback);
|
||||
bcm47xx_fill_sprom_r1(sprom, prefix, fallback);
|
||||
}
|
||||
|
||||
bcm47xx_sprom_fill_auto(sprom, prefix, fallback);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_BCM47XX_SSB
|
||||
|
|
@ -829,13 +657,45 @@ static int bcm47xx_get_sprom_ssb(struct ssb_bus *bus, struct ssb_sprom *out)
|
|||
bcm47xx_fill_sprom(out, prefix, false);
|
||||
return 0;
|
||||
} else {
|
||||
pr_warn("bcm47xx: unable to fill SPROM for given bustype.\n");
|
||||
pr_warn("Unable to fill SPROM for given bustype.\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_BCM47XX_BCMA)
|
||||
/*
|
||||
* Having many NVRAM entries for PCI devices led to repeating prefixes like
|
||||
* pci/1/1/ all the time and wasting flash space. So at some point Broadcom
|
||||
* decided to introduce prefixes like 0: 1: 2: etc.
|
||||
* If we find e.g. devpath0=pci/2/1 or devpath0=pci/2/1/ we should use 0:
|
||||
* instead of pci/2/1/.
|
||||
*/
|
||||
static void bcm47xx_sprom_apply_prefix_alias(char *prefix, size_t prefix_size)
|
||||
{
|
||||
size_t prefix_len = strlen(prefix);
|
||||
size_t short_len = prefix_len - 1;
|
||||
char nvram_var[10];
|
||||
char buf[20];
|
||||
int i;
|
||||
|
||||
/* Passed prefix has to end with a slash */
|
||||
if (prefix_len <= 0 || prefix[prefix_len - 1] != '/')
|
||||
return;
|
||||
|
||||
for (i = 0; i < 3; i++) {
|
||||
if (snprintf(nvram_var, sizeof(nvram_var), "devpath%d", i) <= 0)
|
||||
continue;
|
||||
if (bcm47xx_nvram_getenv(nvram_var, buf, sizeof(buf)) < 0)
|
||||
continue;
|
||||
if (!strcmp(buf, prefix) ||
|
||||
(short_len && strlen(buf) == short_len && !strncmp(buf, prefix, short_len))) {
|
||||
snprintf(prefix, prefix_size, "%d:", i);
|
||||
return;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static int bcm47xx_get_sprom_bcma(struct bcma_bus *bus, struct ssb_sprom *out)
|
||||
{
|
||||
char prefix[10];
|
||||
|
|
@ -847,6 +707,7 @@ static int bcm47xx_get_sprom_bcma(struct bcma_bus *bus, struct ssb_sprom *out)
|
|||
snprintf(prefix, sizeof(prefix), "pci/%u/%u/",
|
||||
bus->host_pci->bus->number + 1,
|
||||
PCI_SLOT(bus->host_pci->devfn));
|
||||
bcm47xx_sprom_apply_prefix_alias(prefix, sizeof(prefix));
|
||||
bcm47xx_fill_sprom(out, prefix, false);
|
||||
return 0;
|
||||
case BCMA_HOSTTYPE_SOC:
|
||||
|
|
@ -861,7 +722,7 @@ static int bcm47xx_get_sprom_bcma(struct bcma_bus *bus, struct ssb_sprom *out)
|
|||
}
|
||||
return 0;
|
||||
default:
|
||||
pr_warn("bcm47xx: unable to fill SPROM for given bustype.\n");
|
||||
pr_warn("Unable to fill SPROM for given bustype.\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -22,12 +22,10 @@
|
|||
* 675 Mass Ave, Cambridge, MA 02139, USA.
|
||||
*/
|
||||
|
||||
|
||||
#include <linux/init.h>
|
||||
#include <linux/ssb/ssb.h>
|
||||
#include <asm/time.h>
|
||||
#include <bcm47xx.h>
|
||||
#include <bcm47xx_nvram.h>
|
||||
#include <bcm47xx_board.h>
|
||||
|
||||
void __init plat_time_init(void)
|
||||
|
|
|
|||
|
|
@ -17,7 +17,6 @@
|
|||
#include <bcm63xx_cpu.h>
|
||||
#include <bcm63xx_io.h>
|
||||
#include <bcm63xx_regs.h>
|
||||
#include <bcm63xx_gpio.h>
|
||||
|
||||
void __init prom_init(void)
|
||||
{
|
||||
|
|
@ -53,9 +52,6 @@ void __init prom_init(void)
|
|||
reg &= ~mask;
|
||||
bcm_perf_writel(reg, PERF_CKCTL_REG);
|
||||
|
||||
/* register gpiochip */
|
||||
bcm63xx_gpio_init();
|
||||
|
||||
/* do low level board init */
|
||||
board_prom_init();
|
||||
|
||||
|
|
|
|||
|
|
@ -20,6 +20,7 @@
|
|||
#include <bcm63xx_cpu.h>
|
||||
#include <bcm63xx_regs.h>
|
||||
#include <bcm63xx_io.h>
|
||||
#include <bcm63xx_gpio.h>
|
||||
|
||||
void bcm63xx_machine_halt(void)
|
||||
{
|
||||
|
|
@ -160,6 +161,9 @@ void __init plat_mem_setup(void)
|
|||
|
||||
int __init bcm63xx_register_devices(void)
|
||||
{
|
||||
/* register gpiochip */
|
||||
bcm63xx_gpio_init();
|
||||
|
||||
return board_register_devices();
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,62 @@
|
|||
if BMIPS_GENERIC
|
||||
|
||||
choice
|
||||
prompt "Built-in device tree"
|
||||
help
|
||||
Legacy bootloaders do not pass a DTB pointer to the kernel, so
|
||||
if a "wrapper" is not being used, the kernel will need to include
|
||||
a device tree that matches the target board.
|
||||
|
||||
The builtin DTB will only be used if the firmware does not supply
|
||||
a valid DTB.
|
||||
|
||||
config DT_NONE
|
||||
bool "None"
|
||||
|
||||
config DT_BCM93384WVG
|
||||
bool "BCM93384WVG Zephyr CPU"
|
||||
select BUILTIN_DTB
|
||||
|
||||
config DT_BCM93384WVG_VIPER
|
||||
bool "BCM93384WVG Viper CPU (EXPERIMENTAL)"
|
||||
select BUILTIN_DTB
|
||||
|
||||
config DT_BCM96368MVWG
|
||||
bool "BCM96368MVWG"
|
||||
select BUILTIN_DTB
|
||||
|
||||
config DT_BCM9EJTAGPRB
|
||||
bool "BCM9EJTAGPRB"
|
||||
select BUILTIN_DTB
|
||||
|
||||
config DT_BCM97125CBMB
|
||||
bool "BCM97125CBMB"
|
||||
select BUILTIN_DTB
|
||||
|
||||
config DT_BCM97346DBSMB
|
||||
bool "BCM97346DBSMB"
|
||||
select BUILTIN_DTB
|
||||
|
||||
config DT_BCM97358SVMB
|
||||
bool "BCM97358SVMB"
|
||||
select BUILTIN_DTB
|
||||
|
||||
config DT_BCM97360SVMB
|
||||
bool "BCM97360SVMB"
|
||||
select BUILTIN_DTB
|
||||
|
||||
config DT_BCM97362SVMB
|
||||
bool "BCM97362SVMB"
|
||||
select BUILTIN_DTB
|
||||
|
||||
config DT_BCM97420C
|
||||
bool "BCM97420C"
|
||||
select BUILTIN_DTB
|
||||
|
||||
config DT_BCM97425SVMB
|
||||
bool "BCM97425SVMB"
|
||||
select BUILTIN_DTB
|
||||
|
||||
endchoice
|
||||
|
||||
endif
|
||||
|
|
@ -0,0 +1,7 @@
|
|||
#
|
||||
# Broadcom Generic BMIPS kernel
|
||||
#
|
||||
platform-$(CONFIG_BMIPS_GENERIC) += bmips/
|
||||
cflags-$(CONFIG_BMIPS_GENERIC) += \
|
||||
-I$(srctree)/arch/mips/include/asm/mach-bmips/
|
||||
load-$(CONFIG_BMIPS_GENERIC) := 0xffffffff80010000
|
||||
|
|
@ -0,0 +1,117 @@
|
|||
/*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*
|
||||
* Copyright (C) 2014 Kevin Cernekee <cernekee@gmail.com>
|
||||
*/
|
||||
|
||||
#define pr_fmt(fmt) "bmips-dma: " fmt
|
||||
|
||||
#include <linux/device.h>
|
||||
#include <linux/dma-direction.h>
|
||||
#include <linux/dma-mapping.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/printk.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/types.h>
|
||||
#include <dma-coherence.h>
|
||||
|
||||
/*
|
||||
* BCM338x has configurable address translation windows which allow the
|
||||
* peripherals' DMA addresses to be different from the Zephyr-visible
|
||||
* physical addresses. e.g. usb_dma_addr = zephyr_pa ^ 0x08000000
|
||||
*
|
||||
* If the "brcm,ubus" node has a "dma-ranges" property we will enable this
|
||||
* translation globally using the provided information. This implements a
|
||||
* very limited subset of "dma-ranges" support and it will probably be
|
||||
* replaced by a more generic version later.
|
||||
*/
|
||||
|
||||
struct bmips_dma_range {
|
||||
u32 child_addr;
|
||||
u32 parent_addr;
|
||||
u32 size;
|
||||
};
|
||||
|
||||
static struct bmips_dma_range *bmips_dma_ranges;
|
||||
|
||||
#define FLUSH_RAC 0x100
|
||||
|
||||
static dma_addr_t bmips_phys_to_dma(struct device *dev, phys_addr_t pa)
|
||||
{
|
||||
struct bmips_dma_range *r;
|
||||
|
||||
for (r = bmips_dma_ranges; r && r->size; r++) {
|
||||
if (pa >= r->child_addr &&
|
||||
pa < (r->child_addr + r->size))
|
||||
return pa - r->child_addr + r->parent_addr;
|
||||
}
|
||||
return pa;
|
||||
}
|
||||
|
||||
dma_addr_t plat_map_dma_mem(struct device *dev, void *addr, size_t size)
|
||||
{
|
||||
return bmips_phys_to_dma(dev, virt_to_phys(addr));
|
||||
}
|
||||
|
||||
dma_addr_t plat_map_dma_mem_page(struct device *dev, struct page *page)
|
||||
{
|
||||
return bmips_phys_to_dma(dev, page_to_phys(page));
|
||||
}
|
||||
|
||||
unsigned long plat_dma_addr_to_phys(struct device *dev, dma_addr_t dma_addr)
|
||||
{
|
||||
struct bmips_dma_range *r;
|
||||
|
||||
for (r = bmips_dma_ranges; r && r->size; r++) {
|
||||
if (dma_addr >= r->parent_addr &&
|
||||
dma_addr < (r->parent_addr + r->size))
|
||||
return dma_addr - r->parent_addr + r->child_addr;
|
||||
}
|
||||
return dma_addr;
|
||||
}
|
||||
|
||||
static int __init bmips_init_dma_ranges(void)
|
||||
{
|
||||
struct device_node *np =
|
||||
of_find_compatible_node(NULL, NULL, "brcm,ubus");
|
||||
const __be32 *data;
|
||||
struct bmips_dma_range *r;
|
||||
int len;
|
||||
|
||||
if (!np)
|
||||
return 0;
|
||||
|
||||
data = of_get_property(np, "dma-ranges", &len);
|
||||
if (!data)
|
||||
goto out_good;
|
||||
|
||||
len /= sizeof(*data) * 3;
|
||||
if (!len)
|
||||
goto out_bad;
|
||||
|
||||
/* add a dummy (zero) entry at the end as a sentinel */
|
||||
bmips_dma_ranges = kzalloc(sizeof(struct bmips_dma_range) * (len + 1),
|
||||
GFP_KERNEL);
|
||||
if (!bmips_dma_ranges)
|
||||
goto out_bad;
|
||||
|
||||
for (r = bmips_dma_ranges; len; len--, r++) {
|
||||
r->child_addr = be32_to_cpup(data++);
|
||||
r->parent_addr = be32_to_cpup(data++);
|
||||
r->size = be32_to_cpup(data++);
|
||||
}
|
||||
|
||||
out_good:
|
||||
of_node_put(np);
|
||||
return 0;
|
||||
|
||||
out_bad:
|
||||
pr_err("error parsing dma-ranges property\n");
|
||||
of_node_put(np);
|
||||
return -EINVAL;
|
||||
}
|
||||
arch_initcall(bmips_init_dma_ranges);
|
||||
|
|
@ -0,0 +1,38 @@
|
|||
/*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License version 2 as published
|
||||
* by the Free Software Foundation.
|
||||
*
|
||||
* Copyright (C) 2014 Broadcom Corporation
|
||||
* Author: Kevin Cernekee <cernekee@gmail.com>
|
||||
*/
|
||||
|
||||
#include <linux/of.h>
|
||||
#include <linux/irqchip.h>
|
||||
|
||||
#include <asm/bmips.h>
|
||||
#include <asm/irq.h>
|
||||
#include <asm/irq_cpu.h>
|
||||
#include <asm/time.h>
|
||||
|
||||
unsigned int get_c0_compare_int(void)
|
||||
{
|
||||
return CP0_LEGACY_COMPARE_IRQ;
|
||||
}
|
||||
|
||||
void __init arch_init_irq(void)
|
||||
{
|
||||
struct device_node *dn;
|
||||
|
||||
/* Only the STB (bcm7038) controller supports SMP IRQ affinity */
|
||||
dn = of_find_compatible_node(NULL, NULL, "brcm,bcm7038-l1-intc");
|
||||
if (dn)
|
||||
of_node_put(dn);
|
||||
else
|
||||
bmips_tp1_irqs = 0;
|
||||
|
||||
irqchip_init();
|
||||
}
|
||||
|
||||
OF_DECLARE_2(irqchip, mips_cpu_intc, "mti,cpu-interrupt-controller",
|
||||
mips_cpu_irq_of_init);
|
||||
|
|
@ -0,0 +1,194 @@
|
|||
/*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*
|
||||
* Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
|
||||
* Copyright (C) 2014 Kevin Cernekee <cernekee@gmail.com>
|
||||
*/
|
||||
|
||||
#include <linux/init.h>
|
||||
#include <linux/bitops.h>
|
||||
#include <linux/bootmem.h>
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/ioport.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_fdt.h>
|
||||
#include <linux/of_platform.h>
|
||||
#include <linux/smp.h>
|
||||
#include <asm/addrspace.h>
|
||||
#include <asm/bmips.h>
|
||||
#include <asm/bootinfo.h>
|
||||
#include <asm/cpu-type.h>
|
||||
#include <asm/mipsregs.h>
|
||||
#include <asm/prom.h>
|
||||
#include <asm/smp-ops.h>
|
||||
#include <asm/time.h>
|
||||
#include <asm/traps.h>
|
||||
|
||||
#define RELO_NORMAL_VEC BIT(18)
|
||||
|
||||
#define REG_BCM6328_OTP ((void __iomem *)CKSEG1ADDR(0x1000062c))
|
||||
#define BCM6328_TP1_DISABLED BIT(9)
|
||||
|
||||
static const unsigned long kbase = VMLINUX_LOAD_ADDRESS & 0xfff00000;
|
||||
|
||||
struct bmips_quirk {
|
||||
const char *compatible;
|
||||
void (*quirk_fn)(void);
|
||||
};
|
||||
|
||||
static void kbase_setup(void)
|
||||
{
|
||||
__raw_writel(kbase | RELO_NORMAL_VEC,
|
||||
BMIPS_GET_CBR() + BMIPS_RELO_VECTOR_CONTROL_1);
|
||||
ebase = kbase;
|
||||
}
|
||||
|
||||
static void bcm3384_viper_quirks(void)
|
||||
{
|
||||
/*
|
||||
* Some experimental CM boxes are set up to let CM own the Viper TP0
|
||||
* and let Linux own TP1. This requires moving the kernel
|
||||
* load address to a non-conflicting region (e.g. via
|
||||
* CONFIG_PHYSICAL_START) and supplying an alternate DTB.
|
||||
* If we detect this condition, we need to move the MIPS exception
|
||||
* vectors up to an area that we own.
|
||||
*
|
||||
* This is distinct from the OTHER special case mentioned in
|
||||
* smp-bmips.c (boot on TP1, but enable SMP, then TP0 becomes our
|
||||
* logical CPU#1). For the Viper TP1 case, SMP is off limits.
|
||||
*
|
||||
* Also note that many BMIPS435x CPUs do not have a
|
||||
* BMIPS_RELO_VECTOR_CONTROL_1 register, so it isn't safe to just
|
||||
* write VMLINUX_LOAD_ADDRESS into that register on every SoC.
|
||||
*/
|
||||
board_ebase_setup = &kbase_setup;
|
||||
bmips_smp_enabled = 0;
|
||||
}
|
||||
|
||||
static void bcm63xx_fixup_cpu1(void)
|
||||
{
|
||||
/*
|
||||
* The bootloader has set up the CPU1 reset vector at
|
||||
* 0xa000_0200.
|
||||
* This conflicts with the special interrupt vector (IV).
|
||||
* The bootloader has also set up CPU1 to respond to the wrong
|
||||
* IPI interrupt.
|
||||
* Here we will start up CPU1 in the background and ask it to
|
||||
* reconfigure itself then go back to sleep.
|
||||
*/
|
||||
memcpy((void *)0xa0000200, &bmips_smp_movevec, 0x20);
|
||||
__sync();
|
||||
set_c0_cause(C_SW0);
|
||||
cpumask_set_cpu(1, &bmips_booted_mask);
|
||||
}
|
||||
|
||||
static void bcm6328_quirks(void)
|
||||
{
|
||||
/* Check CPU1 status in OTP (it is usually disabled) */
|
||||
if (__raw_readl(REG_BCM6328_OTP) & BCM6328_TP1_DISABLED)
|
||||
bmips_smp_enabled = 0;
|
||||
else
|
||||
bcm63xx_fixup_cpu1();
|
||||
}
|
||||
|
||||
static void bcm6368_quirks(void)
|
||||
{
|
||||
bcm63xx_fixup_cpu1();
|
||||
}
|
||||
|
||||
static const struct bmips_quirk bmips_quirk_list[] = {
|
||||
{ "brcm,bcm3384-viper", &bcm3384_viper_quirks },
|
||||
{ "brcm,bcm33843-viper", &bcm3384_viper_quirks },
|
||||
{ "brcm,bcm6328", &bcm6328_quirks },
|
||||
{ "brcm,bcm6368", &bcm6368_quirks },
|
||||
{ },
|
||||
};
|
||||
|
||||
void __init prom_init(void)
|
||||
{
|
||||
register_bmips_smp_ops();
|
||||
}
|
||||
|
||||
void __init prom_free_prom_memory(void)
|
||||
{
|
||||
}
|
||||
|
||||
const char *get_system_type(void)
|
||||
{
|
||||
return "Generic BMIPS kernel";
|
||||
}
|
||||
|
||||
void __init plat_time_init(void)
|
||||
{
|
||||
struct device_node *np;
|
||||
u32 freq;
|
||||
|
||||
np = of_find_node_by_name(NULL, "cpus");
|
||||
if (!np)
|
||||
panic("missing 'cpus' DT node");
|
||||
if (of_property_read_u32(np, "mips-hpt-frequency", &freq) < 0)
|
||||
panic("missing 'mips-hpt-frequency' property");
|
||||
of_node_put(np);
|
||||
|
||||
mips_hpt_frequency = freq;
|
||||
}
|
||||
|
||||
void __init plat_mem_setup(void)
|
||||
{
|
||||
void *dtb;
|
||||
const struct bmips_quirk *q;
|
||||
|
||||
set_io_port_base(0);
|
||||
ioport_resource.start = 0;
|
||||
ioport_resource.end = ~0;
|
||||
|
||||
/* intended to somewhat resemble ARM; see Documentation/arm/Booting */
|
||||
if (fw_arg0 == 0 && fw_arg1 == 0xffffffff)
|
||||
dtb = phys_to_virt(fw_arg2);
|
||||
else if (__dtb_start != __dtb_end)
|
||||
dtb = (void *)__dtb_start;
|
||||
else
|
||||
panic("no dtb found");
|
||||
|
||||
__dt_setup_arch(dtb);
|
||||
strlcpy(arcs_cmdline, boot_command_line, COMMAND_LINE_SIZE);
|
||||
|
||||
for (q = bmips_quirk_list; q->quirk_fn; q++) {
|
||||
if (of_flat_dt_is_compatible(of_get_flat_dt_root(),
|
||||
q->compatible)) {
|
||||
q->quirk_fn();
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void __init device_tree_init(void)
|
||||
{
|
||||
struct device_node *np;
|
||||
|
||||
unflatten_and_copy_device_tree();
|
||||
|
||||
/* Disable SMP boot unless both CPUs are listed in DT and !disabled */
|
||||
np = of_find_node_by_name(NULL, "cpus");
|
||||
if (np && of_get_available_child_count(np) <= 1)
|
||||
bmips_smp_enabled = 0;
|
||||
of_node_put(np);
|
||||
}
|
||||
|
||||
int __init plat_of_setup(void)
|
||||
{
|
||||
return __dt_register_buses("simple-bus", NULL);
|
||||
}
|
||||
|
||||
arch_initcall(plat_of_setup);
|
||||
|
||||
static int __init plat_dev_init(void)
|
||||
{
|
||||
of_clk_init(NULL);
|
||||
return 0;
|
||||
}
|
||||
|
||||
device_initcall(plat_dev_init);
|
||||
|
|
@ -12,6 +12,8 @@
|
|||
# Author: Wu Zhangjin <wuzhangjin@gmail.com>
|
||||
#
|
||||
|
||||
include $(srctree)/arch/mips/Kbuild.platforms
|
||||
|
||||
# set the default size of the mallocing area for decompressing
|
||||
BOOT_HEAP_SIZE := 0x400000
|
||||
|
||||
|
|
@ -30,9 +32,10 @@ KBUILD_AFLAGS := $(LINUXINCLUDE) $(KBUILD_AFLAGS) -D__ASSEMBLY__ \
|
|||
targets := head.o decompress.o string.o dbg.o uart-16550.o uart-alchemy.o
|
||||
|
||||
# decompressor objects (linked with vmlinuz)
|
||||
vmlinuzobjs-y := $(obj)/head.o $(obj)/decompress.o $(obj)/string.o $(obj)/dbg.o
|
||||
vmlinuzobjs-y := $(obj)/head.o $(obj)/decompress.o $(obj)/string.o
|
||||
|
||||
ifdef CONFIG_DEBUG_ZBOOT
|
||||
vmlinuzobjs-$(CONFIG_DEBUG_ZBOOT) += $(obj)/dbg.o
|
||||
vmlinuzobjs-$(CONFIG_SYS_SUPPORTS_ZBOOT_UART16550) += $(obj)/uart-16550.o
|
||||
vmlinuzobjs-$(CONFIG_MIPS_ALCHEMY) += $(obj)/uart-alchemy.o
|
||||
endif
|
||||
|
|
@ -66,8 +69,8 @@ $(obj)/piggy.o: $(obj)/dummy.o $(obj)/vmlinux.bin.z FORCE
|
|||
# Calculate the load address of the compressed kernel image
|
||||
hostprogs-y := calc_vmlinuz_load_addr
|
||||
|
||||
ifeq ($(CONFIG_MACH_JZ4740),y)
|
||||
VMLINUZ_LOAD_ADDRESS := 0x80600000
|
||||
ifneq ($(zload-y),)
|
||||
VMLINUZ_LOAD_ADDRESS := $(zload-y)
|
||||
else
|
||||
VMLINUZ_LOAD_ADDRESS = $(shell $(obj)/calc_vmlinuz_load_addr \
|
||||
$(obj)/vmlinux.bin $(VMLINUX_LOAD_ADDRESS))
|
||||
|
|
|
|||
|
|
@ -28,8 +28,13 @@ unsigned long free_mem_end_ptr;
|
|||
extern unsigned char __image_begin, __image_end;
|
||||
|
||||
/* debug interfaces */
|
||||
#ifdef CONFIG_DEBUG_ZBOOT
|
||||
extern void puts(const char *s);
|
||||
extern void puthex(unsigned long long val);
|
||||
#else
|
||||
#define puts(s) do {} while (0)
|
||||
#define puthex(val) do {} while (0)
|
||||
#endif
|
||||
|
||||
void error(char *x)
|
||||
{
|
||||
|
|
|
|||
|
|
@ -1,21 +1,12 @@
|
|||
dtb-$(CONFIG_BCM3384) += bcm93384wvg.dtb
|
||||
dtb-$(CONFIG_CAVIUM_OCTEON_SOC) += octeon_3xxx.dtb octeon_68xx.dtb
|
||||
dtb-$(CONFIG_DT_EASY50712) += easy50712.dtb
|
||||
dtb-$(CONFIG_DT_XLP_EVP) += xlp_evp.dtb
|
||||
dtb-$(CONFIG_DT_XLP_SVP) += xlp_svp.dtb
|
||||
dtb-$(CONFIG_DT_XLP_FVP) += xlp_fvp.dtb
|
||||
dtb-$(CONFIG_DT_XLP_GVP) += xlp_gvp.dtb
|
||||
dtb-$(CONFIG_DTB_RT2880_EVAL) += rt2880_eval.dtb
|
||||
dtb-$(CONFIG_DTB_RT305X_EVAL) += rt3052_eval.dtb
|
||||
dtb-$(CONFIG_DTB_RT3883_EVAL) += rt3883_eval.dtb
|
||||
dtb-$(CONFIG_DTB_MT7620A_EVAL) += mt7620a_eval.dtb
|
||||
dtb-$(CONFIG_MIPS_SEAD3) += sead3.dtb
|
||||
dts-dirs += brcm
|
||||
dts-dirs += cavium-octeon
|
||||
dts-dirs += lantiq
|
||||
dts-dirs += mti
|
||||
dts-dirs += netlogic
|
||||
dts-dirs += ralink
|
||||
|
||||
obj-y += $(patsubst %.dtb, %.dtb.o, $(dtb-y))
|
||||
obj-y := $(addsuffix /, $(dts-dirs))
|
||||
|
||||
targets += dtbs
|
||||
targets += $(dtb-y)
|
||||
|
||||
dtbs: $(addprefix $(obj)/, $(dtb-y))
|
||||
|
||||
clean-files += *.dtb *.dtb.S
|
||||
always := $(dtb-y)
|
||||
subdir-y := $(dts-dirs)
|
||||
clean-files := *.dtb *.dtb.S
|
||||
|
|
|
|||
|
|
@ -1,109 +0,0 @@
|
|||
/ {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "brcm,bcm3384", "brcm,bcm33843";
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
/* On BMIPS5000 this is 1/8th of the CPU core clock */
|
||||
mips-hpt-frequency = <100000000>;
|
||||
|
||||
cpu@0 {
|
||||
compatible = "brcm,bmips5000";
|
||||
device_type = "cpu";
|
||||
reg = <0>;
|
||||
};
|
||||
|
||||
cpu@1 {
|
||||
compatible = "brcm,bmips5000";
|
||||
device_type = "cpu";
|
||||
reg = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
clocks {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
periph_clk: periph_clk@0 {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <54000000>;
|
||||
};
|
||||
};
|
||||
|
||||
aliases {
|
||||
uart0 = &uart0;
|
||||
};
|
||||
|
||||
cpu_intc: cpu_intc@0 {
|
||||
#address-cells = <0>;
|
||||
compatible = "mti,cpu-interrupt-controller";
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
};
|
||||
|
||||
periph_intc: periph_intc@14e00038 {
|
||||
compatible = "brcm,bcm3384-intc";
|
||||
reg = <0x14e00038 0x8 0x14e00340 0x8>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
|
||||
interrupt-parent = <&cpu_intc>;
|
||||
interrupts = <4>;
|
||||
};
|
||||
|
||||
zmips_intc: zmips_intc@104b0060 {
|
||||
compatible = "brcm,bcm3384-intc";
|
||||
reg = <0x104b0060 0x8>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
|
||||
interrupt-parent = <&periph_intc>;
|
||||
interrupts = <29>;
|
||||
};
|
||||
|
||||
iop_intc: iop_intc@14e00058 {
|
||||
compatible = "brcm,bcm3384-intc";
|
||||
reg = <0x14e00058 0x8>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
|
||||
interrupt-parent = <&cpu_intc>;
|
||||
interrupts = <6>;
|
||||
};
|
||||
|
||||
uart0: serial@14e00520 {
|
||||
compatible = "brcm,bcm6345-uart";
|
||||
reg = <0x14e00520 0x18>;
|
||||
interrupt-parent = <&periph_intc>;
|
||||
interrupts = <2>;
|
||||
clocks = <&periph_clk>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ehci0: usb@15400300 {
|
||||
compatible = "brcm,bcm3384-ehci", "generic-ehci";
|
||||
reg = <0x15400300 0x100>;
|
||||
big-endian;
|
||||
interrupt-parent = <&periph_intc>;
|
||||
interrupts = <41>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ohci0: usb@15400400 {
|
||||
compatible = "brcm,bcm3384-ohci", "generic-ohci";
|
||||
reg = <0x15400400 0x100>;
|
||||
big-endian;
|
||||
no-big-frame-no;
|
||||
interrupt-parent = <&periph_intc>;
|
||||
interrupts = <40>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,19 @@
|
|||
dtb-$(CONFIG_DT_BCM93384WVG) += bcm93384wvg.dtb
|
||||
dtb-$(CONFIG_DT_BCM93384WVG_VIPER) += bcm93384wvg_viper.dtb
|
||||
dtb-$(CONFIG_DT_BCM96368MVWG) += bcm96368mvwg.dtb
|
||||
dtb-$(CONFIG_DT_BCM9EJTAGPRB) += bcm9ejtagprb.dtb
|
||||
dtb-$(CONFIG_DT_BCM97125CBMB) += bcm97125cbmb.dtb
|
||||
dtb-$(CONFIG_DT_BCM97346DBSMB) += bcm97346dbsmb.dtb
|
||||
dtb-$(CONFIG_DT_BCM97358SVMB) += bcm97358svmb.dtb
|
||||
dtb-$(CONFIG_DT_BCM97360SVMB) += bcm97360svmb.dtb
|
||||
dtb-$(CONFIG_DT_BCM97362SVMB) += bcm97362svmb.dtb
|
||||
dtb-$(CONFIG_DT_BCM97420C) += bcm97420c.dtb
|
||||
dtb-$(CONFIG_DT_BCM97425SVMB) += bcm97425svmb.dtb
|
||||
|
||||
obj-y += $(patsubst %.dtb, %.dtb.o, $(dtb-y))
|
||||
|
||||
# Force kbuild to make empty built-in.o if necessary
|
||||
obj- += dummy.o
|
||||
|
||||
always := $(dtb-y)
|
||||
clean-files := *.dtb *.dtb.S
|
||||
|
|
@ -0,0 +1,108 @@
|
|||
/ {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "brcm,bcm3384-viper", "brcm,bcm33843-viper";
|
||||
|
||||
memory@0 {
|
||||
device_type = "memory";
|
||||
|
||||
/* Typical ranges. The bootloader should fill these in. */
|
||||
reg = <0x06000000 0x02000000>,
|
||||
<0x0e000000 0x02000000>;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
/* 1/2 of the CPU core clock (standard MIPS behavior) */
|
||||
mips-hpt-frequency = <300000000>;
|
||||
|
||||
cpu@0 {
|
||||
compatible = "brcm,bmips4350";
|
||||
device_type = "cpu";
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
cpu_intc: cpu_intc {
|
||||
#address-cells = <0>;
|
||||
compatible = "mti,cpu-interrupt-controller";
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
};
|
||||
|
||||
clocks {
|
||||
periph_clk: periph_clk {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <54000000>;
|
||||
};
|
||||
};
|
||||
|
||||
aliases {
|
||||
uart0 = &uart0;
|
||||
};
|
||||
|
||||
ubus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
compatible = "brcm,ubus", "simple-bus";
|
||||
ranges;
|
||||
/* No dma-ranges on Viper. */
|
||||
|
||||
periph_intc: periph_intc@14e00048 {
|
||||
compatible = "brcm,bcm3380-l2-intc";
|
||||
reg = <0x14e00048 0x4 0x14e0004c 0x4>,
|
||||
<0x14e00350 0x4 0x14e00354 0x4>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
|
||||
interrupt-parent = <&cpu_intc>;
|
||||
interrupts = <4>;
|
||||
};
|
||||
|
||||
cmips_intc: cmips_intc@151f8048 {
|
||||
compatible = "brcm,bcm3380-l2-intc";
|
||||
reg = <0x151f8048 0x4 0x151f804c 0x4>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
|
||||
interrupt-parent = <&periph_intc>;
|
||||
interrupts = <30>;
|
||||
brcm,int-map-mask = <0xffffffff>;
|
||||
};
|
||||
|
||||
uart0: serial@14e00520 {
|
||||
compatible = "brcm,bcm6345-uart";
|
||||
reg = <0x14e00520 0x18>;
|
||||
interrupt-parent = <&periph_intc>;
|
||||
interrupts = <2>;
|
||||
clocks = <&periph_clk>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ehci0: usb@15400300 {
|
||||
compatible = "brcm,bcm3384-ehci", "generic-ehci";
|
||||
reg = <0x15400300 0x100>;
|
||||
big-endian;
|
||||
interrupt-parent = <&periph_intc>;
|
||||
interrupts = <41>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ohci0: usb@15400400 {
|
||||
compatible = "brcm,bcm3384-ohci", "generic-ohci";
|
||||
reg = <0x15400400 0x100>;
|
||||
big-endian;
|
||||
no-big-frame-no;
|
||||
interrupt-parent = <&periph_intc>;
|
||||
interrupts = <40>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,126 @@
|
|||
/ {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "brcm,bcm3384", "brcm,bcm33843";
|
||||
|
||||
memory@0 {
|
||||
device_type = "memory";
|
||||
|
||||
/* Typical range. The bootloader should fill this in. */
|
||||
reg = <0x0 0x08000000>;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
/* On BMIPS5000 this is 1/8th of the CPU core clock */
|
||||
mips-hpt-frequency = <100000000>;
|
||||
|
||||
cpu@0 {
|
||||
compatible = "brcm,bmips5000";
|
||||
device_type = "cpu";
|
||||
reg = <0>;
|
||||
};
|
||||
|
||||
cpu@1 {
|
||||
compatible = "brcm,bmips5000";
|
||||
device_type = "cpu";
|
||||
reg = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
cpu_intc: cpu_intc {
|
||||
#address-cells = <0>;
|
||||
compatible = "mti,cpu-interrupt-controller";
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
};
|
||||
|
||||
clocks {
|
||||
periph_clk: periph_clk {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <54000000>;
|
||||
};
|
||||
};
|
||||
|
||||
aliases {
|
||||
uart0 = &uart0;
|
||||
};
|
||||
|
||||
ubus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
compatible = "brcm,ubus", "simple-bus";
|
||||
ranges;
|
||||
dma-ranges = <0x00000000 0x08000000 0x08000000>,
|
||||
<0x08000000 0x00000000 0x08000000>;
|
||||
|
||||
periph_intc: periph_intc@14e00038 {
|
||||
compatible = "brcm,bcm3380-l2-intc";
|
||||
reg = <0x14e00038 0x4 0x14e0003c 0x4>,
|
||||
<0x14e00340 0x4 0x14e00344 0x4>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
|
||||
interrupt-parent = <&cpu_intc>;
|
||||
interrupts = <4>;
|
||||
};
|
||||
|
||||
zmips_intc: zmips_intc@104b0060 {
|
||||
compatible = "brcm,bcm3380-l2-intc";
|
||||
reg = <0x104b0060 0x4 0x104b0064 0x4>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
|
||||
interrupt-parent = <&periph_intc>;
|
||||
interrupts = <29>;
|
||||
brcm,int-map-mask = <0xffffffff>;
|
||||
};
|
||||
|
||||
iop_intc: iop_intc@14e00058 {
|
||||
compatible = "brcm,bcm3380-l2-intc";
|
||||
reg = <0x14e00058 0x4 0x14e0005c 0x4>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
|
||||
interrupt-parent = <&cpu_intc>;
|
||||
interrupts = <6>;
|
||||
brcm,int-map-mask = <0xffffffff>;
|
||||
};
|
||||
|
||||
uart0: serial@14e00520 {
|
||||
compatible = "brcm,bcm6345-uart";
|
||||
reg = <0x14e00520 0x18>;
|
||||
interrupt-parent = <&periph_intc>;
|
||||
interrupts = <2>;
|
||||
clocks = <&periph_clk>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ehci0: usb@15400300 {
|
||||
compatible = "brcm,bcm3384-ehci", "generic-ehci";
|
||||
reg = <0x15400300 0x100>;
|
||||
big-endian;
|
||||
interrupt-parent = <&periph_intc>;
|
||||
interrupts = <41>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ohci0: usb@15400400 {
|
||||
compatible = "brcm,bcm3384-ohci", "generic-ohci";
|
||||
reg = <0x15400400 0x100>;
|
||||
big-endian;
|
||||
no-big-frame-no;
|
||||
interrupt-parent = <&periph_intc>;
|
||||
interrupts = <40>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,86 @@
|
|||
/ {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "brcm,bcm6328";
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
mips-hpt-frequency = <160000000>;
|
||||
|
||||
cpu@0 {
|
||||
compatible = "brcm,bmips4350";
|
||||
device_type = "cpu";
|
||||
reg = <0>;
|
||||
};
|
||||
|
||||
cpu@1 {
|
||||
compatible = "brcm,bmips4350";
|
||||
device_type = "cpu";
|
||||
reg = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
clocks {
|
||||
periph_clk: periph_clk {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <50000000>;
|
||||
};
|
||||
};
|
||||
|
||||
aliases {
|
||||
uart0 = &uart0;
|
||||
};
|
||||
|
||||
cpu_intc: cpu_intc {
|
||||
#address-cells = <0>;
|
||||
compatible = "mti,cpu-interrupt-controller";
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
};
|
||||
|
||||
ubus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
compatible = "simple-bus";
|
||||
ranges;
|
||||
|
||||
periph_intc: periph_intc@10000020 {
|
||||
compatible = "brcm,bcm3380-l2-intc";
|
||||
reg = <0x10000024 0x4 0x1000002c 0x4>,
|
||||
<0x10000020 0x4 0x10000028 0x4>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
|
||||
interrupt-parent = <&cpu_intc>;
|
||||
interrupts = <2>;
|
||||
};
|
||||
|
||||
uart0: serial@10000100 {
|
||||
compatible = "brcm,bcm6345-uart";
|
||||
reg = <0x10000100 0x18>;
|
||||
interrupt-parent = <&periph_intc>;
|
||||
interrupts = <28>;
|
||||
clocks = <&periph_clk>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
timer: timer@10000040 {
|
||||
compatible = "syscon";
|
||||
reg = <0x10000040 0x2c>;
|
||||
little-endian;
|
||||
};
|
||||
|
||||
reboot {
|
||||
compatible = "syscon-reboot";
|
||||
regmap = <&timer>;
|
||||
offset = <0x28>;
|
||||
mask = <0x1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,93 @@
|
|||
/ {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "brcm,bcm6368";
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
mips-hpt-frequency = <200000000>;
|
||||
|
||||
cpu@0 {
|
||||
compatible = "brcm,bmips4350";
|
||||
device_type = "cpu";
|
||||
reg = <0>;
|
||||
};
|
||||
|
||||
cpu@1 {
|
||||
compatible = "brcm,bmips4350";
|
||||
device_type = "cpu";
|
||||
reg = <1>;
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
clocks {
|
||||
periph_clk: periph_clk {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <50000000>;
|
||||
};
|
||||
};
|
||||
|
||||
aliases {
|
||||
uart0 = &uart0;
|
||||
};
|
||||
|
||||
cpu_intc: cpu_intc {
|
||||
#address-cells = <0>;
|
||||
compatible = "mti,cpu-interrupt-controller";
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
};
|
||||
|
||||
ubus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
compatible = "simple-bus";
|
||||
ranges;
|
||||
|
||||
periph_intc: periph_intc@10000020 {
|
||||
compatible = "brcm,bcm3380-l2-intc";
|
||||
reg = <0x10000024 0x4 0x1000002c 0x4>,
|
||||
<0x10000020 0x4 0x10000028 0x4>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
|
||||
interrupt-parent = <&cpu_intc>;
|
||||
interrupts = <2>;
|
||||
};
|
||||
|
||||
uart0: serial@10000100 {
|
||||
compatible = "brcm,bcm6345-uart";
|
||||
reg = <0x10000100 0x18>;
|
||||
interrupt-parent = <&periph_intc>;
|
||||
interrupts = <2>;
|
||||
clocks = <&periph_clk>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ehci0: usb@10001500 {
|
||||
compatible = "brcm,bcm6368-ehci", "generic-ehci";
|
||||
reg = <0x10001500 0x100>;
|
||||
big-endian;
|
||||
interrupt-parent = <&periph_intc>;
|
||||
interrupts = <7>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ohci0: usb@10001600 {
|
||||
compatible = "brcm,bcm6368-ohci", "generic-ohci";
|
||||
reg = <0x10001600 0x100>;
|
||||
big-endian;
|
||||
no-big-frame-no;
|
||||
interrupt-parent = <&periph_intc>;
|
||||
interrupts = <5>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,139 @@
|
|||
/ {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "brcm,bcm7125";
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
mips-hpt-frequency = <202500000>;
|
||||
|
||||
cpu@0 {
|
||||
compatible = "brcm,bmips4380";
|
||||
device_type = "cpu";
|
||||
reg = <0>;
|
||||
};
|
||||
|
||||
cpu@1 {
|
||||
compatible = "brcm,bmips4380";
|
||||
device_type = "cpu";
|
||||
reg = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
aliases {
|
||||
uart0 = &uart0;
|
||||
};
|
||||
|
||||
cpu_intc: cpu_intc {
|
||||
#address-cells = <0>;
|
||||
compatible = "mti,cpu-interrupt-controller";
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
};
|
||||
|
||||
clocks {
|
||||
uart_clk: uart_clk {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <81000000>;
|
||||
};
|
||||
};
|
||||
|
||||
rdb {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
compatible = "simple-bus";
|
||||
ranges = <0 0x10000000 0x01000000>;
|
||||
|
||||
periph_intc: periph_intc@441400 {
|
||||
compatible = "brcm,bcm7038-l1-intc";
|
||||
reg = <0x441400 0x30>, <0x441600 0x30>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
|
||||
interrupt-parent = <&cpu_intc>;
|
||||
interrupts = <2>, <3>;
|
||||
};
|
||||
|
||||
sun_l2_intc: sun_l2_intc@401800 {
|
||||
compatible = "brcm,l2-intc";
|
||||
reg = <0x401800 0x30>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-parent = <&periph_intc>;
|
||||
interrupts = <23>;
|
||||
};
|
||||
|
||||
gisb-arb@400000 {
|
||||
compatible = "brcm,bcm7400-gisb-arb";
|
||||
reg = <0x400000 0xdc>;
|
||||
native-endian;
|
||||
interrupt-parent = <&sun_l2_intc>;
|
||||
interrupts = <0>, <2>;
|
||||
brcm,gisb-arb-master-mask = <0x2f7>;
|
||||
brcm,gisb-arb-master-names = "ssp_0", "cpu_0", "pci_0",
|
||||
"bsp_0", "rdc_0", "rptd_0",
|
||||
"avd_0", "jtag_0";
|
||||
};
|
||||
|
||||
upg_irq0_intc: upg_irq0_intc@406780 {
|
||||
compatible = "brcm,bcm7120-l2-intc";
|
||||
reg = <0x406780 0x8>;
|
||||
|
||||
brcm,int-map-mask = <0x44>;
|
||||
brcm,int-fwd-mask = <0x70000>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
|
||||
interrupt-parent = <&periph_intc>;
|
||||
interrupts = <18>;
|
||||
};
|
||||
|
||||
sun_top_ctrl: syscon@404000 {
|
||||
compatible = "brcm,bcm7125-sun-top-ctrl", "syscon";
|
||||
reg = <0x404000 0x60c>;
|
||||
little-endian;
|
||||
};
|
||||
|
||||
reboot {
|
||||
compatible = "brcm,bcm7038-reboot";
|
||||
syscon = <&sun_top_ctrl 0x8 0x14>;
|
||||
};
|
||||
|
||||
uart0: serial@406b00 {
|
||||
compatible = "ns16550a";
|
||||
reg = <0x406b00 0x20>;
|
||||
reg-io-width = <0x4>;
|
||||
reg-shift = <0x2>;
|
||||
native-endian;
|
||||
interrupt-parent = <&periph_intc>;
|
||||
interrupts = <21>;
|
||||
clocks = <&uart_clk>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ehci0: usb@488300 {
|
||||
compatible = "brcm,bcm7125-ehci", "generic-ehci";
|
||||
reg = <0x488300 0x100>;
|
||||
native-endian;
|
||||
interrupt-parent = <&periph_intc>;
|
||||
interrupts = <60>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ohci0: usb@488400 {
|
||||
compatible = "brcm,bcm7125-ohci", "generic-ohci";
|
||||
reg = <0x488400 0x100>;
|
||||
native-endian;
|
||||
interrupt-parent = <&periph_intc>;
|
||||
interrupts = <61>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,224 @@
|
|||
/ {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "brcm,bcm7346";
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
mips-hpt-frequency = <163125000>;
|
||||
|
||||
cpu@0 {
|
||||
compatible = "brcm,bmips5000";
|
||||
device_type = "cpu";
|
||||
reg = <0>;
|
||||
};
|
||||
|
||||
cpu@1 {
|
||||
compatible = "brcm,bmips5000";
|
||||
device_type = "cpu";
|
||||
reg = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
aliases {
|
||||
uart0 = &uart0;
|
||||
};
|
||||
|
||||
cpu_intc: cpu_intc {
|
||||
#address-cells = <0>;
|
||||
compatible = "mti,cpu-interrupt-controller";
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
};
|
||||
|
||||
clocks {
|
||||
uart_clk: uart_clk {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <81000000>;
|
||||
};
|
||||
};
|
||||
|
||||
rdb {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
compatible = "simple-bus";
|
||||
ranges = <0 0x10000000 0x01000000>;
|
||||
|
||||
periph_intc: periph_intc@411400 {
|
||||
compatible = "brcm,bcm7038-l1-intc";
|
||||
reg = <0x411400 0x30>, <0x411600 0x30>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
|
||||
interrupt-parent = <&cpu_intc>;
|
||||
interrupts = <2>, <3>;
|
||||
};
|
||||
|
||||
sun_l2_intc: sun_l2_intc@403000 {
|
||||
compatible = "brcm,l2-intc";
|
||||
reg = <0x403000 0x30>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-parent = <&periph_intc>;
|
||||
interrupts = <51>;
|
||||
};
|
||||
|
||||
gisb-arb@400000 {
|
||||
compatible = "brcm,bcm7400-gisb-arb";
|
||||
reg = <0x400000 0xdc>;
|
||||
native-endian;
|
||||
interrupt-parent = <&sun_l2_intc>;
|
||||
interrupts = <0>, <2>;
|
||||
brcm,gisb-arb-master-mask = <0x673>;
|
||||
brcm,gisb-arb-master-names = "ssp_0", "cpu_0", "bsp_0",
|
||||
"rdc_0", "raaga_0",
|
||||
"jtag_0", "svd_0";
|
||||
};
|
||||
|
||||
upg_irq0_intc: upg_irq0_intc@406780 {
|
||||
compatible = "brcm,bcm7120-l2-intc";
|
||||
reg = <0x406780 0x8>;
|
||||
|
||||
brcm,int-map-mask = <0x44>;
|
||||
brcm,int-fwd-mask = <0x70000>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
|
||||
interrupt-parent = <&periph_intc>;
|
||||
interrupts = <59>;
|
||||
};
|
||||
|
||||
sun_top_ctrl: syscon@404000 {
|
||||
compatible = "brcm,bcm7346-sun-top-ctrl", "syscon";
|
||||
reg = <0x404000 0x51c>;
|
||||
little-endian;
|
||||
};
|
||||
|
||||
reboot {
|
||||
compatible = "brcm,brcmstb-reboot";
|
||||
syscon = <&sun_top_ctrl 0x304 0x308>;
|
||||
};
|
||||
|
||||
uart0: serial@406900 {
|
||||
compatible = "ns16550a";
|
||||
reg = <0x406900 0x20>;
|
||||
reg-io-width = <0x4>;
|
||||
reg-shift = <0x2>;
|
||||
native-endian;
|
||||
interrupt-parent = <&periph_intc>;
|
||||
interrupts = <64>;
|
||||
clocks = <&uart_clk>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
enet0: ethernet@430000 {
|
||||
phy-mode = "internal";
|
||||
phy-handle = <&phy1>;
|
||||
mac-address = [ 00 10 18 36 23 1a ];
|
||||
compatible = "brcm,genet-v2";
|
||||
#address-cells = <0x1>;
|
||||
#size-cells = <0x1>;
|
||||
reg = <0x430000 0x4c8c>;
|
||||
interrupts = <24>, <25>;
|
||||
interrupt-parent = <&periph_intc>;
|
||||
status = "disabled";
|
||||
|
||||
mdio@e14 {
|
||||
compatible = "brcm,genet-mdio-v2";
|
||||
#address-cells = <0x1>;
|
||||
#size-cells = <0x0>;
|
||||
reg = <0xe14 0x8>;
|
||||
|
||||
phy1: ethernet-phy@1 {
|
||||
max-speed = <100>;
|
||||
reg = <0x1>;
|
||||
compatible = "brcm,40nm-ephy",
|
||||
"ethernet-phy-ieee802.3-c22";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
ehci0: usb@480300 {
|
||||
compatible = "brcm,bcm7346-ehci", "generic-ehci";
|
||||
reg = <0x480300 0x100>;
|
||||
native-endian;
|
||||
interrupt-parent = <&periph_intc>;
|
||||
interrupts = <68>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ohci0: usb@480400 {
|
||||
compatible = "brcm,bcm7346-ohci", "generic-ohci";
|
||||
reg = <0x480400 0x100>;
|
||||
native-endian;
|
||||
no-big-frame-no;
|
||||
interrupt-parent = <&periph_intc>;
|
||||
interrupts = <70>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ehci1: usb@480500 {
|
||||
compatible = "brcm,bcm7346-ehci", "generic-ehci";
|
||||
reg = <0x480500 0x100>;
|
||||
native-endian;
|
||||
interrupt-parent = <&periph_intc>;
|
||||
interrupts = <69>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ohci1: usb@480600 {
|
||||
compatible = "brcm,bcm7346-ohci", "generic-ohci";
|
||||
reg = <0x480600 0x100>;
|
||||
native-endian;
|
||||
no-big-frame-no;
|
||||
interrupt-parent = <&periph_intc>;
|
||||
interrupts = <71>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ehci2: usb@490300 {
|
||||
compatible = "brcm,bcm7346-ehci", "generic-ehci";
|
||||
reg = <0x490300 0x100>;
|
||||
native-endian;
|
||||
interrupt-parent = <&periph_intc>;
|
||||
interrupts = <73>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ohci2: usb@490400 {
|
||||
compatible = "brcm,bcm7346-ohci", "generic-ohci";
|
||||
reg = <0x490400 0x100>;
|
||||
native-endian;
|
||||
no-big-frame-no;
|
||||
interrupt-parent = <&periph_intc>;
|
||||
interrupts = <75>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ehci3: usb@490500 {
|
||||
compatible = "brcm,bcm7346-ehci", "generic-ehci";
|
||||
reg = <0x490500 0x100>;
|
||||
native-endian;
|
||||
interrupt-parent = <&periph_intc>;
|
||||
interrupts = <74>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ohci3: usb@490600 {
|
||||
compatible = "brcm,bcm7346-ohci", "generic-ohci";
|
||||
reg = <0x490600 0x100>;
|
||||
native-endian;
|
||||
no-big-frame-no;
|
||||
interrupt-parent = <&periph_intc>;
|
||||
interrupts = <76>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,161 @@
|
|||
/ {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "brcm,bcm7358";
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
mips-hpt-frequency = <375000000>;
|
||||
|
||||
cpu@0 {
|
||||
compatible = "brcm,bmips3300";
|
||||
device_type = "cpu";
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
aliases {
|
||||
uart0 = &uart0;
|
||||
};
|
||||
|
||||
cpu_intc: cpu_intc {
|
||||
#address-cells = <0>;
|
||||
compatible = "mti,cpu-interrupt-controller";
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
};
|
||||
|
||||
clocks {
|
||||
uart_clk: uart_clk {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <81000000>;
|
||||
};
|
||||
};
|
||||
|
||||
rdb {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
compatible = "simple-bus";
|
||||
ranges = <0 0x10000000 0x01000000>;
|
||||
|
||||
periph_intc: periph_intc@411400 {
|
||||
compatible = "brcm,bcm7038-l1-intc";
|
||||
reg = <0x411400 0x30>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
|
||||
interrupt-parent = <&cpu_intc>;
|
||||
interrupts = <2>;
|
||||
};
|
||||
|
||||
sun_l2_intc: sun_l2_intc@403000 {
|
||||
compatible = "brcm,l2-intc";
|
||||
reg = <0x403000 0x30>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-parent = <&periph_intc>;
|
||||
interrupts = <48>;
|
||||
};
|
||||
|
||||
gisb-arb@400000 {
|
||||
compatible = "brcm,bcm7400-gisb-arb";
|
||||
reg = <0x400000 0xdc>;
|
||||
native-endian;
|
||||
interrupt-parent = <&sun_l2_intc>;
|
||||
interrupts = <0>, <2>;
|
||||
brcm,gisb-arb-master-mask = <0x2f3>;
|
||||
brcm,gisb-arb-master-names = "ssp_0", "cpu_0", "bsp_0",
|
||||
"rdc_0", "raaga_0",
|
||||
"avd_0", "jtag_0";
|
||||
};
|
||||
|
||||
upg_irq0_intc: upg_irq0_intc@406600 {
|
||||
compatible = "brcm,bcm7120-l2-intc";
|
||||
reg = <0x406600 0x8>;
|
||||
|
||||
brcm,int-map-mask = <0x44>;
|
||||
brcm,int-fwd-mask = <0x70000>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
|
||||
interrupt-parent = <&periph_intc>;
|
||||
interrupts = <56>;
|
||||
};
|
||||
|
||||
sun_top_ctrl: syscon@404000 {
|
||||
compatible = "brcm,bcm7358-sun-top-ctrl", "syscon";
|
||||
reg = <0x404000 0x51c>;
|
||||
little-endian;
|
||||
};
|
||||
|
||||
reboot {
|
||||
compatible = "brcm,brcmstb-reboot";
|
||||
syscon = <&sun_top_ctrl 0x304 0x308>;
|
||||
};
|
||||
|
||||
uart0: serial@406800 {
|
||||
compatible = "ns16550a";
|
||||
reg = <0x406800 0x20>;
|
||||
reg-io-width = <0x4>;
|
||||
reg-shift = <0x2>;
|
||||
native-endian;
|
||||
interrupt-parent = <&periph_intc>;
|
||||
interrupts = <61>;
|
||||
clocks = <&uart_clk>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
enet0: ethernet@430000 {
|
||||
phy-mode = "internal";
|
||||
phy-handle = <&phy1>;
|
||||
mac-address = [ 00 10 18 36 23 1a ];
|
||||
compatible = "brcm,genet-v2";
|
||||
#address-cells = <0x1>;
|
||||
#size-cells = <0x1>;
|
||||
reg = <0x430000 0x4c8c>;
|
||||
interrupts = <24>, <25>;
|
||||
interrupt-parent = <&periph_intc>;
|
||||
status = "disabled";
|
||||
|
||||
mdio@e14 {
|
||||
compatible = "brcm,genet-mdio-v2";
|
||||
#address-cells = <0x1>;
|
||||
#size-cells = <0x0>;
|
||||
reg = <0xe14 0x8>;
|
||||
|
||||
phy1: ethernet-phy@1 {
|
||||
max-speed = <100>;
|
||||
reg = <0x1>;
|
||||
compatible = "brcm,40nm-ephy",
|
||||
"ethernet-phy-ieee802.3-c22";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
ehci0: usb@480300 {
|
||||
compatible = "brcm,bcm7358-ehci", "generic-ehci";
|
||||
reg = <0x480300 0x100>;
|
||||
native-endian;
|
||||
interrupt-parent = <&periph_intc>;
|
||||
interrupts = <65>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ohci0: usb@480400 {
|
||||
compatible = "brcm,bcm7358-ohci", "generic-ohci";
|
||||
reg = <0x480400 0x100>;
|
||||
native-endian;
|
||||
no-big-frame-no;
|
||||
interrupt-parent = <&periph_intc>;
|
||||
interrupts = <66>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,161 @@
|
|||
/ {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "brcm,bcm7360";
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
mips-hpt-frequency = <375000000>;
|
||||
|
||||
cpu@0 {
|
||||
compatible = "brcm,bmips3300";
|
||||
device_type = "cpu";
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
aliases {
|
||||
uart0 = &uart0;
|
||||
};
|
||||
|
||||
cpu_intc: cpu_intc {
|
||||
#address-cells = <0>;
|
||||
compatible = "mti,cpu-interrupt-controller";
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
};
|
||||
|
||||
clocks {
|
||||
uart_clk: uart_clk {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <81000000>;
|
||||
};
|
||||
};
|
||||
|
||||
rdb {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
compatible = "simple-bus";
|
||||
ranges = <0 0x10000000 0x01000000>;
|
||||
|
||||
periph_intc: periph_intc@411400 {
|
||||
compatible = "brcm,bcm7038-l1-intc";
|
||||
reg = <0x411400 0x30>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
|
||||
interrupt-parent = <&cpu_intc>;
|
||||
interrupts = <2>;
|
||||
};
|
||||
|
||||
sun_l2_intc: sun_l2_intc@403000 {
|
||||
compatible = "brcm,l2-intc";
|
||||
reg = <0x403000 0x30>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-parent = <&periph_intc>;
|
||||
interrupts = <48>;
|
||||
};
|
||||
|
||||
gisb-arb@400000 {
|
||||
compatible = "brcm,bcm7400-gisb-arb";
|
||||
reg = <0x400000 0xdc>;
|
||||
native-endian;
|
||||
interrupt-parent = <&sun_l2_intc>;
|
||||
interrupts = <0>, <2>;
|
||||
brcm,gisb-arb-master-mask = <0x2f3>;
|
||||
brcm,gisb-arb-master-names = "ssp_0", "cpu_0", "bsp_0",
|
||||
"rdc_0", "raaga_0",
|
||||
"avd_0", "jtag_0";
|
||||
};
|
||||
|
||||
upg_irq0_intc: upg_irq0_intc@406600 {
|
||||
compatible = "brcm,bcm7120-l2-intc";
|
||||
reg = <0x406600 0x8>;
|
||||
|
||||
brcm,int-map-mask = <0x44>;
|
||||
brcm,int-fwd-mask = <0x70000>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
|
||||
interrupt-parent = <&periph_intc>;
|
||||
interrupts = <56>;
|
||||
};
|
||||
|
||||
sun_top_ctrl: syscon@404000 {
|
||||
compatible = "brcm,bcm7360-sun-top-ctrl", "syscon";
|
||||
reg = <0x404000 0x51c>;
|
||||
little-endian;
|
||||
};
|
||||
|
||||
reboot {
|
||||
compatible = "brcm,brcmstb-reboot";
|
||||
syscon = <&sun_top_ctrl 0x304 0x308>;
|
||||
};
|
||||
|
||||
uart0: serial@406800 {
|
||||
compatible = "ns16550a";
|
||||
reg = <0x406800 0x20>;
|
||||
reg-io-width = <0x4>;
|
||||
reg-shift = <0x2>;
|
||||
native-endian;
|
||||
interrupt-parent = <&periph_intc>;
|
||||
interrupts = <61>;
|
||||
clocks = <&uart_clk>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
enet0: ethernet@430000 {
|
||||
phy-mode = "internal";
|
||||
phy-handle = <&phy1>;
|
||||
mac-address = [ 00 10 18 36 23 1a ];
|
||||
compatible = "brcm,genet-v2";
|
||||
#address-cells = <0x1>;
|
||||
#size-cells = <0x1>;
|
||||
reg = <0x430000 0x4c8c>;
|
||||
interrupts = <24>, <25>;
|
||||
interrupt-parent = <&periph_intc>;
|
||||
status = "disabled";
|
||||
|
||||
mdio@e14 {
|
||||
compatible = "brcm,genet-mdio-v2";
|
||||
#address-cells = <0x1>;
|
||||
#size-cells = <0x0>;
|
||||
reg = <0xe14 0x8>;
|
||||
|
||||
phy1: ethernet-phy@1 {
|
||||
max-speed = <100>;
|
||||
reg = <0x1>;
|
||||
compatible = "brcm,40nm-ephy",
|
||||
"ethernet-phy-ieee802.3-c22";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
ehci0: usb@480300 {
|
||||
compatible = "brcm,bcm7360-ehci", "generic-ehci";
|
||||
reg = <0x480300 0x100>;
|
||||
native-endian;
|
||||
interrupt-parent = <&periph_intc>;
|
||||
interrupts = <65>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ohci0: usb@480400 {
|
||||
compatible = "brcm,bcm7360-ohci", "generic-ohci";
|
||||
reg = <0x480400 0x100>;
|
||||
native-endian;
|
||||
no-big-frame-no;
|
||||
interrupt-parent = <&periph_intc>;
|
||||
interrupts = <66>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,167 @@
|
|||
/ {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "brcm,bcm7362";
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
mips-hpt-frequency = <375000000>;
|
||||
|
||||
cpu@0 {
|
||||
compatible = "brcm,bmips4380";
|
||||
device_type = "cpu";
|
||||
reg = <0>;
|
||||
};
|
||||
|
||||
cpu@1 {
|
||||
compatible = "brcm,bmips4380";
|
||||
device_type = "cpu";
|
||||
reg = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
aliases {
|
||||
uart0 = &uart0;
|
||||
};
|
||||
|
||||
cpu_intc: cpu_intc {
|
||||
#address-cells = <0>;
|
||||
compatible = "mti,cpu-interrupt-controller";
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
};
|
||||
|
||||
clocks {
|
||||
uart_clk: uart_clk {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <81000000>;
|
||||
};
|
||||
};
|
||||
|
||||
rdb {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
compatible = "simple-bus";
|
||||
ranges = <0 0x10000000 0x01000000>;
|
||||
|
||||
periph_intc: periph_intc@411400 {
|
||||
compatible = "brcm,bcm7038-l1-intc";
|
||||
reg = <0x411400 0x30>, <0x411600 0x30>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
|
||||
interrupt-parent = <&cpu_intc>;
|
||||
interrupts = <2>, <3>;
|
||||
};
|
||||
|
||||
sun_l2_intc: sun_l2_intc@403000 {
|
||||
compatible = "brcm,l2-intc";
|
||||
reg = <0x403000 0x30>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-parent = <&periph_intc>;
|
||||
interrupts = <48>;
|
||||
};
|
||||
|
||||
gisb-arb@400000 {
|
||||
compatible = "brcm,bcm7400-gisb-arb";
|
||||
reg = <0x400000 0xdc>;
|
||||
native-endian;
|
||||
interrupt-parent = <&sun_l2_intc>;
|
||||
interrupts = <0>, <2>;
|
||||
brcm,gisb-arb-master-mask = <0x2f3>;
|
||||
brcm,gisb-arb-master-names = "ssp_0", "cpu_0", "bsp_0",
|
||||
"rdc_0", "raaga_0",
|
||||
"avd_0", "jtag_0";
|
||||
};
|
||||
|
||||
upg_irq0_intc: upg_irq0_intc@406600 {
|
||||
compatible = "brcm,bcm7120-l2-intc";
|
||||
reg = <0x406600 0x8>;
|
||||
|
||||
brcm,int-map-mask = <0x44>;
|
||||
brcm,int-fwd-mask = <0x70000>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
|
||||
interrupt-parent = <&periph_intc>;
|
||||
interrupts = <56>;
|
||||
};
|
||||
|
||||
sun_top_ctrl: syscon@404000 {
|
||||
compatible = "brcm,bcm7362-sun-top-ctrl", "syscon";
|
||||
reg = <0x404000 0x51c>;
|
||||
little-endian;
|
||||
};
|
||||
|
||||
reboot {
|
||||
compatible = "brcm,brcmstb-reboot";
|
||||
syscon = <&sun_top_ctrl 0x304 0x308>;
|
||||
};
|
||||
|
||||
uart0: serial@406800 {
|
||||
compatible = "ns16550a";
|
||||
reg = <0x406800 0x20>;
|
||||
reg-io-width = <0x4>;
|
||||
reg-shift = <0x2>;
|
||||
native-endian;
|
||||
interrupt-parent = <&periph_intc>;
|
||||
interrupts = <61>;
|
||||
clocks = <&uart_clk>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
enet0: ethernet@430000 {
|
||||
phy-mode = "internal";
|
||||
phy-handle = <&phy1>;
|
||||
mac-address = [ 00 10 18 36 23 1a ];
|
||||
compatible = "brcm,genet-v2";
|
||||
#address-cells = <0x1>;
|
||||
#size-cells = <0x1>;
|
||||
reg = <0x430000 0x4c8c>;
|
||||
interrupts = <24>, <25>;
|
||||
interrupt-parent = <&periph_intc>;
|
||||
status = "disabled";
|
||||
|
||||
mdio@e14 {
|
||||
compatible = "brcm,genet-mdio-v2";
|
||||
#address-cells = <0x1>;
|
||||
#size-cells = <0x0>;
|
||||
reg = <0xe14 0x8>;
|
||||
|
||||
phy1: ethernet-phy@1 {
|
||||
max-speed = <100>;
|
||||
reg = <0x1>;
|
||||
compatible = "brcm,40nm-ephy",
|
||||
"ethernet-phy-ieee802.3-c22";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
ehci0: usb@480300 {
|
||||
compatible = "brcm,bcm7362-ehci", "generic-ehci";
|
||||
reg = <0x480300 0x100>;
|
||||
native-endian;
|
||||
interrupt-parent = <&periph_intc>;
|
||||
interrupts = <65>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ohci0: usb@480400 {
|
||||
compatible = "brcm,bcm7362-ohci", "generic-ohci";
|
||||
reg = <0x480400 0x100>;
|
||||
native-endian;
|
||||
no-big-frame-no;
|
||||
interrupt-parent = <&periph_intc>;
|
||||
interrupts = <66>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,184 @@
|
|||
/ {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "brcm,bcm7420";
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
mips-hpt-frequency = <93750000>;
|
||||
|
||||
cpu@0 {
|
||||
compatible = "brcm,bmips5000";
|
||||
device_type = "cpu";
|
||||
reg = <0>;
|
||||
};
|
||||
|
||||
cpu@1 {
|
||||
compatible = "brcm,bmips5000";
|
||||
device_type = "cpu";
|
||||
reg = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
aliases {
|
||||
uart0 = &uart0;
|
||||
};
|
||||
|
||||
cpu_intc: cpu_intc {
|
||||
#address-cells = <0>;
|
||||
compatible = "mti,cpu-interrupt-controller";
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
};
|
||||
|
||||
clocks {
|
||||
uart_clk: uart_clk {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <81000000>;
|
||||
};
|
||||
};
|
||||
|
||||
rdb {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
compatible = "simple-bus";
|
||||
ranges = <0 0x10000000 0x01000000>;
|
||||
|
||||
periph_intc: periph_intc@441400 {
|
||||
compatible = "brcm,bcm7038-l1-intc";
|
||||
reg = <0x441400 0x30>, <0x441600 0x30>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
|
||||
interrupt-parent = <&cpu_intc>;
|
||||
interrupts = <2>, <3>;
|
||||
};
|
||||
|
||||
sun_l2_intc: sun_l2_intc@401800 {
|
||||
compatible = "brcm,l2-intc";
|
||||
reg = <0x401800 0x30>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-parent = <&periph_intc>;
|
||||
interrupts = <23>;
|
||||
};
|
||||
|
||||
gisb-arb@400000 {
|
||||
compatible = "brcm,bcm7400-gisb-arb";
|
||||
reg = <0x400000 0xdc>;
|
||||
native-endian;
|
||||
interrupt-parent = <&sun_l2_intc>;
|
||||
interrupts = <0>, <2>;
|
||||
brcm,gisb-arb-master-mask = <0x3ff>;
|
||||
brcm,gisb-arb-master-names = "ssp_0", "cpu_0", "pci_0",
|
||||
"pcie_0", "bsp_0", "rdc_0",
|
||||
"rptd_0", "avd_0", "avd_1",
|
||||
"jtag_0";
|
||||
};
|
||||
|
||||
upg_irq0_intc: upg_irq0_intc@406780 {
|
||||
compatible = "brcm,bcm7120-l2-intc";
|
||||
reg = <0x406780 0x8>;
|
||||
|
||||
brcm,int-map-mask = <0x44>;
|
||||
brcm,int-fwd-mask = <0x70000>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
|
||||
interrupt-parent = <&periph_intc>;
|
||||
interrupts = <18>;
|
||||
};
|
||||
|
||||
sun_top_ctrl: syscon@404000 {
|
||||
compatible = "brcm,bcm7420-sun-top-ctrl", "syscon";
|
||||
reg = <0x404000 0x60c>;
|
||||
little-endian;
|
||||
};
|
||||
|
||||
reboot {
|
||||
compatible = "brcm,bcm7038-reboot";
|
||||
syscon = <&sun_top_ctrl 0x8 0x14>;
|
||||
};
|
||||
|
||||
uart0: serial@406b00 {
|
||||
compatible = "ns16550a";
|
||||
reg = <0x406b00 0x20>;
|
||||
reg-io-width = <0x4>;
|
||||
reg-shift = <0x2>;
|
||||
interrupt-parent = <&periph_intc>;
|
||||
interrupts = <21>;
|
||||
clocks = <&uart_clk>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
enet0: ethernet@468000 {
|
||||
phy-mode = "internal";
|
||||
phy-handle = <&phy1>;
|
||||
mac-address = [ 00 10 18 36 23 1a ];
|
||||
compatible = "brcm,genet-v1";
|
||||
#address-cells = <0x1>;
|
||||
#size-cells = <0x1>;
|
||||
reg = <0x468000 0x3c8c>;
|
||||
interrupts = <69>, <79>;
|
||||
interrupt-parent = <&periph_intc>;
|
||||
status = "disabled";
|
||||
|
||||
mdio@e14 {
|
||||
compatible = "brcm,genet-mdio-v1";
|
||||
#address-cells = <0x1>;
|
||||
#size-cells = <0x0>;
|
||||
reg = <0xe14 0x8>;
|
||||
|
||||
phy1: ethernet-phy@1 {
|
||||
max-speed = <100>;
|
||||
reg = <0x1>;
|
||||
compatible = "brcm,65nm-ephy",
|
||||
"ethernet-phy-ieee802.3-c22";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
ehci0: usb@488300 {
|
||||
compatible = "brcm,bcm7420-ehci", "generic-ehci";
|
||||
reg = <0x488300 0x100>;
|
||||
interrupt-parent = <&periph_intc>;
|
||||
interrupts = <60>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ohci0: usb@488400 {
|
||||
compatible = "brcm,bcm7420-ohci", "generic-ohci";
|
||||
reg = <0x488400 0x100>;
|
||||
native-endian;
|
||||
no-big-frame-no;
|
||||
interrupt-parent = <&periph_intc>;
|
||||
interrupts = <61>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ehci1: usb@488500 {
|
||||
compatible = "brcm,bcm7420-ehci", "generic-ehci";
|
||||
reg = <0x488500 0x100>;
|
||||
interrupt-parent = <&periph_intc>;
|
||||
interrupts = <55>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ohci1: usb@488600 {
|
||||
compatible = "brcm,bcm7420-ohci", "generic-ohci";
|
||||
reg = <0x488600 0x100>;
|
||||
native-endian;
|
||||
no-big-frame-no;
|
||||
interrupt-parent = <&periph_intc>;
|
||||
interrupts = <62>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,225 @@
|
|||
/ {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "brcm,bcm7425";
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
mips-hpt-frequency = <163125000>;
|
||||
|
||||
cpu@0 {
|
||||
compatible = "brcm,bmips5000";
|
||||
device_type = "cpu";
|
||||
reg = <0>;
|
||||
};
|
||||
|
||||
cpu@1 {
|
||||
compatible = "brcm,bmips5000";
|
||||
device_type = "cpu";
|
||||
reg = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
aliases {
|
||||
uart0 = &uart0;
|
||||
};
|
||||
|
||||
cpu_intc: cpu_intc {
|
||||
#address-cells = <0>;
|
||||
compatible = "mti,cpu-interrupt-controller";
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
};
|
||||
|
||||
clocks {
|
||||
uart_clk: uart_clk {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <81000000>;
|
||||
};
|
||||
};
|
||||
|
||||
rdb {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
compatible = "simple-bus";
|
||||
ranges = <0 0x10000000 0x01000000>;
|
||||
|
||||
periph_intc: periph_intc@41a400 {
|
||||
compatible = "brcm,bcm7038-l1-intc";
|
||||
reg = <0x41a400 0x30>, <0x41a600 0x30>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
|
||||
interrupt-parent = <&cpu_intc>;
|
||||
interrupts = <2>, <3>;
|
||||
};
|
||||
|
||||
sun_l2_intc: sun_l2_intc@403000 {
|
||||
compatible = "brcm,l2-intc";
|
||||
reg = <0x403000 0x30>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-parent = <&periph_intc>;
|
||||
interrupts = <47>;
|
||||
};
|
||||
|
||||
gisb-arb@400000 {
|
||||
compatible = "brcm,bcm7400-gisb-arb";
|
||||
reg = <0x400000 0xdc>;
|
||||
native-endian;
|
||||
interrupt-parent = <&sun_l2_intc>;
|
||||
interrupts = <0>, <2>;
|
||||
brcm,gisb-arb-master-mask = <0x177b>;
|
||||
brcm,gisb-arb-master-names = "ssp_0", "cpu_0", "pcie_0",
|
||||
"bsp_0", "rdc_0",
|
||||
"raaga_0", "avd_1",
|
||||
"jtag_0", "svd_0",
|
||||
"vice_0";
|
||||
};
|
||||
|
||||
upg_irq0_intc: upg_irq0_intc@406780 {
|
||||
compatible = "brcm,bcm7120-l2-intc";
|
||||
reg = <0x406780 0x8>;
|
||||
|
||||
brcm,int-map-mask = <0x44>;
|
||||
brcm,int-fwd-mask = <0x70000>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
|
||||
interrupt-parent = <&periph_intc>;
|
||||
interrupts = <55>;
|
||||
};
|
||||
|
||||
sun_top_ctrl: syscon@404000 {
|
||||
compatible = "brcm,bcm7425-sun-top-ctrl", "syscon";
|
||||
reg = <0x404000 0x51c>;
|
||||
little-endian;
|
||||
};
|
||||
|
||||
reboot {
|
||||
compatible = "brcm,brcmstb-reboot";
|
||||
syscon = <&sun_top_ctrl 0x304 0x308>;
|
||||
};
|
||||
|
||||
uart0: serial@406b00 {
|
||||
compatible = "ns16550a";
|
||||
reg = <0x406b00 0x20>;
|
||||
reg-io-width = <0x4>;
|
||||
reg-shift = <0x2>;
|
||||
interrupt-parent = <&periph_intc>;
|
||||
interrupts = <61>;
|
||||
clocks = <&uart_clk>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
enet0: ethernet@b80000 {
|
||||
phy-mode = "internal";
|
||||
phy-handle = <&phy1>;
|
||||
mac-address = [ 00 10 18 36 23 1a ];
|
||||
compatible = "brcm,genet-v3";
|
||||
#address-cells = <0x1>;
|
||||
#size-cells = <0x1>;
|
||||
reg = <0xb80000 0x11c88>;
|
||||
interrupts = <17>, <18>;
|
||||
interrupt-parent = <&periph_intc>;
|
||||
status = "disabled";
|
||||
|
||||
mdio@e14 {
|
||||
compatible = "brcm,genet-mdio-v3";
|
||||
#address-cells = <0x1>;
|
||||
#size-cells = <0x0>;
|
||||
reg = <0xe14 0x8>;
|
||||
|
||||
phy1: ethernet-phy@1 {
|
||||
max-speed = <100>;
|
||||
reg = <0x1>;
|
||||
compatible = "brcm,40nm-ephy",
|
||||
"ethernet-phy-ieee802.3-c22";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
ehci0: usb@480300 {
|
||||
compatible = "brcm,bcm7425-ehci", "generic-ehci";
|
||||
reg = <0x480300 0x100>;
|
||||
native-endian;
|
||||
interrupt-parent = <&periph_intc>;
|
||||
interrupts = <65>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ohci0: usb@480400 {
|
||||
compatible = "brcm,bcm7425-ohci", "generic-ohci";
|
||||
reg = <0x480400 0x100>;
|
||||
native-endian;
|
||||
no-big-frame-no;
|
||||
interrupt-parent = <&periph_intc>;
|
||||
interrupts = <67>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ehci1: usb@480500 {
|
||||
compatible = "brcm,bcm7425-ehci", "generic-ehci";
|
||||
reg = <0x480500 0x100>;
|
||||
native-endian;
|
||||
interrupt-parent = <&periph_intc>;
|
||||
interrupts = <66>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ohci1: usb@480600 {
|
||||
compatible = "brcm,bcm7425-ohci", "generic-ohci";
|
||||
reg = <0x480600 0x100>;
|
||||
native-endian;
|
||||
no-big-frame-no;
|
||||
interrupt-parent = <&periph_intc>;
|
||||
interrupts = <68>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ehci2: usb@490300 {
|
||||
compatible = "brcm,bcm7425-ehci", "generic-ehci";
|
||||
reg = <0x490300 0x100>;
|
||||
native-endian;
|
||||
interrupt-parent = <&periph_intc>;
|
||||
interrupts = <70>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ohci2: usb@490400 {
|
||||
compatible = "brcm,bcm7425-ohci", "generic-ohci";
|
||||
reg = <0x490400 0x100>;
|
||||
native-endian;
|
||||
no-big-frame-no;
|
||||
interrupt-parent = <&periph_intc>;
|
||||
interrupts = <72>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ehci3: usb@490500 {
|
||||
compatible = "brcm,bcm7425-ehci", "generic-ehci";
|
||||
reg = <0x490500 0x100>;
|
||||
native-endian;
|
||||
interrupt-parent = <&periph_intc>;
|
||||
interrupts = <71>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ohci3: usb@490600 {
|
||||
compatible = "brcm,bcm7425-ohci", "generic-ohci";
|
||||
reg = <0x490600 0x100>;
|
||||
native-endian;
|
||||
no-big-frame-no;
|
||||
interrupt-parent = <&periph_intc>;
|
||||
interrupts = <73>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -1,6 +1,6 @@
|
|||
/dts-v1/;
|
||||
|
||||
/include/ "bcm3384.dtsi"
|
||||
/include/ "bcm3384_zephyr.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "brcm,bcm93384wvg", "brcm,bcm3384";
|
||||
|
|
@ -10,13 +10,6 @@
|
|||
bootargs = "console=ttyS0,115200";
|
||||
stdout-path = &uart0;
|
||||
};
|
||||
|
||||
memory@0 {
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x04000000>;
|
||||
dma-xor-mask = <0x08000000>;
|
||||
dma-xor-limit = <0x0fffffff>;
|
||||
};
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
|
|
@ -0,0 +1,25 @@
|
|||
/dts-v1/;
|
||||
|
||||
/include/ "bcm3384_viper.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "brcm,bcm93384wvg-viper", "brcm,bcm3384-viper";
|
||||
model = "Broadcom BCM93384WVG-viper";
|
||||
|
||||
chosen {
|
||||
bootargs = "console=ttyS0,115200";
|
||||
stdout-path = &uart0;
|
||||
};
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ehci0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ohci0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -0,0 +1,31 @@
|
|||
/dts-v1/;
|
||||
|
||||
/include/ "bcm6368.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "brcm,bcm96368mvwg", "brcm,bcm6368";
|
||||
model = "Broadcom BCM96368MVWG";
|
||||
|
||||
memory@0 {
|
||||
device_type = "memory";
|
||||
reg = <0x00000000 0x04000000>;
|
||||
};
|
||||
|
||||
chosen {
|
||||
bootargs = "console=ttyS0,115200";
|
||||
stdout-path = &uart0;
|
||||
};
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* FIXME: need to set up USB_CTRL registers first */
|
||||
&ehci0 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&ohci0 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -0,0 +1,31 @@
|
|||
/dts-v1/;
|
||||
|
||||
/include/ "bcm7125.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "brcm,bcm97125cbmb", "brcm,bcm7125";
|
||||
model = "Broadcom BCM97125CBMB";
|
||||
|
||||
memory@0 {
|
||||
device_type = "memory";
|
||||
reg = <0x00000000 0x10000000>;
|
||||
};
|
||||
|
||||
chosen {
|
||||
bootargs = "console=ttyS0,115200";
|
||||
stdout-path = &uart0;
|
||||
};
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* FIXME: USB is wonky; disable it for now */
|
||||
&ehci0 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&ohci0 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -0,0 +1,58 @@
|
|||
/dts-v1/;
|
||||
|
||||
/include/ "bcm7346.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "brcm,bcm97346dbsmb", "brcm,bcm7346";
|
||||
model = "Broadcom BCM97346DBSMB";
|
||||
|
||||
memory@0 {
|
||||
device_type = "memory";
|
||||
reg = <0x00000000 0x10000000>, <0x20000000 0x30000000>;
|
||||
};
|
||||
|
||||
chosen {
|
||||
bootargs = "console=ttyS0,115200";
|
||||
stdout-path = &uart0;
|
||||
};
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&enet0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ehci0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ohci0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ehci1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ohci1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ehci2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ohci2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ehci3 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ohci3 {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -0,0 +1,34 @@
|
|||
/dts-v1/;
|
||||
|
||||
/include/ "bcm7358.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "brcm,bcm97358svmb", "brcm,bcm7358";
|
||||
model = "Broadcom BCM97358SVMB";
|
||||
|
||||
memory@0 {
|
||||
device_type = "memory";
|
||||
reg = <0x00000000 0x10000000>;
|
||||
};
|
||||
|
||||
chosen {
|
||||
bootargs = "console=ttyS0,115200";
|
||||
stdout-path = &uart0;
|
||||
};
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&enet0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ehci0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ohci0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -0,0 +1,34 @@
|
|||
/dts-v1/;
|
||||
|
||||
/include/ "bcm7360.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "brcm,bcm97360svmb", "brcm,bcm7360";
|
||||
model = "Broadcom BCM97360SVMB";
|
||||
|
||||
memory@0 {
|
||||
device_type = "memory";
|
||||
reg = <0x00000000 0x10000000>;
|
||||
};
|
||||
|
||||
chosen {
|
||||
bootargs = "console=ttyS0,115200";
|
||||
stdout-path = &uart0;
|
||||
};
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&enet0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ehci0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ohci0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -0,0 +1,34 @@
|
|||
/dts-v1/;
|
||||
|
||||
/include/ "bcm7362.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "brcm,bcm97362svmb", "brcm,bcm7362";
|
||||
model = "Broadcom BCM97362SVMB";
|
||||
|
||||
memory@0 {
|
||||
device_type = "memory";
|
||||
reg = <0x00000000 0x10000000>, <0x20000000 0x30000000>;
|
||||
};
|
||||
|
||||
chosen {
|
||||
bootargs = "console=ttyS0,115200";
|
||||
stdout-path = &uart0;
|
||||
};
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&enet0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ehci0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ohci0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -0,0 +1,45 @@
|
|||
/dts-v1/;
|
||||
|
||||
/include/ "bcm7420.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "brcm,bcm97420c", "brcm,bcm7420";
|
||||
model = "Broadcom BCM97420C";
|
||||
|
||||
memory@0 {
|
||||
device_type = "memory";
|
||||
reg = <0x00000000 0x10000000>,
|
||||
<0x20000000 0x30000000>,
|
||||
<0x60000000 0x10000000>;
|
||||
};
|
||||
|
||||
chosen {
|
||||
bootargs = "console=ttyS0,115200";
|
||||
stdout-path = &uart0;
|
||||
};
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* FIXME: MAC driver comes up but cannot attach to PHY */
|
||||
&enet0 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&ehci0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ohci0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ehci1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ohci1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -0,0 +1,60 @@
|
|||
/dts-v1/;
|
||||
|
||||
/include/ "bcm7425.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "brcm,bcm97425svmb", "brcm,bcm7425";
|
||||
model = "Broadcom BCM97425SVMB";
|
||||
|
||||
memory@0 {
|
||||
device_type = "memory";
|
||||
reg = <0x00000000 0x10000000>,
|
||||
<0x20000000 0x30000000>,
|
||||
<0x90000000 0x40000000>;
|
||||
};
|
||||
|
||||
chosen {
|
||||
bootargs = "console=ttyS0,115200";
|
||||
stdout-path = &uart0;
|
||||
};
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&enet0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ehci0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ohci0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ehci1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ohci1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ehci2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ohci2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ehci3 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ohci3 {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -0,0 +1,22 @@
|
|||
/dts-v1/;
|
||||
|
||||
/include/ "bcm6328.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "brcm,bcm9ejtagprb", "brcm,bcm6328";
|
||||
model = "Broadcom BCM9EJTAGPRB";
|
||||
|
||||
memory@0 {
|
||||
device_type = "memory";
|
||||
reg = <0x00000000 0x08000000>;
|
||||
};
|
||||
|
||||
chosen {
|
||||
bootargs = "console=ttyS0,115200";
|
||||
stdout-path = &uart0;
|
||||
};
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -0,0 +1,9 @@
|
|||
dtb-$(CONFIG_CAVIUM_OCTEON_SOC) += octeon_3xxx.dtb octeon_68xx.dtb
|
||||
|
||||
obj-y += $(patsubst %.dtb, %.dtb.o, $(dtb-y))
|
||||
|
||||
# Force kbuild to make empty built-in.o if necessary
|
||||
obj- += dummy.o
|
||||
|
||||
always := $(dtb-y)
|
||||
clean-files := *.dtb *.dtb.S
|
||||
|
|
@ -587,4 +587,16 @@
|
|||
usbn = &usbn;
|
||||
led0 = &led0;
|
||||
};
|
||||
|
||||
dsr1000n-leds {
|
||||
compatible = "gpio-leds";
|
||||
usb1 {
|
||||
label = "usb1";
|
||||
gpios = <&gpio 9 1>; /* Active low */
|
||||
};
|
||||
usb2 {
|
||||
label = "usb2";
|
||||
gpios = <&gpio 10 1>; /* Active low */
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,9 @@
|
|||
dtb-$(CONFIG_DT_EASY50712) += easy50712.dtb
|
||||
|
||||
obj-y += $(patsubst %.dtb, %.dtb.o, $(dtb-y))
|
||||
|
||||
# Force kbuild to make empty built-in.o if necessary
|
||||
obj- += dummy.o
|
||||
|
||||
always := $(dtb-y)
|
||||
clean-files := *.dtb *.dtb.S
|
||||
|
|
@ -0,0 +1,9 @@
|
|||
dtb-$(CONFIG_MIPS_SEAD3) += sead3.dtb
|
||||
|
||||
obj-y += $(patsubst %.dtb, %.dtb.o, $(dtb-y))
|
||||
|
||||
# Force kbuild to make empty built-in.o if necessary
|
||||
obj- += dummy.o
|
||||
|
||||
always := $(dtb-y)
|
||||
clean-files := *.dtb *.dtb.S
|
||||
|
|
@ -0,0 +1,13 @@
|
|||
dtb-$(CONFIG_DT_XLP_EVP) += xlp_evp.dtb
|
||||
dtb-$(CONFIG_DT_XLP_SVP) += xlp_svp.dtb
|
||||
dtb-$(CONFIG_DT_XLP_FVP) += xlp_fvp.dtb
|
||||
dtb-$(CONFIG_DT_XLP_GVP) += xlp_gvp.dtb
|
||||
dtb-$(CONFIG_DT_XLP_RVP) += xlp_rvp.dtb
|
||||
|
||||
obj-y += $(patsubst %.dtb, %.dtb.o, $(dtb-y))
|
||||
|
||||
# Force kbuild to make empty built-in.o if necessary
|
||||
obj- += dummy.o
|
||||
|
||||
always := $(dtb-y)
|
||||
clean-files := *.dtb *.dtb.S
|
||||
|
|
@ -0,0 +1,77 @@
|
|||
/*
|
||||
* XLP5XX Device Tree Source for RVP boards
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/ {
|
||||
model = "netlogic,XLP-RVP";
|
||||
compatible = "netlogic,xlp";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
soc {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
compatible = "simple-bus";
|
||||
ranges = <0 0 0 0x18000000 0x04000000 // PCIe CFG
|
||||
1 0 0 0x16000000 0x02000000>; // GBU chipselects
|
||||
|
||||
serial0: serial@30000 {
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <0 0x112100 0xa00>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
clock-frequency = <125000000>;
|
||||
interrupt-parent = <&pic>;
|
||||
interrupts = <17>;
|
||||
};
|
||||
pic: pic@110000 {
|
||||
compatible = "netlogic,xlp-pic";
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <1>;
|
||||
reg = <0 0x110000 0x200>;
|
||||
interrupt-controller;
|
||||
};
|
||||
|
||||
nor_flash@1,0 {
|
||||
compatible = "cfi-flash";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
bank-width = <2>;
|
||||
reg = <1 0 0x1000000>;
|
||||
|
||||
partition@0 {
|
||||
label = "x-loader";
|
||||
reg = <0x0 0x100000>; /* 1M */
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@100000 {
|
||||
label = "u-boot";
|
||||
reg = <0x100000 0x100000>; /* 1M */
|
||||
};
|
||||
|
||||
partition@200000 {
|
||||
label = "kernel";
|
||||
reg = <0x200000 0x500000>; /* 5M */
|
||||
};
|
||||
|
||||
partition@700000 {
|
||||
label = "rootfs";
|
||||
reg = <0x700000 0x800000>; /* 8M */
|
||||
};
|
||||
|
||||
partition@f00000 {
|
||||
label = "env";
|
||||
reg = <0xf00000 0x100000>; /* 1M */
|
||||
read-only;
|
||||
};
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
chosen {
|
||||
bootargs = "console=ttyS0,115200 rdinit=/sbin/init";
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,12 @@
|
|||
dtb-$(CONFIG_DTB_RT2880_EVAL) += rt2880_eval.dtb
|
||||
dtb-$(CONFIG_DTB_RT305X_EVAL) += rt3052_eval.dtb
|
||||
dtb-$(CONFIG_DTB_RT3883_EVAL) += rt3883_eval.dtb
|
||||
dtb-$(CONFIG_DTB_MT7620A_EVAL) += mt7620a_eval.dtb
|
||||
|
||||
obj-y += $(patsubst %.dtb, %.dtb.o, $(dtb-y))
|
||||
|
||||
# Force kbuild to make empty built-in.o if necessary
|
||||
obj- += dummy.o
|
||||
|
||||
always := $(dtb-y)
|
||||
clean-files := *.dtb *.dtb.S
|
||||
|
|
@ -33,7 +33,7 @@ do { \
|
|||
__asm__ __volatile__ ( \
|
||||
"dmtc2 %[rt],0x0048+" STR(index) \
|
||||
: \
|
||||
: [rt] "d" (value)); \
|
||||
: [rt] "d" (cpu_to_be64(value))); \
|
||||
} while (0)
|
||||
|
||||
/*
|
||||
|
|
@ -48,7 +48,7 @@ do { \
|
|||
: [rt] "=d" (__value) \
|
||||
: ); \
|
||||
\
|
||||
__value; \
|
||||
be64_to_cpu(__value); \
|
||||
})
|
||||
|
||||
/*
|
||||
|
|
@ -59,7 +59,7 @@ do { \
|
|||
__asm__ __volatile__ ( \
|
||||
"dmtc2 %[rt],0x0040+" STR(index) \
|
||||
: \
|
||||
: [rt] "d" (value)); \
|
||||
: [rt] "d" (cpu_to_be64(value))); \
|
||||
} while (0)
|
||||
|
||||
/*
|
||||
|
|
@ -70,6 +70,80 @@ do { \
|
|||
__asm__ __volatile__ ( \
|
||||
"dmtc2 %[rt],0x4047" \
|
||||
: \
|
||||
: [rt] "d" (cpu_to_be64(value))); \
|
||||
} while (0)
|
||||
|
||||
/*
|
||||
* The value is the final block dword (64-bit).
|
||||
*/
|
||||
#define octeon_sha1_start(value) \
|
||||
do { \
|
||||
__asm__ __volatile__ ( \
|
||||
"dmtc2 %[rt],0x4057" \
|
||||
: \
|
||||
: [rt] "d" (value)); \
|
||||
} while (0)
|
||||
|
||||
/*
|
||||
* The value is the final block dword (64-bit).
|
||||
*/
|
||||
#define octeon_sha256_start(value) \
|
||||
do { \
|
||||
__asm__ __volatile__ ( \
|
||||
"dmtc2 %[rt],0x404f" \
|
||||
: \
|
||||
: [rt] "d" (value)); \
|
||||
} while (0)
|
||||
|
||||
/*
|
||||
* Macros needed to implement SHA512:
|
||||
*/
|
||||
|
||||
/*
|
||||
* The index can be 0-7.
|
||||
*/
|
||||
#define write_octeon_64bit_hash_sha512(value, index) \
|
||||
do { \
|
||||
__asm__ __volatile__ ( \
|
||||
"dmtc2 %[rt],0x0250+" STR(index) \
|
||||
: \
|
||||
: [rt] "d" (value)); \
|
||||
} while (0)
|
||||
|
||||
/*
|
||||
* The index can be 0-7.
|
||||
*/
|
||||
#define read_octeon_64bit_hash_sha512(index) \
|
||||
({ \
|
||||
u64 __value; \
|
||||
\
|
||||
__asm__ __volatile__ ( \
|
||||
"dmfc2 %[rt],0x0250+" STR(index) \
|
||||
: [rt] "=d" (__value) \
|
||||
: ); \
|
||||
\
|
||||
__value; \
|
||||
})
|
||||
|
||||
/*
|
||||
* The index can be 0-14.
|
||||
*/
|
||||
#define write_octeon_64bit_block_sha512(value, index) \
|
||||
do { \
|
||||
__asm__ __volatile__ ( \
|
||||
"dmtc2 %[rt],0x0240+" STR(index) \
|
||||
: \
|
||||
: [rt] "d" (value)); \
|
||||
} while (0)
|
||||
|
||||
/*
|
||||
* The value is the final block word (64-bit).
|
||||
*/
|
||||
#define octeon_sha512_start(value) \
|
||||
do { \
|
||||
__asm__ __volatile__ ( \
|
||||
"dmtc2 %[rt],0x424f" \
|
||||
: \
|
||||
: [rt] "d" (value)); \
|
||||
} while (0)
|
||||
|
||||
|
|
|
|||
|
|
@ -306,7 +306,7 @@ void __init plat_swiotlb_setup(void)
|
|||
swiotlbsize = 64 * (1<<20);
|
||||
}
|
||||
#endif
|
||||
#ifdef CONFIG_USB_OCTEON_OHCI
|
||||
#ifdef CONFIG_USB_OHCI_HCD_PLATFORM
|
||||
/* OCTEON II ohci is only 32-bit. */
|
||||
if (OCTEON_IS_OCTEON2() && max_addr >= 0x100000000ul)
|
||||
swiotlbsize = 64 * (1<<20);
|
||||
|
|
|
|||
|
|
@ -519,44 +519,89 @@ int cvmx_l2c_unlock_mem_region(uint64_t start, uint64_t len)
|
|||
union __cvmx_l2c_tag {
|
||||
uint64_t u64;
|
||||
struct cvmx_l2c_tag_cn50xx {
|
||||
#ifdef __BIG_ENDIAN_BITFIELD
|
||||
uint64_t reserved:40;
|
||||
uint64_t V:1; /* Line valid */
|
||||
uint64_t D:1; /* Line dirty */
|
||||
uint64_t L:1; /* Line locked */
|
||||
uint64_t U:1; /* Use, LRU eviction */
|
||||
uint64_t addr:20; /* Phys mem addr (33..14) */
|
||||
#else
|
||||
uint64_t addr:20; /* Phys mem addr (33..14) */
|
||||
uint64_t U:1; /* Use, LRU eviction */
|
||||
uint64_t L:1; /* Line locked */
|
||||
uint64_t D:1; /* Line dirty */
|
||||
uint64_t V:1; /* Line valid */
|
||||
uint64_t reserved:40;
|
||||
#endif
|
||||
} cn50xx;
|
||||
struct cvmx_l2c_tag_cn30xx {
|
||||
#ifdef __BIG_ENDIAN_BITFIELD
|
||||
uint64_t reserved:41;
|
||||
uint64_t V:1; /* Line valid */
|
||||
uint64_t D:1; /* Line dirty */
|
||||
uint64_t L:1; /* Line locked */
|
||||
uint64_t U:1; /* Use, LRU eviction */
|
||||
uint64_t addr:19; /* Phys mem addr (33..15) */
|
||||
#else
|
||||
uint64_t addr:19; /* Phys mem addr (33..15) */
|
||||
uint64_t U:1; /* Use, LRU eviction */
|
||||
uint64_t L:1; /* Line locked */
|
||||
uint64_t D:1; /* Line dirty */
|
||||
uint64_t V:1; /* Line valid */
|
||||
uint64_t reserved:41;
|
||||
#endif
|
||||
} cn30xx;
|
||||
struct cvmx_l2c_tag_cn31xx {
|
||||
#ifdef __BIG_ENDIAN_BITFIELD
|
||||
uint64_t reserved:42;
|
||||
uint64_t V:1; /* Line valid */
|
||||
uint64_t D:1; /* Line dirty */
|
||||
uint64_t L:1; /* Line locked */
|
||||
uint64_t U:1; /* Use, LRU eviction */
|
||||
uint64_t addr:18; /* Phys mem addr (33..16) */
|
||||
#else
|
||||
uint64_t addr:18; /* Phys mem addr (33..16) */
|
||||
uint64_t U:1; /* Use, LRU eviction */
|
||||
uint64_t L:1; /* Line locked */
|
||||
uint64_t D:1; /* Line dirty */
|
||||
uint64_t V:1; /* Line valid */
|
||||
uint64_t reserved:42;
|
||||
#endif
|
||||
} cn31xx;
|
||||
struct cvmx_l2c_tag_cn38xx {
|
||||
#ifdef __BIG_ENDIAN_BITFIELD
|
||||
uint64_t reserved:43;
|
||||
uint64_t V:1; /* Line valid */
|
||||
uint64_t D:1; /* Line dirty */
|
||||
uint64_t L:1; /* Line locked */
|
||||
uint64_t U:1; /* Use, LRU eviction */
|
||||
uint64_t addr:17; /* Phys mem addr (33..17) */
|
||||
#else
|
||||
uint64_t addr:17; /* Phys mem addr (33..17) */
|
||||
uint64_t U:1; /* Use, LRU eviction */
|
||||
uint64_t L:1; /* Line locked */
|
||||
uint64_t D:1; /* Line dirty */
|
||||
uint64_t V:1; /* Line valid */
|
||||
uint64_t reserved:43;
|
||||
#endif
|
||||
} cn38xx;
|
||||
struct cvmx_l2c_tag_cn58xx {
|
||||
#ifdef __BIG_ENDIAN_BITFIELD
|
||||
uint64_t reserved:44;
|
||||
uint64_t V:1; /* Line valid */
|
||||
uint64_t D:1; /* Line dirty */
|
||||
uint64_t L:1; /* Line locked */
|
||||
uint64_t U:1; /* Use, LRU eviction */
|
||||
uint64_t addr:16; /* Phys mem addr (33..18) */
|
||||
#else
|
||||
uint64_t addr:16; /* Phys mem addr (33..18) */
|
||||
uint64_t U:1; /* Use, LRU eviction */
|
||||
uint64_t L:1; /* Line locked */
|
||||
uint64_t D:1; /* Line dirty */
|
||||
uint64_t V:1; /* Line valid */
|
||||
uint64_t reserved:44;
|
||||
#endif
|
||||
} cn58xx;
|
||||
struct cvmx_l2c_tag_cn58xx cn56xx; /* 2048 sets */
|
||||
struct cvmx_l2c_tag_cn31xx cn52xx; /* 512 sets */
|
||||
|
|
|
|||
|
|
@ -8,9 +8,11 @@
|
|||
* Copyright (C) 2007, 2008 Cavium Networks
|
||||
*/
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/export.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/semaphore.h>
|
||||
#include <linux/mtd/mtd.h>
|
||||
#include <linux/mtd/map.h>
|
||||
#include <linux/of_platform.h>
|
||||
#include <linux/mtd/partitions.h>
|
||||
|
||||
#include <asm/octeon/octeon.h>
|
||||
|
|
@ -25,19 +27,62 @@ static const char *part_probe_types[] = {
|
|||
NULL
|
||||
};
|
||||
|
||||
static map_word octeon_flash_map_read(struct map_info *map, unsigned long ofs)
|
||||
{
|
||||
map_word r;
|
||||
|
||||
down(&octeon_bootbus_sem);
|
||||
r = inline_map_read(map, ofs);
|
||||
up(&octeon_bootbus_sem);
|
||||
|
||||
return r;
|
||||
}
|
||||
|
||||
static void octeon_flash_map_write(struct map_info *map, const map_word datum,
|
||||
unsigned long ofs)
|
||||
{
|
||||
down(&octeon_bootbus_sem);
|
||||
inline_map_write(map, datum, ofs);
|
||||
up(&octeon_bootbus_sem);
|
||||
}
|
||||
|
||||
static void octeon_flash_map_copy_from(struct map_info *map, void *to,
|
||||
unsigned long from, ssize_t len)
|
||||
{
|
||||
down(&octeon_bootbus_sem);
|
||||
inline_map_copy_from(map, to, from, len);
|
||||
up(&octeon_bootbus_sem);
|
||||
}
|
||||
|
||||
static void octeon_flash_map_copy_to(struct map_info *map, unsigned long to,
|
||||
const void *from, ssize_t len)
|
||||
{
|
||||
down(&octeon_bootbus_sem);
|
||||
inline_map_copy_to(map, to, from, len);
|
||||
up(&octeon_bootbus_sem);
|
||||
}
|
||||
|
||||
/**
|
||||
* Module/ driver initialization.
|
||||
*
|
||||
* Returns Zero on success
|
||||
*/
|
||||
static int __init flash_init(void)
|
||||
static int octeon_flash_probe(struct platform_device *pdev)
|
||||
{
|
||||
union cvmx_mio_boot_reg_cfgx region_cfg;
|
||||
u32 cs;
|
||||
int r;
|
||||
struct device_node *np = pdev->dev.of_node;
|
||||
|
||||
r = of_property_read_u32(np, "reg", &cs);
|
||||
if (r)
|
||||
return r;
|
||||
|
||||
/*
|
||||
* Read the bootbus region 0 setup to determine the base
|
||||
* address of the flash.
|
||||
*/
|
||||
union cvmx_mio_boot_reg_cfgx region_cfg;
|
||||
region_cfg.u64 = cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(0));
|
||||
region_cfg.u64 = cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(cs));
|
||||
if (region_cfg.s.en) {
|
||||
/*
|
||||
* The bootloader always takes the flash and sets its
|
||||
|
|
@ -56,7 +101,11 @@ static int __init flash_init(void)
|
|||
flash_map.virt = ioremap(flash_map.phys, flash_map.size);
|
||||
pr_notice("Bootbus flash: Setting flash for %luMB flash at "
|
||||
"0x%08llx\n", flash_map.size >> 20, flash_map.phys);
|
||||
simple_map_init(&flash_map);
|
||||
WARN_ON(!map_bankwidth_supported(flash_map.bankwidth));
|
||||
flash_map.read = octeon_flash_map_read;
|
||||
flash_map.write = octeon_flash_map_write;
|
||||
flash_map.copy_from = octeon_flash_map_copy_from;
|
||||
flash_map.copy_to = octeon_flash_map_copy_to;
|
||||
mymtd = do_map_probe("cfi_probe", &flash_map);
|
||||
if (mymtd) {
|
||||
mymtd->owner = THIS_MODULE;
|
||||
|
|
@ -69,4 +118,26 @@ static int __init flash_init(void)
|
|||
return 0;
|
||||
}
|
||||
|
||||
late_initcall(flash_init);
|
||||
static const struct of_device_id of_flash_match[] = {
|
||||
{
|
||||
.compatible = "cfi-flash",
|
||||
},
|
||||
{ },
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, of_flash_match);
|
||||
|
||||
static struct platform_driver of_flash_driver = {
|
||||
.driver = {
|
||||
.name = "octeon-of-flash",
|
||||
.of_match_table = of_flash_match,
|
||||
},
|
||||
.probe = octeon_flash_probe,
|
||||
};
|
||||
|
||||
static int octeon_flash_init(void)
|
||||
{
|
||||
return platform_driver_register(&of_flash_driver);
|
||||
}
|
||||
late_initcall(octeon_flash_init);
|
||||
|
||||
MODULE_LICENSE("GPL");
|
||||
|
|
|
|||
|
|
@ -325,8 +325,14 @@ static void __init octeon_ehci_hw_start(struct device *dev)
|
|||
/* Use 64-bit addressing. */
|
||||
ehci_ctl.s.ehci_64b_addr_en = 1;
|
||||
ehci_ctl.s.l2c_addr_msb = 0;
|
||||
#ifdef __BIG_ENDIAN
|
||||
ehci_ctl.s.l2c_buff_emod = 1; /* Byte swapped. */
|
||||
ehci_ctl.s.l2c_desc_emod = 1; /* Byte swapped. */
|
||||
#else
|
||||
ehci_ctl.s.l2c_buff_emod = 0; /* not swapped. */
|
||||
ehci_ctl.s.l2c_desc_emod = 0; /* not swapped. */
|
||||
ehci_ctl.s.inv_reg_a2 = 1;
|
||||
#endif
|
||||
cvmx_write_csr(CVMX_UCTLX_EHCI_CTL(0), ehci_ctl.u64);
|
||||
|
||||
octeon2_usb_clocks_stop();
|
||||
|
|
@ -381,8 +387,14 @@ static void __init octeon_ohci_hw_start(struct device *dev)
|
|||
|
||||
ohci_ctl.u64 = cvmx_read_csr(CVMX_UCTLX_OHCI_CTL(0));
|
||||
ohci_ctl.s.l2c_addr_msb = 0;
|
||||
#ifdef __BIG_ENDIAN
|
||||
ohci_ctl.s.l2c_buff_emod = 1; /* Byte swapped. */
|
||||
ohci_ctl.s.l2c_desc_emod = 1; /* Byte swapped. */
|
||||
#else
|
||||
ohci_ctl.s.l2c_buff_emod = 0; /* not swapped. */
|
||||
ohci_ctl.s.l2c_desc_emod = 0; /* not swapped. */
|
||||
ohci_ctl.s.inv_reg_a2 = 1;
|
||||
#endif
|
||||
cvmx_write_csr(CVMX_UCTLX_OHCI_CTL(0), ohci_ctl.u64);
|
||||
|
||||
octeon2_usb_clocks_stop();
|
||||
|
|
@ -958,6 +970,13 @@ end_led:
|
|||
}
|
||||
}
|
||||
|
||||
if (octeon_bootinfo->board_type != CVMX_BOARD_TYPE_CUST_DSR1000N) {
|
||||
int dsr1000n_leds = fdt_path_offset(initial_boot_params,
|
||||
"/dsr1000n-leds");
|
||||
if (dsr1000n_leds >= 0)
|
||||
fdt_nop_node(initial_boot_params, dsr1000n_leds);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -37,11 +37,13 @@ struct boot_init_vector {
|
|||
|
||||
/* similar to bootloader's linux_app_boot_info but without global data */
|
||||
struct linux_app_boot_info {
|
||||
#ifdef __BIG_ENDIAN_BITFIELD
|
||||
uint32_t labi_signature;
|
||||
uint32_t start_core0_addr;
|
||||
uint32_t avail_coremask;
|
||||
uint32_t pci_console_active;
|
||||
uint32_t icache_prefetch_disable;
|
||||
uint32_t padding;
|
||||
uint64_t InitTLBStart_addr;
|
||||
uint32_t start_app_addr;
|
||||
uint32_t cur_exception_base;
|
||||
|
|
@ -49,6 +51,27 @@ struct linux_app_boot_info {
|
|||
uint32_t compact_flash_common_base_addr;
|
||||
uint32_t compact_flash_attribute_base_addr;
|
||||
uint32_t led_display_base_addr;
|
||||
#else
|
||||
uint32_t start_core0_addr;
|
||||
uint32_t labi_signature;
|
||||
|
||||
uint32_t pci_console_active;
|
||||
uint32_t avail_coremask;
|
||||
|
||||
uint32_t padding;
|
||||
uint32_t icache_prefetch_disable;
|
||||
|
||||
uint64_t InitTLBStart_addr;
|
||||
|
||||
uint32_t cur_exception_base;
|
||||
uint32_t start_app_addr;
|
||||
|
||||
uint32_t compact_flash_common_base_addr;
|
||||
uint32_t no_mark_private_data;
|
||||
|
||||
uint32_t led_display_base_addr;
|
||||
uint32_t compact_flash_attribute_base_addr;
|
||||
#endif
|
||||
};
|
||||
|
||||
/* If not to copy a lot of bootloader's structures
|
||||
|
|
|
|||
|
|
@ -51,6 +51,9 @@ extern void pci_console_init(const char *arg);
|
|||
|
||||
static unsigned long long MAX_MEMORY = 512ull << 20;
|
||||
|
||||
DEFINE_SEMAPHORE(octeon_bootbus_sem);
|
||||
EXPORT_SYMBOL(octeon_bootbus_sem);
|
||||
|
||||
struct octeon_boot_descriptor *octeon_boot_desc_ptr;
|
||||
|
||||
struct cvmx_bootinfo *octeon_bootinfo;
|
||||
|
|
@ -413,7 +416,10 @@ static void octeon_restart(char *command)
|
|||
|
||||
mb();
|
||||
while (1)
|
||||
cvmx_write_csr(CVMX_CIU_SOFT_RST, 1);
|
||||
if (OCTEON_IS_OCTEON3())
|
||||
cvmx_write_csr(CVMX_RST_SOFT_RST, 1);
|
||||
else
|
||||
cvmx_write_csr(CVMX_CIU_SOFT_RST, 1);
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -1043,7 +1049,7 @@ int prom_putchar(char c)
|
|||
}
|
||||
EXPORT_SYMBOL(prom_putchar);
|
||||
|
||||
void prom_free_prom_memory(void)
|
||||
void __init prom_free_prom_memory(void)
|
||||
{
|
||||
if (CAVIUM_OCTEON_DCACHE_PREFETCH_WAR) {
|
||||
/* Check for presence of Core-14449 fix. */
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
CONFIG_BCM3384=y
|
||||
CONFIG_BMIPS_GENERIC=y
|
||||
CONFIG_HIGHMEM=y
|
||||
CONFIG_SMP=y
|
||||
CONFIG_NR_CPUS=4
|
||||
|
|
@ -33,6 +33,7 @@ CONFIG_DEVTMPFS=y
|
|||
CONFIG_DEVTMPFS_MOUNT=y
|
||||
# CONFIG_STANDALONE is not set
|
||||
# CONFIG_PREVENT_FIRMWARE_BUILD is not set
|
||||
CONFIG_BRCMSTB_GISB_ARB=y
|
||||
CONFIG_MTD=y
|
||||
CONFIG_MTD_CFI=y
|
||||
CONFIG_MTD_CFI_INTELEXT=y
|
||||
|
|
@ -43,15 +44,19 @@ CONFIG_SCSI=y
|
|||
CONFIG_BLK_DEV_SD=y
|
||||
# CONFIG_SCSI_LOWLEVEL is not set
|
||||
CONFIG_NETDEVICES=y
|
||||
CONFIG_BCMGENET=y
|
||||
CONFIG_USB_USBNET=y
|
||||
# CONFIG_INPUT is not set
|
||||
# CONFIG_SERIO is not set
|
||||
# CONFIG_VT is not set
|
||||
# CONFIG_DEVKMEM is not set
|
||||
CONFIG_SERIAL_EARLYCON_FORCE=y
|
||||
CONFIG_SERIAL_BCM63XX=y
|
||||
CONFIG_SERIAL_BCM63XX_CONSOLE=y
|
||||
# CONFIG_HW_RANDOM is not set
|
||||
CONFIG_POWER_SUPPLY=y
|
||||
CONFIG_POWER_RESET=y
|
||||
CONFIG_POWER_RESET_BRCMSTB=y
|
||||
CONFIG_POWER_RESET_SYSCON=y
|
||||
# CONFIG_HWMON is not set
|
||||
CONFIG_USB=y
|
||||
CONFIG_USB_EHCI_HCD=y
|
||||
|
|
@ -75,4 +80,6 @@ CONFIG_NLS_ASCII=y
|
|||
CONFIG_NLS_ISO8859_1=y
|
||||
CONFIG_DEBUG_FS=y
|
||||
CONFIG_MAGIC_SYSRQ=y
|
||||
CONFIG_CMDLINE_BOOL=y
|
||||
CONFIG_CMDLINE="earlycon"
|
||||
# CONFIG_CRYPTO_HW is not set
|
||||
|
|
@ -0,0 +1,88 @@
|
|||
CONFIG_BMIPS_GENERIC=y
|
||||
CONFIG_CPU_LITTLE_ENDIAN=y
|
||||
CONFIG_HIGHMEM=y
|
||||
CONFIG_SMP=y
|
||||
CONFIG_NR_CPUS=4
|
||||
# CONFIG_SECCOMP is not set
|
||||
CONFIG_MIPS_O32_FP64_SUPPORT=y
|
||||
# CONFIG_LOCALVERSION_AUTO is not set
|
||||
# CONFIG_SWAP is not set
|
||||
CONFIG_NO_HZ=y
|
||||
CONFIG_BLK_DEV_INITRD=y
|
||||
# CONFIG_RD_GZIP is not set
|
||||
CONFIG_EXPERT=y
|
||||
# CONFIG_VM_EVENT_COUNTERS is not set
|
||||
# CONFIG_SLUB_DEBUG is not set
|
||||
# CONFIG_BLK_DEV_BSG is not set
|
||||
# CONFIG_IOSCHED_DEADLINE is not set
|
||||
# CONFIG_IOSCHED_CFQ is not set
|
||||
CONFIG_NET=y
|
||||
CONFIG_PACKET=y
|
||||
CONFIG_PACKET_DIAG=y
|
||||
CONFIG_UNIX=y
|
||||
CONFIG_INET=y
|
||||
# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
|
||||
# CONFIG_INET_XFRM_MODE_TUNNEL is not set
|
||||
# CONFIG_INET_XFRM_MODE_BEET is not set
|
||||
# CONFIG_INET_LRO is not set
|
||||
# CONFIG_INET_DIAG is not set
|
||||
CONFIG_CFG80211=y
|
||||
CONFIG_NL80211_TESTMODE=y
|
||||
CONFIG_MAC80211=y
|
||||
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
|
||||
CONFIG_DEVTMPFS=y
|
||||
CONFIG_DEVTMPFS_MOUNT=y
|
||||
# CONFIG_STANDALONE is not set
|
||||
# CONFIG_PREVENT_FIRMWARE_BUILD is not set
|
||||
CONFIG_BRCMSTB_GISB_ARB=y
|
||||
CONFIG_MTD=y
|
||||
CONFIG_MTD_CFI=y
|
||||
CONFIG_MTD_CFI_INTELEXT=y
|
||||
CONFIG_MTD_CFI_AMDSTD=y
|
||||
CONFIG_MTD_PHYSMAP=y
|
||||
# CONFIG_BLK_DEV is not set
|
||||
CONFIG_SCSI=y
|
||||
CONFIG_BLK_DEV_SD=y
|
||||
# CONFIG_SCSI_LOWLEVEL is not set
|
||||
CONFIG_NETDEVICES=y
|
||||
CONFIG_BCMGENET=y
|
||||
CONFIG_USB_USBNET=y
|
||||
# CONFIG_INPUT is not set
|
||||
# CONFIG_SERIO is not set
|
||||
# CONFIG_VT is not set
|
||||
# CONFIG_DEVKMEM is not set
|
||||
CONFIG_SERIAL_8250=y
|
||||
# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set
|
||||
CONFIG_SERIAL_8250_CONSOLE=y
|
||||
CONFIG_SERIAL_OF_PLATFORM=y
|
||||
# CONFIG_HW_RANDOM is not set
|
||||
CONFIG_POWER_SUPPLY=y
|
||||
CONFIG_POWER_RESET=y
|
||||
CONFIG_POWER_RESET_BRCMSTB=y
|
||||
CONFIG_POWER_RESET_SYSCON=y
|
||||
# CONFIG_HWMON is not set
|
||||
CONFIG_USB=y
|
||||
CONFIG_USB_EHCI_HCD=y
|
||||
# CONFIG_USB_EHCI_TT_NEWSCHED is not set
|
||||
CONFIG_USB_EHCI_HCD_PLATFORM=y
|
||||
CONFIG_USB_OHCI_HCD=y
|
||||
CONFIG_USB_OHCI_HCD_PLATFORM=y
|
||||
CONFIG_USB_STORAGE=y
|
||||
CONFIG_EXT4_FS=y
|
||||
CONFIG_EXT4_FS_POSIX_ACL=y
|
||||
CONFIG_EXT4_FS_SECURITY=y
|
||||
# CONFIG_DNOTIFY is not set
|
||||
CONFIG_FUSE_FS=y
|
||||
CONFIG_VFAT_FS=y
|
||||
CONFIG_PROC_KCORE=y
|
||||
CONFIG_TMPFS=y
|
||||
CONFIG_NFS_FS=y
|
||||
CONFIG_CIFS=y
|
||||
CONFIG_NLS_CODEPAGE_437=y
|
||||
CONFIG_NLS_ASCII=y
|
||||
CONFIG_NLS_ISO8859_1=y
|
||||
CONFIG_DEBUG_FS=y
|
||||
CONFIG_MAGIC_SYSRQ=y
|
||||
CONFIG_CMDLINE_BOOL=y
|
||||
CONFIG_CMDLINE="earlycon"
|
||||
# CONFIG_CRYPTO_HW is not set
|
||||
|
|
@ -0,0 +1,439 @@
|
|||
CONFIG_MIPS_MALTA=y
|
||||
CONFIG_CPU_LITTLE_ENDIAN=y
|
||||
CONFIG_CPU_MIPS32_R2=y
|
||||
CONFIG_CPU_MIPS32_R5_FEATURES=y
|
||||
CONFIG_CPU_MIPS32_R5_XPA=y
|
||||
CONFIG_PAGE_SIZE_16KB=y
|
||||
CONFIG_HZ_100=y
|
||||
CONFIG_SYSVIPC=y
|
||||
CONFIG_NO_HZ=y
|
||||
CONFIG_HIGH_RES_TIMERS=y
|
||||
CONFIG_IKCONFIG=y
|
||||
CONFIG_IKCONFIG_PROC=y
|
||||
CONFIG_LOG_BUF_SHIFT=15
|
||||
CONFIG_NAMESPACES=y
|
||||
CONFIG_RELAY=y
|
||||
CONFIG_EXPERT=y
|
||||
# CONFIG_COMPAT_BRK is not set
|
||||
CONFIG_SLAB=y
|
||||
CONFIG_MODULES=y
|
||||
CONFIG_MODULE_UNLOAD=y
|
||||
CONFIG_MODVERSIONS=y
|
||||
CONFIG_MODULE_SRCVERSION_ALL=y
|
||||
CONFIG_PCI=y
|
||||
CONFIG_NET=y
|
||||
CONFIG_PACKET=y
|
||||
CONFIG_UNIX=y
|
||||
CONFIG_XFRM_USER=m
|
||||
CONFIG_NET_KEY=y
|
||||
CONFIG_NET_KEY_MIGRATE=y
|
||||
CONFIG_INET=y
|
||||
CONFIG_IP_MULTICAST=y
|
||||
CONFIG_IP_ADVANCED_ROUTER=y
|
||||
CONFIG_IP_MULTIPLE_TABLES=y
|
||||
CONFIG_IP_ROUTE_MULTIPATH=y
|
||||
CONFIG_IP_ROUTE_VERBOSE=y
|
||||
CONFIG_IP_PNP=y
|
||||
CONFIG_IP_PNP_DHCP=y
|
||||
CONFIG_IP_PNP_BOOTP=y
|
||||
CONFIG_NET_IPIP=m
|
||||
CONFIG_IP_MROUTE=y
|
||||
CONFIG_IP_PIMSM_V1=y
|
||||
CONFIG_IP_PIMSM_V2=y
|
||||
CONFIG_SYN_COOKIES=y
|
||||
CONFIG_INET_AH=m
|
||||
CONFIG_INET_ESP=m
|
||||
CONFIG_INET_IPCOMP=m
|
||||
CONFIG_INET_XFRM_MODE_TRANSPORT=m
|
||||
CONFIG_INET_XFRM_MODE_TUNNEL=m
|
||||
CONFIG_TCP_MD5SIG=y
|
||||
CONFIG_IPV6_ROUTER_PREF=y
|
||||
CONFIG_IPV6_ROUTE_INFO=y
|
||||
CONFIG_IPV6_OPTIMISTIC_DAD=y
|
||||
CONFIG_INET6_AH=m
|
||||
CONFIG_INET6_ESP=m
|
||||
CONFIG_INET6_IPCOMP=m
|
||||
CONFIG_IPV6_TUNNEL=m
|
||||
CONFIG_IPV6_MROUTE=y
|
||||
CONFIG_IPV6_PIMSM_V2=y
|
||||
CONFIG_NETWORK_SECMARK=y
|
||||
CONFIG_NETFILTER=y
|
||||
CONFIG_NF_CONNTRACK=m
|
||||
CONFIG_NF_CONNTRACK_SECMARK=y
|
||||
CONFIG_NF_CONNTRACK_EVENTS=y
|
||||
CONFIG_NF_CT_PROTO_DCCP=m
|
||||
CONFIG_NF_CT_PROTO_UDPLITE=m
|
||||
CONFIG_NF_CONNTRACK_AMANDA=m
|
||||
CONFIG_NF_CONNTRACK_FTP=m
|
||||
CONFIG_NF_CONNTRACK_H323=m
|
||||
CONFIG_NF_CONNTRACK_IRC=m
|
||||
CONFIG_NF_CONNTRACK_PPTP=m
|
||||
CONFIG_NF_CONNTRACK_SANE=m
|
||||
CONFIG_NF_CONNTRACK_SIP=m
|
||||
CONFIG_NF_CONNTRACK_TFTP=m
|
||||
CONFIG_NF_CT_NETLINK=m
|
||||
CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
|
||||
CONFIG_NETFILTER_XT_TARGET_CONNMARK=m
|
||||
CONFIG_NETFILTER_XT_TARGET_MARK=m
|
||||
CONFIG_NETFILTER_XT_TARGET_NFLOG=m
|
||||
CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
|
||||
CONFIG_NETFILTER_XT_TARGET_TRACE=m
|
||||
CONFIG_NETFILTER_XT_TARGET_SECMARK=m
|
||||
CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
|
||||
CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m
|
||||
CONFIG_NETFILTER_XT_MATCH_COMMENT=m
|
||||
CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m
|
||||
CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m
|
||||
CONFIG_NETFILTER_XT_MATCH_CONNMARK=m
|
||||
CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
|
||||
CONFIG_NETFILTER_XT_MATCH_DCCP=m
|
||||
CONFIG_NETFILTER_XT_MATCH_ESP=m
|
||||
CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m
|
||||
CONFIG_NETFILTER_XT_MATCH_HELPER=m
|
||||
CONFIG_NETFILTER_XT_MATCH_IPRANGE=m
|
||||
CONFIG_NETFILTER_XT_MATCH_LENGTH=m
|
||||
CONFIG_NETFILTER_XT_MATCH_LIMIT=m
|
||||
CONFIG_NETFILTER_XT_MATCH_MAC=m
|
||||
CONFIG_NETFILTER_XT_MATCH_MARK=m
|
||||
CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m
|
||||
CONFIG_NETFILTER_XT_MATCH_OWNER=m
|
||||
CONFIG_NETFILTER_XT_MATCH_POLICY=m
|
||||
CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m
|
||||
CONFIG_NETFILTER_XT_MATCH_QUOTA=m
|
||||
CONFIG_NETFILTER_XT_MATCH_RATEEST=m
|
||||
CONFIG_NETFILTER_XT_MATCH_REALM=m
|
||||
CONFIG_NETFILTER_XT_MATCH_RECENT=m
|
||||
CONFIG_NETFILTER_XT_MATCH_STATE=m
|
||||
CONFIG_NETFILTER_XT_MATCH_STATISTIC=m
|
||||
CONFIG_NETFILTER_XT_MATCH_STRING=m
|
||||
CONFIG_NETFILTER_XT_MATCH_TCPMSS=m
|
||||
CONFIG_NETFILTER_XT_MATCH_TIME=m
|
||||
CONFIG_NETFILTER_XT_MATCH_U32=m
|
||||
CONFIG_IP_VS=m
|
||||
CONFIG_IP_VS_IPV6=y
|
||||
CONFIG_IP_VS_PROTO_TCP=y
|
||||
CONFIG_IP_VS_PROTO_UDP=y
|
||||
CONFIG_IP_VS_PROTO_ESP=y
|
||||
CONFIG_IP_VS_PROTO_AH=y
|
||||
CONFIG_IP_VS_RR=m
|
||||
CONFIG_IP_VS_WRR=m
|
||||
CONFIG_IP_VS_LC=m
|
||||
CONFIG_IP_VS_WLC=m
|
||||
CONFIG_IP_VS_LBLC=m
|
||||
CONFIG_IP_VS_LBLCR=m
|
||||
CONFIG_IP_VS_DH=m
|
||||
CONFIG_IP_VS_SH=m
|
||||
CONFIG_IP_VS_SED=m
|
||||
CONFIG_IP_VS_NQ=m
|
||||
CONFIG_NF_CONNTRACK_IPV4=m
|
||||
CONFIG_IP_NF_IPTABLES=m
|
||||
CONFIG_IP_NF_MATCH_AH=m
|
||||
CONFIG_IP_NF_MATCH_ECN=m
|
||||
CONFIG_IP_NF_MATCH_TTL=m
|
||||
CONFIG_IP_NF_FILTER=m
|
||||
CONFIG_IP_NF_TARGET_REJECT=m
|
||||
CONFIG_IP_NF_MANGLE=m
|
||||
CONFIG_IP_NF_TARGET_CLUSTERIP=m
|
||||
CONFIG_IP_NF_TARGET_ECN=m
|
||||
CONFIG_IP_NF_TARGET_TTL=m
|
||||
CONFIG_IP_NF_RAW=m
|
||||
CONFIG_IP_NF_ARPTABLES=m
|
||||
CONFIG_IP_NF_ARPFILTER=m
|
||||
CONFIG_IP_NF_ARP_MANGLE=m
|
||||
CONFIG_NF_CONNTRACK_IPV6=m
|
||||
CONFIG_IP6_NF_MATCH_AH=m
|
||||
CONFIG_IP6_NF_MATCH_EUI64=m
|
||||
CONFIG_IP6_NF_MATCH_FRAG=m
|
||||
CONFIG_IP6_NF_MATCH_OPTS=m
|
||||
CONFIG_IP6_NF_MATCH_HL=m
|
||||
CONFIG_IP6_NF_MATCH_IPV6HEADER=m
|
||||
CONFIG_IP6_NF_MATCH_MH=m
|
||||
CONFIG_IP6_NF_MATCH_RT=m
|
||||
CONFIG_IP6_NF_TARGET_HL=m
|
||||
CONFIG_IP6_NF_FILTER=m
|
||||
CONFIG_IP6_NF_TARGET_REJECT=m
|
||||
CONFIG_IP6_NF_MANGLE=m
|
||||
CONFIG_IP6_NF_RAW=m
|
||||
CONFIG_BRIDGE_NF_EBTABLES=m
|
||||
CONFIG_BRIDGE_EBT_BROUTE=m
|
||||
CONFIG_BRIDGE_EBT_T_FILTER=m
|
||||
CONFIG_BRIDGE_EBT_T_NAT=m
|
||||
CONFIG_BRIDGE_EBT_802_3=m
|
||||
CONFIG_BRIDGE_EBT_AMONG=m
|
||||
CONFIG_BRIDGE_EBT_ARP=m
|
||||
CONFIG_BRIDGE_EBT_IP=m
|
||||
CONFIG_BRIDGE_EBT_IP6=m
|
||||
CONFIG_BRIDGE_EBT_LIMIT=m
|
||||
CONFIG_BRIDGE_EBT_MARK=m
|
||||
CONFIG_BRIDGE_EBT_PKTTYPE=m
|
||||
CONFIG_BRIDGE_EBT_STP=m
|
||||
CONFIG_BRIDGE_EBT_VLAN=m
|
||||
CONFIG_BRIDGE_EBT_ARPREPLY=m
|
||||
CONFIG_BRIDGE_EBT_DNAT=m
|
||||
CONFIG_BRIDGE_EBT_MARK_T=m
|
||||
CONFIG_BRIDGE_EBT_REDIRECT=m
|
||||
CONFIG_BRIDGE_EBT_SNAT=m
|
||||
CONFIG_BRIDGE_EBT_LOG=m
|
||||
CONFIG_BRIDGE_EBT_NFLOG=m
|
||||
CONFIG_IP_SCTP=m
|
||||
CONFIG_BRIDGE=m
|
||||
CONFIG_VLAN_8021Q=m
|
||||
CONFIG_VLAN_8021Q_GVRP=y
|
||||
CONFIG_ATALK=m
|
||||
CONFIG_DEV_APPLETALK=m
|
||||
CONFIG_IPDDP=m
|
||||
CONFIG_IPDDP_ENCAP=y
|
||||
CONFIG_PHONET=m
|
||||
CONFIG_NET_SCHED=y
|
||||
CONFIG_NET_SCH_CBQ=m
|
||||
CONFIG_NET_SCH_HTB=m
|
||||
CONFIG_NET_SCH_HFSC=m
|
||||
CONFIG_NET_SCH_PRIO=m
|
||||
CONFIG_NET_SCH_RED=m
|
||||
CONFIG_NET_SCH_SFQ=m
|
||||
CONFIG_NET_SCH_TEQL=m
|
||||
CONFIG_NET_SCH_TBF=m
|
||||
CONFIG_NET_SCH_GRED=m
|
||||
CONFIG_NET_SCH_DSMARK=m
|
||||
CONFIG_NET_SCH_NETEM=m
|
||||
CONFIG_NET_SCH_INGRESS=m
|
||||
CONFIG_NET_CLS_BASIC=m
|
||||
CONFIG_NET_CLS_TCINDEX=m
|
||||
CONFIG_NET_CLS_ROUTE4=m
|
||||
CONFIG_NET_CLS_FW=m
|
||||
CONFIG_NET_CLS_U32=m
|
||||
CONFIG_NET_CLS_RSVP=m
|
||||
CONFIG_NET_CLS_RSVP6=m
|
||||
CONFIG_NET_CLS_FLOW=m
|
||||
CONFIG_NET_CLS_ACT=y
|
||||
CONFIG_NET_ACT_POLICE=y
|
||||
CONFIG_NET_ACT_GACT=m
|
||||
CONFIG_GACT_PROB=y
|
||||
CONFIG_NET_ACT_MIRRED=m
|
||||
CONFIG_NET_ACT_IPT=m
|
||||
CONFIG_NET_ACT_NAT=m
|
||||
CONFIG_NET_ACT_PEDIT=m
|
||||
CONFIG_NET_ACT_SIMP=m
|
||||
CONFIG_NET_ACT_SKBEDIT=m
|
||||
CONFIG_NET_CLS_IND=y
|
||||
CONFIG_CFG80211=m
|
||||
CONFIG_MAC80211=m
|
||||
CONFIG_MAC80211_MESH=y
|
||||
CONFIG_RFKILL=m
|
||||
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
|
||||
CONFIG_DEVTMPFS=y
|
||||
CONFIG_DEVTMPFS_MOUNT=y
|
||||
CONFIG_CONNECTOR=m
|
||||
CONFIG_MTD=y
|
||||
CONFIG_MTD_BLOCK=y
|
||||
CONFIG_MTD_OOPS=m
|
||||
CONFIG_MTD_CFI=y
|
||||
CONFIG_MTD_CFI_INTELEXT=y
|
||||
CONFIG_MTD_CFI_AMDSTD=y
|
||||
CONFIG_MTD_CFI_STAA=y
|
||||
CONFIG_MTD_PHYSMAP=y
|
||||
CONFIG_MTD_UBI=m
|
||||
CONFIG_MTD_UBI_GLUEBI=m
|
||||
CONFIG_BLK_DEV_FD=m
|
||||
CONFIG_BLK_DEV_UMEM=m
|
||||
CONFIG_BLK_DEV_LOOP=m
|
||||
CONFIG_BLK_DEV_CRYPTOLOOP=m
|
||||
CONFIG_BLK_DEV_NBD=m
|
||||
CONFIG_BLK_DEV_RAM=y
|
||||
CONFIG_CDROM_PKTCDVD=m
|
||||
CONFIG_ATA_OVER_ETH=m
|
||||
CONFIG_IDE=y
|
||||
CONFIG_BLK_DEV_IDECD=y
|
||||
CONFIG_IDE_GENERIC=y
|
||||
CONFIG_BLK_DEV_GENERIC=y
|
||||
CONFIG_BLK_DEV_PIIX=y
|
||||
CONFIG_BLK_DEV_IT8213=m
|
||||
CONFIG_BLK_DEV_TC86C001=m
|
||||
CONFIG_RAID_ATTRS=m
|
||||
CONFIG_SCSI=m
|
||||
CONFIG_BLK_DEV_SD=m
|
||||
CONFIG_CHR_DEV_ST=m
|
||||
CONFIG_CHR_DEV_OSST=m
|
||||
CONFIG_BLK_DEV_SR=m
|
||||
CONFIG_BLK_DEV_SR_VENDOR=y
|
||||
CONFIG_CHR_DEV_SG=m
|
||||
CONFIG_SCSI_CONSTANTS=y
|
||||
CONFIG_SCSI_LOGGING=y
|
||||
CONFIG_SCSI_SCAN_ASYNC=y
|
||||
CONFIG_SCSI_FC_ATTRS=m
|
||||
CONFIG_ISCSI_TCP=m
|
||||
CONFIG_BLK_DEV_3W_XXXX_RAID=m
|
||||
CONFIG_SCSI_3W_9XXX=m
|
||||
CONFIG_SCSI_ACARD=m
|
||||
CONFIG_SCSI_AACRAID=m
|
||||
CONFIG_SCSI_AIC7XXX=m
|
||||
CONFIG_AIC7XXX_RESET_DELAY_MS=15000
|
||||
# CONFIG_AIC7XXX_DEBUG_ENABLE is not set
|
||||
CONFIG_MD=y
|
||||
CONFIG_BLK_DEV_MD=m
|
||||
CONFIG_MD_LINEAR=m
|
||||
CONFIG_MD_RAID0=m
|
||||
CONFIG_MD_RAID1=m
|
||||
CONFIG_MD_RAID10=m
|
||||
CONFIG_MD_RAID456=m
|
||||
CONFIG_MD_MULTIPATH=m
|
||||
CONFIG_MD_FAULTY=m
|
||||
CONFIG_BLK_DEV_DM=m
|
||||
CONFIG_DM_CRYPT=m
|
||||
CONFIG_DM_SNAPSHOT=m
|
||||
CONFIG_DM_MIRROR=m
|
||||
CONFIG_DM_ZERO=m
|
||||
CONFIG_DM_MULTIPATH=m
|
||||
CONFIG_NETDEVICES=y
|
||||
CONFIG_BONDING=m
|
||||
CONFIG_DUMMY=m
|
||||
CONFIG_EQUALIZER=m
|
||||
CONFIG_IFB=m
|
||||
CONFIG_MACVLAN=m
|
||||
CONFIG_TUN=m
|
||||
CONFIG_VETH=m
|
||||
# CONFIG_NET_VENDOR_3COM is not set
|
||||
CONFIG_PCNET32=y
|
||||
CONFIG_CHELSIO_T3=m
|
||||
CONFIG_AX88796=m
|
||||
CONFIG_NETXEN_NIC=m
|
||||
CONFIG_TC35815=m
|
||||
CONFIG_MARVELL_PHY=m
|
||||
CONFIG_DAVICOM_PHY=m
|
||||
CONFIG_QSEMI_PHY=m
|
||||
CONFIG_LXT_PHY=m
|
||||
CONFIG_CICADA_PHY=m
|
||||
CONFIG_VITESSE_PHY=m
|
||||
CONFIG_SMSC_PHY=m
|
||||
CONFIG_BROADCOM_PHY=m
|
||||
CONFIG_ICPLUS_PHY=m
|
||||
CONFIG_REALTEK_PHY=m
|
||||
CONFIG_ATMEL=m
|
||||
CONFIG_PCI_ATMEL=m
|
||||
CONFIG_PRISM54=m
|
||||
CONFIG_HOSTAP=m
|
||||
CONFIG_HOSTAP_FIRMWARE=y
|
||||
CONFIG_HOSTAP_FIRMWARE_NVRAM=y
|
||||
CONFIG_HOSTAP_PLX=m
|
||||
CONFIG_HOSTAP_PCI=m
|
||||
CONFIG_IPW2100=m
|
||||
CONFIG_IPW2100_MONITOR=y
|
||||
CONFIG_LIBERTAS=m
|
||||
# CONFIG_INPUT_KEYBOARD is not set
|
||||
# CONFIG_INPUT_MOUSE is not set
|
||||
# CONFIG_SERIO_I8042 is not set
|
||||
CONFIG_SERIAL_8250=y
|
||||
CONFIG_SERIAL_8250_CONSOLE=y
|
||||
# CONFIG_HWMON is not set
|
||||
CONFIG_FB=y
|
||||
CONFIG_FB_CIRRUS=y
|
||||
# CONFIG_VGA_CONSOLE is not set
|
||||
CONFIG_FRAMEBUFFER_CONSOLE=y
|
||||
CONFIG_HID=m
|
||||
CONFIG_RTC_CLASS=y
|
||||
CONFIG_RTC_DRV_CMOS=y
|
||||
CONFIG_UIO=m
|
||||
CONFIG_UIO_CIF=m
|
||||
CONFIG_EXT2_FS=y
|
||||
CONFIG_EXT3_FS=y
|
||||
CONFIG_REISERFS_FS=m
|
||||
CONFIG_REISERFS_PROC_INFO=y
|
||||
CONFIG_REISERFS_FS_XATTR=y
|
||||
CONFIG_REISERFS_FS_POSIX_ACL=y
|
||||
CONFIG_REISERFS_FS_SECURITY=y
|
||||
CONFIG_JFS_FS=m
|
||||
CONFIG_JFS_POSIX_ACL=y
|
||||
CONFIG_JFS_SECURITY=y
|
||||
CONFIG_XFS_FS=m
|
||||
CONFIG_XFS_QUOTA=y
|
||||
CONFIG_XFS_POSIX_ACL=y
|
||||
CONFIG_QUOTA=y
|
||||
CONFIG_QFMT_V2=y
|
||||
CONFIG_FUSE_FS=m
|
||||
CONFIG_ISO9660_FS=m
|
||||
CONFIG_JOLIET=y
|
||||
CONFIG_ZISOFS=y
|
||||
CONFIG_UDF_FS=m
|
||||
CONFIG_MSDOS_FS=m
|
||||
CONFIG_VFAT_FS=m
|
||||
CONFIG_PROC_KCORE=y
|
||||
CONFIG_TMPFS=y
|
||||
CONFIG_AFFS_FS=m
|
||||
CONFIG_HFS_FS=m
|
||||
CONFIG_HFSPLUS_FS=m
|
||||
CONFIG_BEFS_FS=m
|
||||
CONFIG_BFS_FS=m
|
||||
CONFIG_EFS_FS=m
|
||||
CONFIG_JFFS2_FS=m
|
||||
CONFIG_JFFS2_FS_XATTR=y
|
||||
CONFIG_JFFS2_COMPRESSION_OPTIONS=y
|
||||
CONFIG_JFFS2_RUBIN=y
|
||||
CONFIG_CRAMFS=m
|
||||
CONFIG_VXFS_FS=m
|
||||
CONFIG_MINIX_FS=m
|
||||
CONFIG_ROMFS_FS=m
|
||||
CONFIG_SYSV_FS=m
|
||||
CONFIG_UFS_FS=m
|
||||
CONFIG_NFS_FS=y
|
||||
CONFIG_ROOT_NFS=y
|
||||
CONFIG_NFSD=y
|
||||
CONFIG_NFSD_V3=y
|
||||
CONFIG_NLS_CODEPAGE_437=m
|
||||
CONFIG_NLS_CODEPAGE_737=m
|
||||
CONFIG_NLS_CODEPAGE_775=m
|
||||
CONFIG_NLS_CODEPAGE_850=m
|
||||
CONFIG_NLS_CODEPAGE_852=m
|
||||
CONFIG_NLS_CODEPAGE_855=m
|
||||
CONFIG_NLS_CODEPAGE_857=m
|
||||
CONFIG_NLS_CODEPAGE_860=m
|
||||
CONFIG_NLS_CODEPAGE_861=m
|
||||
CONFIG_NLS_CODEPAGE_862=m
|
||||
CONFIG_NLS_CODEPAGE_863=m
|
||||
CONFIG_NLS_CODEPAGE_864=m
|
||||
CONFIG_NLS_CODEPAGE_865=m
|
||||
CONFIG_NLS_CODEPAGE_866=m
|
||||
CONFIG_NLS_CODEPAGE_869=m
|
||||
CONFIG_NLS_CODEPAGE_936=m
|
||||
CONFIG_NLS_CODEPAGE_950=m
|
||||
CONFIG_NLS_CODEPAGE_932=m
|
||||
CONFIG_NLS_CODEPAGE_949=m
|
||||
CONFIG_NLS_CODEPAGE_874=m
|
||||
CONFIG_NLS_ISO8859_8=m
|
||||
CONFIG_NLS_CODEPAGE_1250=m
|
||||
CONFIG_NLS_CODEPAGE_1251=m
|
||||
CONFIG_NLS_ASCII=m
|
||||
CONFIG_NLS_ISO8859_1=m
|
||||
CONFIG_NLS_ISO8859_2=m
|
||||
CONFIG_NLS_ISO8859_3=m
|
||||
CONFIG_NLS_ISO8859_4=m
|
||||
CONFIG_NLS_ISO8859_5=m
|
||||
CONFIG_NLS_ISO8859_6=m
|
||||
CONFIG_NLS_ISO8859_7=m
|
||||
CONFIG_NLS_ISO8859_9=m
|
||||
CONFIG_NLS_ISO8859_13=m
|
||||
CONFIG_NLS_ISO8859_14=m
|
||||
CONFIG_NLS_ISO8859_15=m
|
||||
CONFIG_NLS_KOI8_R=m
|
||||
CONFIG_NLS_KOI8_U=m
|
||||
CONFIG_CRYPTO_CRYPTD=m
|
||||
CONFIG_CRYPTO_LRW=m
|
||||
CONFIG_CRYPTO_PCBC=m
|
||||
CONFIG_CRYPTO_HMAC=y
|
||||
CONFIG_CRYPTO_XCBC=m
|
||||
CONFIG_CRYPTO_MD4=m
|
||||
CONFIG_CRYPTO_SHA256=m
|
||||
CONFIG_CRYPTO_SHA512=m
|
||||
CONFIG_CRYPTO_TGR192=m
|
||||
CONFIG_CRYPTO_WP512=m
|
||||
CONFIG_CRYPTO_ANUBIS=m
|
||||
CONFIG_CRYPTO_BLOWFISH=m
|
||||
CONFIG_CRYPTO_CAMELLIA=m
|
||||
CONFIG_CRYPTO_CAST5=m
|
||||
CONFIG_CRYPTO_CAST6=m
|
||||
CONFIG_CRYPTO_FCRYPT=m
|
||||
CONFIG_CRYPTO_KHAZAD=m
|
||||
CONFIG_CRYPTO_SERPENT=m
|
||||
CONFIG_CRYPTO_TEA=m
|
||||
CONFIG_CRYPTO_TWOFISH=m
|
||||
# CONFIG_CRYPTO_ANSI_CPRNG is not set
|
||||
CONFIG_CRC16=m
|
||||
|
|
@ -0,0 +1,336 @@
|
|||
CONFIG_MACH_PISTACHIO=y
|
||||
CONFIG_MIPS_MT_SMP=y
|
||||
CONFIG_MIPS_CPS=y
|
||||
# CONFIG_COMPACTION is not set
|
||||
CONFIG_DEFAULT_MMAP_MIN_ADDR=32768
|
||||
CONFIG_ZSMALLOC=y
|
||||
CONFIG_NR_CPUS=4
|
||||
CONFIG_PREEMPT_VOLUNTARY=y
|
||||
# CONFIG_LOCALVERSION_AUTO is not set
|
||||
CONFIG_DEFAULT_HOSTNAME="localhost"
|
||||
CONFIG_SYSVIPC=y
|
||||
CONFIG_NO_HZ=y
|
||||
CONFIG_HIGH_RES_TIMERS=y
|
||||
CONFIG_IKCONFIG=m
|
||||
CONFIG_IKCONFIG_PROC=y
|
||||
CONFIG_LOG_BUF_SHIFT=18
|
||||
CONFIG_CGROUPS=y
|
||||
CONFIG_CGROUP_FREEZER=y
|
||||
CONFIG_CGROUP_SCHED=y
|
||||
CONFIG_CFS_BANDWIDTH=y
|
||||
CONFIG_NAMESPACES=y
|
||||
CONFIG_USER_NS=y
|
||||
CONFIG_BLK_DEV_INITRD=y
|
||||
# CONFIG_RD_BZIP2 is not set
|
||||
# CONFIG_RD_LZMA is not set
|
||||
# CONFIG_RD_LZO is not set
|
||||
# CONFIG_RD_LZ4 is not set
|
||||
CONFIG_CC_OPTIMIZE_FOR_SIZE=y
|
||||
CONFIG_EMBEDDED=y
|
||||
# CONFIG_COMPAT_BRK is not set
|
||||
CONFIG_PROFILING=y
|
||||
CONFIG_CC_STACKPROTECTOR_STRONG=y
|
||||
CONFIG_MODULES=y
|
||||
CONFIG_MODULE_UNLOAD=y
|
||||
CONFIG_MODULE_FORCE_UNLOAD=y
|
||||
CONFIG_PARTITION_ADVANCED=y
|
||||
CONFIG_PM_DEBUG=y
|
||||
CONFIG_PM_ADVANCED_DEBUG=y
|
||||
CONFIG_CPU_IDLE=y
|
||||
# CONFIG_MIPS_CPS_CPUIDLE is not set
|
||||
CONFIG_NET=y
|
||||
CONFIG_PACKET=y
|
||||
CONFIG_UNIX=y
|
||||
CONFIG_NET_KEY=m
|
||||
CONFIG_INET=y
|
||||
CONFIG_IP_MULTICAST=y
|
||||
CONFIG_IP_ADVANCED_ROUTER=y
|
||||
CONFIG_IP_MULTIPLE_TABLES=y
|
||||
CONFIG_IP_ROUTE_MULTIPATH=y
|
||||
CONFIG_IP_ROUTE_VERBOSE=y
|
||||
CONFIG_IP_MROUTE=y
|
||||
CONFIG_IP_PIMSM_V1=y
|
||||
CONFIG_IP_PIMSM_V2=y
|
||||
CONFIG_SYN_COOKIES=y
|
||||
CONFIG_INET_AH=m
|
||||
CONFIG_INET_ESP=m
|
||||
CONFIG_INET_IPCOMP=m
|
||||
CONFIG_INET_XFRM_MODE_TRANSPORT=m
|
||||
CONFIG_INET_XFRM_MODE_TUNNEL=m
|
||||
CONFIG_INET_XFRM_MODE_BEET=m
|
||||
# CONFIG_INET_DIAG is not set
|
||||
CONFIG_TCP_CONG_ADVANCED=y
|
||||
# CONFIG_TCP_CONG_BIC is not set
|
||||
# CONFIG_TCP_CONG_WESTWOOD is not set
|
||||
# CONFIG_TCP_CONG_HTCP is not set
|
||||
CONFIG_TCP_CONG_LP=m
|
||||
CONFIG_TCP_MD5SIG=y
|
||||
CONFIG_IPV6=y
|
||||
CONFIG_INET6_AH=m
|
||||
CONFIG_INET6_ESP=m
|
||||
CONFIG_INET6_XFRM_MODE_TRANSPORT=m
|
||||
CONFIG_INET6_XFRM_MODE_TUNNEL=m
|
||||
CONFIG_INET6_XFRM_MODE_BEET=m
|
||||
CONFIG_IPV6_SIT=m
|
||||
CONFIG_NETWORK_SECMARK=y
|
||||
CONFIG_NETFILTER=y
|
||||
# CONFIG_BRIDGE_NETFILTER is not set
|
||||
CONFIG_NF_CONNTRACK=y
|
||||
CONFIG_NF_CT_NETLINK=y
|
||||
CONFIG_NETFILTER_XT_MARK=m
|
||||
CONFIG_NETFILTER_XT_TARGET_CLASSIFY=y
|
||||
CONFIG_NETFILTER_XT_TARGET_DSCP=y
|
||||
CONFIG_NETFILTER_XT_TARGET_NFLOG=y
|
||||
CONFIG_NETFILTER_XT_TARGET_NFQUEUE=y
|
||||
CONFIG_NETFILTER_XT_TARGET_SECMARK=y
|
||||
CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
|
||||
CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y
|
||||
CONFIG_NETFILTER_XT_MATCH_DSCP=y
|
||||
CONFIG_NETFILTER_XT_MATCH_POLICY=y
|
||||
CONFIG_NETFILTER_XT_MATCH_STATE=y
|
||||
CONFIG_NF_CONNTRACK_IPV4=y
|
||||
CONFIG_NF_NAT_IPV4=m
|
||||
CONFIG_IP_NF_IPTABLES=y
|
||||
CONFIG_IP_NF_FILTER=y
|
||||
CONFIG_IP_NF_TARGET_REJECT=y
|
||||
CONFIG_IP_NF_MANGLE=y
|
||||
CONFIG_NF_CONNTRACK_IPV6=m
|
||||
CONFIG_NF_NAT_IPV6=m
|
||||
CONFIG_IP6_NF_IPTABLES=m
|
||||
CONFIG_IP6_NF_MATCH_IPV6HEADER=m
|
||||
CONFIG_IP6_NF_FILTER=m
|
||||
CONFIG_IP6_NF_TARGET_REJECT=m
|
||||
CONFIG_IP6_NF_MANGLE=m
|
||||
CONFIG_BRIDGE=m
|
||||
CONFIG_VLAN_8021Q=m
|
||||
CONFIG_NET_SCHED=y
|
||||
CONFIG_NET_SCH_HTB=m
|
||||
CONFIG_NET_SCH_CODEL=m
|
||||
CONFIG_NET_SCH_FQ_CODEL=m
|
||||
CONFIG_NET_CLS_U32=m
|
||||
CONFIG_CLS_U32_MARK=y
|
||||
CONFIG_BT=m
|
||||
CONFIG_BT_RFCOMM=m
|
||||
CONFIG_BT_HCIBTUSB=m
|
||||
CONFIG_BT_HCIBFUSB=m
|
||||
CONFIG_BT_HCIVHCI=m
|
||||
CONFIG_CFG80211=m
|
||||
CONFIG_NL80211_TESTMODE=y
|
||||
CONFIG_CFG80211_DEBUGFS=y
|
||||
CONFIG_CFG80211_WEXT=y
|
||||
CONFIG_MAC80211=m
|
||||
CONFIG_MAC80211_LEDS=y
|
||||
CONFIG_MAC80211_DEBUGFS=y
|
||||
CONFIG_MAC80211_DEBUG_MENU=y
|
||||
CONFIG_MAC80211_VERBOSE_DEBUG=y
|
||||
CONFIG_RFKILL=y
|
||||
CONFIG_DEVTMPFS=y
|
||||
CONFIG_DEVTMPFS_MOUNT=y
|
||||
CONFIG_DEBUG_DEVRES=y
|
||||
CONFIG_CONNECTOR=y
|
||||
CONFIG_MTD=y
|
||||
CONFIG_MTD_BLOCK=y
|
||||
CONFIG_MTD_M25P80=y
|
||||
CONFIG_MTD_SPI_NOR=y
|
||||
CONFIG_MTD_UBI=y
|
||||
CONFIG_MTD_UBI_BLOCK=y
|
||||
CONFIG_ZRAM=m
|
||||
CONFIG_BLK_DEV_LOOP=y
|
||||
CONFIG_SCSI=y
|
||||
CONFIG_BLK_DEV_SD=y
|
||||
CONFIG_BLK_DEV_SR=m
|
||||
CONFIG_SCSI_SPI_ATTRS=y
|
||||
CONFIG_MD=y
|
||||
CONFIG_BLK_DEV_DM=y
|
||||
CONFIG_DM_CRYPT=y
|
||||
CONFIG_DM_VERITY=y
|
||||
CONFIG_NETDEVICES=y
|
||||
CONFIG_TUN=m
|
||||
CONFIG_VETH=m
|
||||
# CONFIG_NET_VENDOR_MARVELL is not set
|
||||
# CONFIG_NET_VENDOR_MICREL is not set
|
||||
# CONFIG_NET_VENDOR_MICROCHIP is not set
|
||||
# CONFIG_NET_VENDOR_NATSEMI is not set
|
||||
# CONFIG_NET_VENDOR_SEEQ is not set
|
||||
# CONFIG_NET_VENDOR_SMSC is not set
|
||||
CONFIG_STMMAC_ETH=y
|
||||
# CONFIG_NET_VENDOR_VIA is not set
|
||||
CONFIG_PPP=m
|
||||
CONFIG_PPP_ASYNC=m
|
||||
CONFIG_USB_PEGASUS=m
|
||||
CONFIG_USB_RTL8150=m
|
||||
CONFIG_USB_RTL8152=m
|
||||
CONFIG_USB_NET_DM9601=m
|
||||
CONFIG_USB_NET_SMSC75XX=m
|
||||
CONFIG_USB_NET_SMSC95XX=m
|
||||
CONFIG_USB_NET_MCS7830=m
|
||||
# CONFIG_USB_NET_CDC_SUBSET is not set
|
||||
# CONFIG_USB_NET_ZAURUS is not set
|
||||
CONFIG_LIBERTAS_THINFIRM=m
|
||||
CONFIG_USB_NET_RNDIS_WLAN=m
|
||||
CONFIG_MAC80211_HWSIM=m
|
||||
CONFIG_HOSTAP=m
|
||||
CONFIG_HOSTAP_FIRMWARE=y
|
||||
CONFIG_HOSTAP_FIRMWARE_NVRAM=y
|
||||
CONFIG_RT2X00=m
|
||||
CONFIG_RT2800USB=m
|
||||
# CONFIG_INPUT_MOUSEDEV is not set
|
||||
CONFIG_INPUT_EVDEV=y
|
||||
# CONFIG_KEYBOARD_ATKBD is not set
|
||||
CONFIG_KEYBOARD_GPIO=y
|
||||
# CONFIG_INPUT_MOUSE is not set
|
||||
# CONFIG_SERIO is not set
|
||||
# CONFIG_VT is not set
|
||||
# CONFIG_LEGACY_PTYS is not set
|
||||
# CONFIG_DEVKMEM is not set
|
||||
CONFIG_SERIAL_8250=y
|
||||
# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set
|
||||
CONFIG_SERIAL_8250_CONSOLE=y
|
||||
CONFIG_SERIAL_8250_DW=y
|
||||
CONFIG_SERIAL_OF_PLATFORM=y
|
||||
CONFIG_HW_RANDOM=y
|
||||
CONFIG_TCG_TPM=y
|
||||
CONFIG_I2C=y
|
||||
CONFIG_I2C_CHARDEV=m
|
||||
CONFIG_I2C_IMG=y
|
||||
CONFIG_I2C_STUB=m
|
||||
CONFIG_SPI=y
|
||||
CONFIG_SPI_BITBANG=m
|
||||
CONFIG_SPI_IMG_SPFI=y
|
||||
CONFIG_SPI_SPIDEV=y
|
||||
CONFIG_DEBUG_GPIO=y
|
||||
CONFIG_GPIO_SYSFS=y
|
||||
CONFIG_POWER_SUPPLY=y
|
||||
CONFIG_THERMAL=y
|
||||
CONFIG_WATCHDOG=y
|
||||
CONFIG_WATCHDOG_CORE=y
|
||||
CONFIG_IMGPDC_WDT=y
|
||||
CONFIG_REGULATOR_FIXED_VOLTAGE=y
|
||||
CONFIG_REGULATOR_GPIO=y
|
||||
CONFIG_MEDIA_SUPPORT=y
|
||||
CONFIG_MEDIA_RC_SUPPORT=y
|
||||
# CONFIG_RC_DECODERS is not set
|
||||
CONFIG_RC_DEVICES=y
|
||||
CONFIG_IR_IMG=y
|
||||
CONFIG_IR_IMG_NEC=y
|
||||
CONFIG_IR_IMG_JVC=y
|
||||
CONFIG_IR_IMG_SONY=y
|
||||
CONFIG_IR_IMG_SHARP=y
|
||||
CONFIG_IR_IMG_SANYO=y
|
||||
CONFIG_IR_IMG_RC5=y
|
||||
CONFIG_IR_IMG_RC6=y
|
||||
# CONFIG_DVB_TUNER_DIB0070 is not set
|
||||
# CONFIG_DVB_TUNER_DIB0090 is not set
|
||||
CONFIG_FB=y
|
||||
CONFIG_FB_MODE_HELPERS=y
|
||||
CONFIG_BACKLIGHT_LCD_SUPPORT=y
|
||||
# CONFIG_LCD_CLASS_DEVICE is not set
|
||||
CONFIG_BACKLIGHT_CLASS_DEVICE=y
|
||||
CONFIG_SOUND=y
|
||||
CONFIG_SND=y
|
||||
CONFIG_SND_SEQUENCER=m
|
||||
CONFIG_SND_SEQ_DUMMY=m
|
||||
CONFIG_SND_HRTIMER=m
|
||||
CONFIG_SND_DYNAMIC_MINORS=y
|
||||
# CONFIG_SND_SPI is not set
|
||||
CONFIG_SND_USB_AUDIO=m
|
||||
CONFIG_USB=y
|
||||
CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
|
||||
# CONFIG_USB_DEFAULT_PERSIST is not set
|
||||
CONFIG_USB_MON=y
|
||||
CONFIG_USB_EHCI_HCD=y
|
||||
CONFIG_USB_EHCI_ROOT_HUB_TT=y
|
||||
CONFIG_USB_ACM=y
|
||||
CONFIG_USB_STORAGE=y
|
||||
CONFIG_USB_DWC2=y
|
||||
CONFIG_USB_SERIAL=y
|
||||
CONFIG_USB_SERIAL_GENERIC=y
|
||||
CONFIG_USB_SERIAL_CP210X=m
|
||||
CONFIG_USB_SERIAL_FTDI_SIO=m
|
||||
CONFIG_USB_SERIAL_KEYSPAN=m
|
||||
CONFIG_USB_SERIAL_PL2303=m
|
||||
CONFIG_USB_SERIAL_OTI6858=m
|
||||
CONFIG_USB_SERIAL_QUALCOMM=m
|
||||
CONFIG_USB_SERIAL_SIERRAWIRELESS=m
|
||||
CONFIG_USB_SERIAL_OPTION=m
|
||||
CONFIG_MMC=y
|
||||
CONFIG_MMC_BLOCK_MINORS=16
|
||||
CONFIG_MMC_TEST=m
|
||||
CONFIG_MMC_DW=y
|
||||
CONFIG_MMC_DW_IDMAC=y
|
||||
CONFIG_NEW_LEDS=y
|
||||
CONFIG_LEDS_CLASS=y
|
||||
CONFIG_RTC_CLASS=y
|
||||
CONFIG_DMADEVICES=y
|
||||
CONFIG_IMG_MDC_DMA=y
|
||||
CONFIG_STAGING=y
|
||||
CONFIG_ASHMEM=y
|
||||
# CONFIG_ANDROID_TIMED_OUTPUT is not set
|
||||
# CONFIG_IOMMU_SUPPORT is not set
|
||||
CONFIG_MEMORY=y
|
||||
CONFIG_IIO=y
|
||||
CONFIG_CC10001_ADC=y
|
||||
CONFIG_PWM=y
|
||||
CONFIG_PWM_IMG=y
|
||||
CONFIG_ANDROID=y
|
||||
CONFIG_EXT4_FS=y
|
||||
CONFIG_EXT4_FS_POSIX_ACL=y
|
||||
CONFIG_EXT4_FS_SECURITY=y
|
||||
# CONFIG_DNOTIFY is not set
|
||||
CONFIG_FUSE_FS=m
|
||||
CONFIG_ISO9660_FS=m
|
||||
CONFIG_JOLIET=y
|
||||
CONFIG_ZISOFS=y
|
||||
CONFIG_UDF_FS=m
|
||||
CONFIG_VFAT_FS=m
|
||||
CONFIG_TMPFS=y
|
||||
CONFIG_TMPFS_POSIX_ACL=y
|
||||
CONFIG_ECRYPT_FS=y
|
||||
CONFIG_HFSPLUS_FS=m
|
||||
CONFIG_UBIFS_FS=y
|
||||
CONFIG_SQUASHFS=y
|
||||
CONFIG_SQUASHFS_FILE_DIRECT=y
|
||||
CONFIG_SQUASHFS_LZO=y
|
||||
CONFIG_PSTORE=y
|
||||
CONFIG_PSTORE_CONSOLE=y
|
||||
CONFIG_PSTORE_RAM=y
|
||||
# CONFIG_NETWORK_FILESYSTEMS is not set
|
||||
CONFIG_NLS_DEFAULT="utf8"
|
||||
CONFIG_NLS_CODEPAGE_437=m
|
||||
CONFIG_NLS_ASCII=m
|
||||
CONFIG_NLS_ISO8859_1=m
|
||||
CONFIG_PRINTK_TIME=y
|
||||
CONFIG_DEBUG_INFO=y
|
||||
CONFIG_MAGIC_SYSRQ=y
|
||||
CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0
|
||||
CONFIG_LOCKUP_DETECTOR=y
|
||||
CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC=y
|
||||
CONFIG_BOOTPARAM_HUNG_TASK_PANIC=y
|
||||
# CONFIG_SCHED_DEBUG is not set
|
||||
CONFIG_SCHEDSTATS=y
|
||||
CONFIG_TIMER_STATS=y
|
||||
CONFIG_DEBUG_SPINLOCK=y
|
||||
CONFIG_DEBUG_CREDENTIALS=y
|
||||
CONFIG_FUNCTION_TRACER=y
|
||||
CONFIG_BLK_DEV_IO_TRACE=y
|
||||
CONFIG_LKDTM=y
|
||||
CONFIG_TEST_UDELAY=m
|
||||
CONFIG_KEYS=y
|
||||
CONFIG_SECURITY=y
|
||||
CONFIG_SECURITY_NETWORK=y
|
||||
CONFIG_SECURITY_YAMA=y
|
||||
CONFIG_SECURITY_YAMA_STACKED=y
|
||||
CONFIG_DEFAULT_SECURITY_DAC=y
|
||||
CONFIG_CRYPTO_AUTHENC=y
|
||||
CONFIG_CRYPTO_HMAC=y
|
||||
CONFIG_CRYPTO_SHA1=y
|
||||
CONFIG_CRYPTO_SHA256=y
|
||||
CONFIG_CRYPTO_SHA512=m
|
||||
CONFIG_CRYPTO_ARC4=y
|
||||
CONFIG_CRYPTO_DES=y
|
||||
# CONFIG_CRYPTO_ANSI_CPRNG is not set
|
||||
CONFIG_CRC_CCITT=y
|
||||
CONFIG_CRC_T10DIF=m
|
||||
CONFIG_CRC7=m
|
||||
CONFIG_LIBCRC32C=m
|
||||
# CONFIG_XZ_DEC_X86 is not set
|
||||
Some files were not shown because too many files have changed in this diff Show More
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Reference in New Issue