ARM: dts: imx6qdl: don't configure reserved pad settings
Several dts files set a bit in the SPEED field for pads RGMII_{R,T}{XC,D0,D1,D2,D3,X_CTL}, but that doesn't exist. Writing there doesn't have an effect and the bit reads as zero. Signed-off-by: Uwe Kleine-König <uwe@kleine-koenig.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
This commit is contained in:
parent
51a012b762
commit
c007b3a697
|
@ -376,18 +376,18 @@
|
||||||
fsl,pins = <
|
fsl,pins = <
|
||||||
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
|
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
|
||||||
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
|
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
|
||||||
MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
|
MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
|
||||||
MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
|
MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
|
||||||
MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
|
MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
|
||||||
MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
|
MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
|
||||||
MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
|
MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
|
||||||
MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
|
MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
|
||||||
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x0a0b1 /* AR8035 CLK_25M --> ENET_REF_CLK (V22) */
|
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x0a0b1 /* AR8035 CLK_25M --> ENET_REF_CLK (V22) */
|
||||||
MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 /* AR8035 pin strapping: IO voltage: pull up */
|
MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 /* AR8035 pin strapping: IO voltage: pull up */
|
||||||
MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x130b0 /* AR8035 pin strapping: PHYADDR#0: pull down */
|
MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x13030 /* AR8035 pin strapping: PHYADDR#0: pull down */
|
||||||
MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x130b0 /* AR8035 pin strapping: PHYADDR#1: pull down */
|
MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x13030 /* AR8035 pin strapping: PHYADDR#1: pull down */
|
||||||
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 /* AR8035 pin strapping: MODE#1: pull up */
|
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 /* AR8035 pin strapping: MODE#1: pull up */
|
||||||
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 /* AR8035 pin strapping: MODE#3: pull up */
|
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 /* AR8035 pin strapping: MODE#3: pull up */
|
||||||
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x130b0 /* AR8035 pin strapping: MODE#0: pull down */
|
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x130b0 /* AR8035 pin strapping: MODE#0: pull down */
|
||||||
MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 /* GPIO16 -> AR8035 25MHz */
|
MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 /* GPIO16 -> AR8035 25MHz */
|
||||||
MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x130b0 /* RGMII_nRST */
|
MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x130b0 /* RGMII_nRST */
|
||||||
|
|
|
@ -79,19 +79,19 @@
|
||||||
fsl,pins = <
|
fsl,pins = <
|
||||||
MX6QDL_PAD_KEY_COL1__ENET_MDIO 0x1b0b0
|
MX6QDL_PAD_KEY_COL1__ENET_MDIO 0x1b0b0
|
||||||
MX6QDL_PAD_KEY_COL2__ENET_MDC 0x1b0b0
|
MX6QDL_PAD_KEY_COL2__ENET_MDC 0x1b0b0
|
||||||
MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
|
MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
|
||||||
MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
|
MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
|
||||||
MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
|
MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
|
||||||
MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
|
MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
|
||||||
MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
|
MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
|
||||||
MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
|
MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
|
||||||
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
|
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
|
||||||
MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
|
MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
|
||||||
MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
|
MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
|
||||||
MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
|
MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
|
||||||
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
|
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
|
||||||
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
|
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
|
||||||
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
|
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
|
||||||
MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1
|
MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1
|
||||||
>;
|
>;
|
||||||
};
|
};
|
||||||
|
|
|
@ -448,19 +448,19 @@
|
||||||
fsl,pins = <
|
fsl,pins = <
|
||||||
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x100b0
|
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x100b0
|
||||||
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x100b0
|
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x100b0
|
||||||
MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x100b0
|
MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x10030
|
||||||
MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x100b0
|
MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x10030
|
||||||
MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x100b0
|
MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x10030
|
||||||
MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x100b0
|
MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x10030
|
||||||
MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x100b0
|
MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x10030
|
||||||
MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x100b0
|
MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x10030
|
||||||
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0
|
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0
|
||||||
MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
|
MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
|
||||||
MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
|
MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
|
||||||
MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
|
MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
|
||||||
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
|
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
|
||||||
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
|
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
|
||||||
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
|
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
|
||||||
/* FEC Reset */
|
/* FEC Reset */
|
||||||
MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0
|
MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0
|
||||||
/* AR8033 Interrupt */
|
/* AR8033 Interrupt */
|
||||||
|
|
|
@ -168,18 +168,18 @@
|
||||||
|
|
||||||
pinctrl_enet: enetgrp {
|
pinctrl_enet: enetgrp {
|
||||||
fsl,pins = <
|
fsl,pins = <
|
||||||
MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
|
MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
|
||||||
MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
|
MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
|
||||||
MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
|
MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
|
||||||
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
|
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
|
||||||
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
|
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
|
||||||
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
|
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
|
||||||
MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
|
MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
|
||||||
MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
|
MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
|
||||||
MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
|
MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
|
||||||
MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
|
MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
|
||||||
MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
|
MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
|
||||||
MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
|
MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
|
||||||
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
|
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
|
||||||
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
|
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
|
||||||
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
|
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
|
||||||
|
|
|
@ -324,18 +324,18 @@
|
||||||
|
|
||||||
pinctrl_enet: enetgrp {
|
pinctrl_enet: enetgrp {
|
||||||
fsl,pins = <
|
fsl,pins = <
|
||||||
MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
|
MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
|
||||||
MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
|
MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
|
||||||
MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
|
MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
|
||||||
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
|
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
|
||||||
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
|
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
|
||||||
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
|
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
|
||||||
MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
|
MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
|
||||||
MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
|
MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
|
||||||
MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
|
MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
|
||||||
MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
|
MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
|
||||||
MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
|
MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
|
||||||
MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
|
MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
|
||||||
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
|
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
|
||||||
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
|
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
|
||||||
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
|
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
|
||||||
|
|
|
@ -303,19 +303,19 @@
|
||||||
fsl,pins = <
|
fsl,pins = <
|
||||||
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
|
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
|
||||||
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
|
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
|
||||||
MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
|
MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
|
||||||
MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
|
MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
|
||||||
MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
|
MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
|
||||||
MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
|
MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
|
||||||
MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
|
MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
|
||||||
MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
|
MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
|
||||||
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
|
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
|
||||||
MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
|
MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
|
||||||
MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
|
MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
|
||||||
MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
|
MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
|
||||||
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
|
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
|
||||||
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
|
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
|
||||||
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
|
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
|
||||||
MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x4001b0a8
|
MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x4001b0a8
|
||||||
MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0
|
MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0
|
||||||
>;
|
>;
|
||||||
|
|
|
@ -421,18 +421,18 @@
|
||||||
|
|
||||||
pinctrl_enet: enetgrp {
|
pinctrl_enet: enetgrp {
|
||||||
fsl,pins = <
|
fsl,pins = <
|
||||||
MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
|
MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
|
||||||
MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
|
MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
|
||||||
MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
|
MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
|
||||||
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
|
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
|
||||||
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
|
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
|
||||||
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
|
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
|
||||||
MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
|
MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
|
||||||
MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
|
MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
|
||||||
MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
|
MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
|
||||||
MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
|
MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
|
||||||
MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
|
MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
|
||||||
MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
|
MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
|
||||||
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
|
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
|
||||||
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
|
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
|
||||||
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
|
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
|
||||||
|
|
|
@ -252,26 +252,26 @@
|
||||||
fsl,pins = <
|
fsl,pins = <
|
||||||
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
|
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
|
||||||
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
|
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
|
||||||
MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
|
MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
|
||||||
MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
|
MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
|
||||||
MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
|
MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
|
||||||
MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
|
MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
|
||||||
MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
|
MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
|
||||||
MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
|
MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
|
||||||
/* AR8035 CLK_25M --> ENET_REF_CLK (V22) */
|
/* AR8035 CLK_25M --> ENET_REF_CLK (V22) */
|
||||||
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x0a0b1
|
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x0a0b1
|
||||||
/* AR8035 pin strapping: IO voltage: pull up */
|
/* AR8035 pin strapping: IO voltage: pull up */
|
||||||
MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
|
MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
|
||||||
/* AR8035 pin strapping: PHYADDR#0: pull down */
|
/* AR8035 pin strapping: PHYADDR#0: pull down */
|
||||||
MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x130b0
|
MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x13030
|
||||||
/* AR8035 pin strapping: PHYADDR#1: pull down */
|
/* AR8035 pin strapping: PHYADDR#1: pull down */
|
||||||
MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x130b0
|
MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x13030
|
||||||
/* AR8035 pin strapping: MODE#1: pull up */
|
/* AR8035 pin strapping: MODE#1: pull up */
|
||||||
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
|
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
|
||||||
/* AR8035 pin strapping: MODE#3: pull up */
|
/* AR8035 pin strapping: MODE#3: pull up */
|
||||||
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
|
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
|
||||||
/* AR8035 pin strapping: MODE#0: pull down */
|
/* AR8035 pin strapping: MODE#0: pull down */
|
||||||
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x130b0
|
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x13030
|
||||||
/* GPIO16 -> AR8035 25MHz */
|
/* GPIO16 -> AR8035 25MHz */
|
||||||
MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
|
MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
|
||||||
/* RGMII_nRST */
|
/* RGMII_nRST */
|
||||||
|
|
|
@ -549,12 +549,12 @@
|
||||||
MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b028
|
MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b028
|
||||||
MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b028
|
MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b028
|
||||||
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
|
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
|
||||||
MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
|
MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
|
||||||
MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
|
MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
|
||||||
MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
|
MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
|
||||||
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
|
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
|
||||||
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
|
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
|
||||||
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
|
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
|
||||||
MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
|
MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
|
||||||
/* Ethernet reset */
|
/* Ethernet reset */
|
||||||
MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x1b0b1
|
MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x1b0b1
|
||||||
|
|
|
@ -31,19 +31,19 @@
|
||||||
fsl,pins = <
|
fsl,pins = <
|
||||||
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
|
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
|
||||||
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
|
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
|
||||||
MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
|
MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
|
||||||
MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
|
MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
|
||||||
MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
|
MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
|
||||||
MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
|
MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
|
||||||
MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
|
MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
|
||||||
MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
|
MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
|
||||||
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
|
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
|
||||||
MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
|
MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
|
||||||
MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
|
MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
|
||||||
MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
|
MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
|
||||||
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
|
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
|
||||||
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
|
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
|
||||||
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
|
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
|
||||||
MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
|
MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
|
||||||
>;
|
>;
|
||||||
};
|
};
|
||||||
|
|
|
@ -284,19 +284,19 @@
|
||||||
fsl,pins = <
|
fsl,pins = <
|
||||||
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
|
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
|
||||||
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
|
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
|
||||||
MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
|
MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
|
||||||
MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
|
MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
|
||||||
MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
|
MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
|
||||||
MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
|
MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
|
||||||
MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
|
MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
|
||||||
MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
|
MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
|
||||||
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
|
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
|
||||||
MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
|
MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
|
||||||
MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
|
MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
|
||||||
MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
|
MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
|
||||||
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
|
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
|
||||||
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
|
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
|
||||||
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
|
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
|
||||||
MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
|
MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
|
||||||
MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b059
|
MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b059
|
||||||
>;
|
>;
|
||||||
|
|
|
@ -586,19 +586,19 @@
|
||||||
fsl,pins = <
|
fsl,pins = <
|
||||||
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x100b0
|
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x100b0
|
||||||
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x100b0
|
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x100b0
|
||||||
MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x100b0
|
MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x10030
|
||||||
MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x100b0
|
MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x10030
|
||||||
MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x100b0
|
MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x10030
|
||||||
MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x100b0
|
MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x10030
|
||||||
MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x100b0
|
MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x10030
|
||||||
MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x100b0
|
MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x10030
|
||||||
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0
|
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0
|
||||||
MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
|
MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
|
||||||
MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
|
MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
|
||||||
MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
|
MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
|
||||||
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
|
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
|
||||||
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
|
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
|
||||||
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
|
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
|
||||||
/* Ethernet PHY reset */
|
/* Ethernet PHY reset */
|
||||||
MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x000b0
|
MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x000b0
|
||||||
/* Ethernet PHY interrupt */
|
/* Ethernet PHY interrupt */
|
||||||
|
|
|
@ -67,18 +67,18 @@
|
||||||
|
|
||||||
pinctrl_enet: enetgrp {
|
pinctrl_enet: enetgrp {
|
||||||
fsl,pins = <
|
fsl,pins = <
|
||||||
MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
|
MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
|
||||||
MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
|
MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
|
||||||
MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
|
MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
|
||||||
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
|
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
|
||||||
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
|
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
|
||||||
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
|
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
|
||||||
MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
|
MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
|
||||||
MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
|
MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
|
||||||
MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
|
MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
|
||||||
MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
|
MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
|
||||||
MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
|
MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
|
||||||
MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
|
MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
|
||||||
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
|
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
|
||||||
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
|
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
|
||||||
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
|
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
|
||||||
|
|
|
@ -238,18 +238,18 @@
|
||||||
imx6qdl-gw51xx {
|
imx6qdl-gw51xx {
|
||||||
pinctrl_enet: enetgrp {
|
pinctrl_enet: enetgrp {
|
||||||
fsl,pins = <
|
fsl,pins = <
|
||||||
MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
|
MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
|
||||||
MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
|
MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
|
||||||
MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
|
MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
|
||||||
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
|
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
|
||||||
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
|
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
|
||||||
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
|
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
|
||||||
MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
|
MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
|
||||||
MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
|
MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
|
||||||
MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
|
MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
|
||||||
MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
|
MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
|
||||||
MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
|
MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
|
||||||
MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
|
MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
|
||||||
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
|
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
|
||||||
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
|
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
|
||||||
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
|
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
|
||||||
|
|
|
@ -382,18 +382,18 @@
|
||||||
|
|
||||||
pinctrl_enet: enetgrp {
|
pinctrl_enet: enetgrp {
|
||||||
fsl,pins = <
|
fsl,pins = <
|
||||||
MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
|
MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
|
||||||
MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
|
MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
|
||||||
MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
|
MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
|
||||||
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
|
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
|
||||||
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
|
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
|
||||||
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
|
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
|
||||||
MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
|
MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
|
||||||
MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
|
MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
|
||||||
MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
|
MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
|
||||||
MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
|
MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
|
||||||
MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
|
MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
|
||||||
MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
|
MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
|
||||||
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
|
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
|
||||||
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
|
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
|
||||||
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
|
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
|
||||||
|
|
|
@ -371,18 +371,18 @@
|
||||||
|
|
||||||
pinctrl_enet: enetgrp {
|
pinctrl_enet: enetgrp {
|
||||||
fsl,pins = <
|
fsl,pins = <
|
||||||
MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
|
MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
|
||||||
MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
|
MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
|
||||||
MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
|
MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
|
||||||
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
|
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
|
||||||
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
|
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
|
||||||
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
|
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
|
||||||
MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
|
MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
|
||||||
MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
|
MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
|
||||||
MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
|
MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
|
||||||
MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
|
MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
|
||||||
MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
|
MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
|
||||||
MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
|
MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
|
||||||
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
|
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
|
||||||
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
|
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
|
||||||
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
|
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
|
||||||
|
|
|
@ -478,18 +478,18 @@
|
||||||
|
|
||||||
pinctrl_enet: enetgrp {
|
pinctrl_enet: enetgrp {
|
||||||
fsl,pins = <
|
fsl,pins = <
|
||||||
MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
|
MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
|
||||||
MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
|
MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
|
||||||
MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
|
MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
|
||||||
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
|
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
|
||||||
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
|
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
|
||||||
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
|
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
|
||||||
MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
|
MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
|
||||||
MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
|
MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
|
||||||
MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
|
MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
|
||||||
MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
|
MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
|
||||||
MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
|
MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
|
||||||
MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
|
MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
|
||||||
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
|
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
|
||||||
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
|
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
|
||||||
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
|
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
|
||||||
|
|
|
@ -254,19 +254,19 @@
|
||||||
fsl,pins = <
|
fsl,pins = <
|
||||||
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
|
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
|
||||||
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
|
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
|
||||||
MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
|
MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
|
||||||
MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
|
MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
|
||||||
MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
|
MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
|
||||||
MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
|
MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
|
||||||
MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
|
MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
|
||||||
MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
|
MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
|
||||||
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
|
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
|
||||||
MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
|
MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
|
||||||
MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
|
MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
|
||||||
MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
|
MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
|
||||||
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
|
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
|
||||||
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
|
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
|
||||||
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
|
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
|
||||||
MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0
|
MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0
|
||||||
>;
|
>;
|
||||||
};
|
};
|
||||||
|
|
|
@ -361,12 +361,12 @@
|
||||||
MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x100b0
|
MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x100b0
|
||||||
MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x100b0
|
MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x100b0
|
||||||
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0
|
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0
|
||||||
MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
|
MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
|
||||||
MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
|
MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
|
||||||
MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
|
MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
|
||||||
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
|
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
|
||||||
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
|
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
|
||||||
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
|
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
|
||||||
/* Phy reset */
|
/* Phy reset */
|
||||||
MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x0f0b0
|
MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x0f0b0
|
||||||
MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0
|
MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0
|
||||||
|
|
|
@ -484,19 +484,19 @@
|
||||||
fsl,pins = <
|
fsl,pins = <
|
||||||
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x100b0
|
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x100b0
|
||||||
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x100b0
|
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x100b0
|
||||||
MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x100b0
|
MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x10030
|
||||||
MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x100b0
|
MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x10030
|
||||||
MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x100b0
|
MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x10030
|
||||||
MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x100b0
|
MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x10030
|
||||||
MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x100b0
|
MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x10030
|
||||||
MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x100b0
|
MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x10030
|
||||||
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0
|
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0
|
||||||
MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
|
MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
|
||||||
MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
|
MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
|
||||||
MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
|
MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
|
||||||
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
|
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
|
||||||
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
|
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
|
||||||
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
|
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
|
||||||
/* Phy reset */
|
/* Phy reset */
|
||||||
MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x0f0b0
|
MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x0f0b0
|
||||||
MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0
|
MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0
|
||||||
|
|
|
@ -394,19 +394,19 @@
|
||||||
fsl,pins = <
|
fsl,pins = <
|
||||||
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x100b0
|
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x100b0
|
||||||
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x100b0
|
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x100b0
|
||||||
MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x100b0
|
MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x10030
|
||||||
MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x100b0
|
MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x10030
|
||||||
MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x100b0
|
MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x10030
|
||||||
MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x100b0
|
MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x10030
|
||||||
MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x100b0
|
MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x10030
|
||||||
MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x100b0
|
MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x10030
|
||||||
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0
|
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0
|
||||||
MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
|
MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
|
||||||
MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
|
MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
|
||||||
MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
|
MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
|
||||||
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
|
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
|
||||||
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
|
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
|
||||||
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
|
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
|
||||||
/* Phy reset */
|
/* Phy reset */
|
||||||
MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x000b0
|
MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x000b0
|
||||||
MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1
|
MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1
|
||||||
|
|
|
@ -231,19 +231,19 @@
|
||||||
fsl,pins = <
|
fsl,pins = <
|
||||||
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
|
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
|
||||||
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
|
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
|
||||||
MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
|
MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
|
||||||
MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
|
MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
|
||||||
MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
|
MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
|
||||||
MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
|
MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
|
||||||
MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
|
MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
|
||||||
MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
|
MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
|
||||||
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
|
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
|
||||||
MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
|
MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
|
||||||
MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
|
MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
|
||||||
MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
|
MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
|
||||||
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
|
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
|
||||||
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
|
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
|
||||||
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
|
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
|
||||||
MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0
|
MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0
|
||||||
>;
|
>;
|
||||||
};
|
};
|
||||||
|
|
|
@ -196,19 +196,19 @@
|
||||||
fsl,pins = <
|
fsl,pins = <
|
||||||
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
|
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
|
||||||
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
|
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
|
||||||
MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
|
MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
|
||||||
MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
|
MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
|
||||||
MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
|
MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
|
||||||
MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
|
MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
|
||||||
MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
|
MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
|
||||||
MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
|
MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
|
||||||
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
|
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
|
||||||
MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
|
MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
|
||||||
MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
|
MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
|
||||||
MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
|
MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
|
||||||
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
|
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
|
||||||
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
|
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
|
||||||
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
|
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
|
||||||
MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
|
MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
|
||||||
/* Phy reset */
|
/* Phy reset */
|
||||||
MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x000b0
|
MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x000b0
|
||||||
|
|
|
@ -345,19 +345,19 @@
|
||||||
fsl,pins = <
|
fsl,pins = <
|
||||||
MX6QDL_PAD_KEY_COL1__ENET_MDIO 0x1b0b0
|
MX6QDL_PAD_KEY_COL1__ENET_MDIO 0x1b0b0
|
||||||
MX6QDL_PAD_KEY_COL2__ENET_MDC 0x1b0b0
|
MX6QDL_PAD_KEY_COL2__ENET_MDC 0x1b0b0
|
||||||
MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
|
MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
|
||||||
MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
|
MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
|
||||||
MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
|
MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
|
||||||
MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
|
MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
|
||||||
MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
|
MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
|
||||||
MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
|
MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
|
||||||
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
|
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
|
||||||
MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
|
MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
|
||||||
MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
|
MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
|
||||||
MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
|
MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
|
||||||
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
|
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
|
||||||
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
|
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
|
||||||
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
|
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
|
||||||
MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1
|
MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1
|
||||||
>;
|
>;
|
||||||
};
|
};
|
||||||
|
|
|
@ -359,19 +359,19 @@
|
||||||
fsl,pins = <
|
fsl,pins = <
|
||||||
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x100b0
|
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x100b0
|
||||||
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x100b0
|
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x100b0
|
||||||
MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x100b0
|
MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x10030
|
||||||
MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x100b0
|
MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x10030
|
||||||
MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x100b0
|
MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x10030
|
||||||
MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x100b0
|
MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x10030
|
||||||
MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x100b0
|
MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x10030
|
||||||
MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x100b0
|
MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x10030
|
||||||
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0
|
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0
|
||||||
MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
|
MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
|
||||||
MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
|
MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
|
||||||
MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
|
MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
|
||||||
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
|
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
|
||||||
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
|
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
|
||||||
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
|
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
|
||||||
/* Phy reset */
|
/* Phy reset */
|
||||||
MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x000b0
|
MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x000b0
|
||||||
MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1
|
MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1
|
||||||
|
|
|
@ -380,19 +380,19 @@
|
||||||
fsl,pins = <
|
fsl,pins = <
|
||||||
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
|
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
|
||||||
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
|
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
|
||||||
MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
|
MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
|
||||||
MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
|
MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
|
||||||
MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
|
MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
|
||||||
MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
|
MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
|
||||||
MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
|
MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
|
||||||
MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
|
MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
|
||||||
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
|
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
|
||||||
MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
|
MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
|
||||||
MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
|
MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
|
||||||
MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
|
MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
|
||||||
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
|
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
|
||||||
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
|
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
|
||||||
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
|
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
|
||||||
MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
|
MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
|
||||||
>;
|
>;
|
||||||
};
|
};
|
||||||
|
|
|
@ -132,18 +132,18 @@
|
||||||
imx6q-udoo {
|
imx6q-udoo {
|
||||||
pinctrl_enet: enetgrp {
|
pinctrl_enet: enetgrp {
|
||||||
fsl,pins = <
|
fsl,pins = <
|
||||||
MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
|
MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
|
||||||
MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
|
MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
|
||||||
MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
|
MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
|
||||||
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
|
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
|
||||||
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
|
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
|
||||||
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
|
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
|
||||||
MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
|
MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
|
||||||
MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
|
MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
|
||||||
MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
|
MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
|
||||||
MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
|
MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
|
||||||
MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
|
MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
|
||||||
MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
|
MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
|
||||||
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
|
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
|
||||||
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
|
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
|
||||||
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
|
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
|
||||||
|
|
|
@ -109,19 +109,19 @@
|
||||||
fsl,pins = <
|
fsl,pins = <
|
||||||
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
|
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
|
||||||
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
|
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
|
||||||
MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
|
MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
|
||||||
MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
|
MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
|
||||||
MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
|
MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
|
||||||
MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
|
MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
|
||||||
MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
|
MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
|
||||||
MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
|
MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
|
||||||
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
|
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
|
||||||
MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
|
MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
|
||||||
MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
|
MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
|
||||||
MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
|
MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
|
||||||
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
|
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
|
||||||
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
|
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
|
||||||
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
|
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
|
||||||
MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
|
MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
|
||||||
MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1
|
MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1
|
||||||
>;
|
>;
|
||||||
|
|
Loading…
Reference in a new issue