ARM: dts: artpec: add pcie support
Add PCIe support to the ARTPEC-6 SoC. This uses the existing pcie-artpec6 driver. So, all that is needed is device tree entries in the DTS. Signed-off-by: Niklas Cassel <niklas.cassel@axis.com> Signed-off-by: Jesper Nilsson <jespern@axis.com>
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@ -46,6 +46,10 @@
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status = "okay";
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status = "okay";
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};
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};
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&pcie {
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status = "okay";
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};
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ðernet {
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ðernet {
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status = "okay";
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status = "okay";
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@ -67,7 +67,7 @@
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};
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};
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};
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};
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syscon {
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syscon: syscon@f8000000 {
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compatible = "axis,artpec6-syscon", "syscon";
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compatible = "axis,artpec6-syscon", "syscon";
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reg = <0xf8000000 0x48>;
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reg = <0xf8000000 0x48>;
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};
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};
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@ -154,6 +154,33 @@
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interrupt-parent = <&intc>;
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interrupt-parent = <&intc>;
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};
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};
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pcie: pcie@f8050000 {
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compatible = "axis,artpec6-pcie", "snps,dw-pcie";
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reg = <0xf8050000 0x2000
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0xf8040000 0x1000
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0xc0000000 0x2000>;
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reg-names = "dbi", "phy", "config";
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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/* downstream I/O */
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ranges = <0x81000000 0 0 0xc0002000 0 0x00010000
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/* non-prefetchable memory */
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0x82000000 0 0xc0012000 0xc0012000 0 0x1ffee000>;
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num-lanes = <2>;
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bus-range = <0x00 0xff>;
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interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "msi";
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0x7>;
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interrupt-map = <0 0 0 1 &intc GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 0 2 &intc GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 0 3 &intc GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 0 4 &intc GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
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axis,syscon-pcie = <&syscon>;
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status = "disabled";
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};
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amba@0 {
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amba@0 {
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compatible = "simple-bus";
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compatible = "simple-bus";
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#address-cells = <0x1>;
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#address-cells = <0x1>;
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