[IA64] hotplug/ia64: SN Hotplug Driver: moving of header files
This patch moves header files out of the arch/ia64/sn directories and into include/asm-ia64/sn. These files were being included by other subsystems and should be under include/asm-ia64/sn. Signed-off-by: Prarit Bhargava <prarit@sgi.com> Signed-off-by: Tony Luck <tony.luck@intel.com>wifi-calibration
Prarit Bhargava
Tony Luck
parent
cb4cb2cb9b
commit
c13cf3714f
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@ -8,6 +8,8 @@
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#ifndef _ASM_IA64_SN_XTALK_HUBDEV_H
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#define _ASM_IA64_SN_XTALK_HUBDEV_H
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#include "xtalk/xwidgetdev.h"
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#define HUB_WIDGET_ID_MAX 0xf
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#define DEV_PER_WIDGET (2*2*8)
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#define IIO_ITTE_WIDGET_BITS 4 /* size of widget field */
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@ -9,17 +9,17 @@
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#include <linux/bootmem.h>
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#include <linux/nodemask.h>
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#include <asm/sn/types.h>
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#include <asm/sn/sn_sal.h>
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#include <asm/sn/addrs.h>
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#include <asm/sn/geo.h>
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#include <asm/sn/io.h>
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#include <asm/sn/pcibr_provider.h>
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#include <asm/sn/pcibus_provider_defs.h>
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#include <asm/sn/pcidev.h>
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#include "pci/pcibr_provider.h"
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#include "xtalk/xwidgetdev.h"
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#include <asm/sn/geo.h>
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#include "xtalk/hubdev.h"
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#include <asm/sn/io.h>
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#include <asm/sn/simulator.h>
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#include <asm/sn/sn_sal.h>
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#include <asm/sn/tioca_provider.h>
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#include "xtalk/hubdev.h"
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#include "xtalk/xwidgetdev.h"
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nasid_t master_nasid = INVALID_NASID; /* Partition Master */
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@ -226,7 +226,7 @@ static void sn_fixup_ionodes(void)
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* from our PCI provider include PIO maps to BAR space and interrupt
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* objects.
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*/
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static void sn_pci_fixup_slot(struct pci_dev *dev)
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void sn_pci_fixup_slot(struct pci_dev *dev)
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{
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int idx;
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int segment = 0;
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@ -10,13 +10,12 @@
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#include <linux/irq.h>
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#include <linux/spinlock.h>
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#include <asm/sn/intr.h>
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#include <asm/sn/addrs.h>
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#include <asm/sn/arch.h>
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#include "xtalk/xwidgetdev.h"
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#include <asm/sn/intr.h>
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#include <asm/sn/pcibr_provider.h>
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#include <asm/sn/pcibus_provider_defs.h>
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#include <asm/sn/pcidev.h>
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#include "pci/pcibr_provider.h"
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#include <asm/sn/shub_mmr.h>
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#include <asm/sn/sn_sal.h>
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@ -11,9 +11,10 @@
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#include <linux/module.h>
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#include <asm/dma.h>
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#include <asm/sn/sn_sal.h>
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#include <asm/sn/pcibr_provider.h>
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#include <asm/sn/pcibus_provider_defs.h>
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#include <asm/sn/pcidev.h>
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#include <asm/sn/sn_sal.h>
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#define SG_ENT_VIRT_ADDRESS(sg) (page_address((sg)->page) + (sg)->offset)
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#define SG_ENT_PHYS_ADDRESS(SG) virt_to_phys(SG_ENT_VIRT_ADDRESS(SG))
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@ -8,9 +8,9 @@
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#include <linux/types.h>
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#include <asm/sn/sn_sal.h>
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#include <asm/sn/pcibr_provider.h>
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#include <asm/sn/pcibus_provider_defs.h>
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#include <asm/sn/pcidev.h>
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#include "pci/pcibr_provider.h"
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int pcibr_invalidate_ate = 0; /* by default don't invalidate ATE on free */
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@ -8,18 +8,17 @@
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#include <linux/types.h>
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#include <linux/pci.h>
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#include <asm/sn/sn_sal.h>
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#include <asm/sn/addrs.h>
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#include <asm/sn/geo.h>
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#include "xtalk/xwidgetdev.h"
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#include "xtalk/hubdev.h"
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#include <asm/sn/pcibr_provider.h>
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#include <asm/sn/pcibus_provider_defs.h>
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#include <asm/sn/pcidev.h>
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#include "pci/tiocp.h"
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#include "pci/pic.h"
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#include "pci/pcibr_provider.h"
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#include "pci/tiocp.h"
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#include <asm/sn/pic.h>
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#include <asm/sn/sn_sal.h>
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#include <asm/sn/tiocp.h>
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#include "tio.h"
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#include <asm/sn/addrs.h>
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#include "xtalk/xwidgetdev.h"
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#include "xtalk/hubdev.h"
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extern int sn_ioif_inited;
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@ -6,18 +6,17 @@
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* Copyright (C) 2001-2004 Silicon Graphics, Inc. All rights reserved.
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*/
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#include <linux/types.h>
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#include <linux/interrupt.h>
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#include <linux/types.h>
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#include <linux/pci.h>
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#include <asm/sn/sn_sal.h>
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#include "xtalk/xwidgetdev.h"
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#include <asm/sn/addrs.h>
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#include <asm/sn/geo.h>
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#include "xtalk/hubdev.h"
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#include <asm/sn/pcibr_provider.h>
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#include <asm/sn/pcibus_provider_defs.h>
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#include <asm/sn/pcidev.h>
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#include "pci/pcibr_provider.h"
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#include <asm/sn/addrs.h>
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#include <asm/sn/sn_sal.h>
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#include "xtalk/xwidgetdev.h"
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#include "xtalk/hubdev.h"
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static int sal_pcibr_error_interrupt(struct pcibus_info *soft)
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{
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@ -6,13 +6,13 @@
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* Copyright (C) 2004 Silicon Graphics, Inc. All rights reserved.
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*/
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#include <linux/types.h>
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#include <linux/interrupt.h>
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#include <linux/types.h>
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#include <asm/sn/pcibr_provider.h>
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#include <asm/sn/pcibus_provider_defs.h>
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#include <asm/sn/pcidev.h>
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#include "pci/tiocp.h"
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#include "pci/pic.h"
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#include "pci/pcibr_provider.h"
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#include <asm/sn/pic.h>
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#include <asm/sn/tiocp.h>
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union br_ptr {
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struct tiocp tio;
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@ -8,6 +8,9 @@
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#ifndef _ASM_IA64_SN_PCI_PCIBR_PROVIDER_H
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#define _ASM_IA64_SN_PCI_PCIBR_PROVIDER_H
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#include <asm/sn/intr.h>
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#include <asm/sn/pcibus_provider_defs.h>
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/* Workarounds */
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#define PV907516 (1 << 1) /* TIOCP: Don't write the write buffer flush reg */
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@ -20,7 +23,7 @@
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#define IS_PIC_SOFT(ps) (ps->pbi_bridge_type == PCIBR_BRIDGETYPE_PIC)
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/*
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/*
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* The different PCI Bridge types supported on the SGI Altix platforms
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*/
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#define PCIBR_BRIDGETYPE_UNKNOWN -1
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@ -100,7 +103,7 @@ struct pcibus_info {
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struct ate_resource pbi_int_ate_resource;
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uint64_t pbi_int_ate_size;
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uint64_t pbi_dir_xbase;
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char pbi_hub_xid;
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@ -13,6 +13,8 @@
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#define SN_PCIDEV_INFO(pci_dev) \
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((struct pcidev_info *)(pci_dev)->sysdata)
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#define SN_PCIBUS_BUSSOFT_INFO(pci_bus) \
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(struct pcibus_info *)((struct pcibus_bussoft *)(PCI_CONTROLLER((pci_bus))->platform_data))
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/*
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* Given a pci_bus, return the sn pcibus_bussoft struct. Note that
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* this only works for root busses, not for busses represented by PPB's.
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@ -53,6 +55,8 @@ struct pcidev_info {
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extern void sn_irq_fixup(struct pci_dev *pci_dev,
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struct sn_irq_info *sn_irq_info);
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extern void sn_irq_unfixup(struct pci_dev *pci_dev);
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extern void sn_pci_fixup_slot(struct pci_dev *dev);
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extern void sn_pci_unfixup_slot(struct pci_dev *dev);
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extern void sn_irq_lh_init(void);
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#endif /* _ASM_IA64_SN_PCI_PCIDEV_H */
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@ -15,7 +15,7 @@
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* PIC handles PCI/X busses. PCI/X requires that the 'bridge' (i.e. PIC)
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* be designated as 'device 0'. That is a departure from earlier SGI
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* PCI bridges. Because of that we use config space 1 to access the
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* config space of the first actual PCI device on the bus.
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* config space of the first actual PCI device on the bus.
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* Here's what the PIC manual says:
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*
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* The current PCI-X bus specification now defines that the parent
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@ -29,14 +29,14 @@
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* correlated Configs pace and our device space 0 <-> 0, 1 <-> 1, etc.
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* PCI-X requires we start a 1, not 0 and currently the PX brick
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* does associate our:
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*
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*
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* device 0 with configuration space window 1,
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* device 1 with configuration space window 2,
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* device 1 with configuration space window 2,
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* device 2 with configuration space window 3,
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* device 3 with configuration space window 4.
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*
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* The net effect is that all config space access are off-by-one with
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* relation to other per-slot accesses on the PIC.
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* The net effect is that all config space access are off-by-one with
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* relation to other per-slot accesses on the PIC.
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* Here is a table that shows some of that:
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*
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* Internal Slot#
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@ -65,7 +65,7 @@
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*****************************************************************************/
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/* NOTE: PIC WAR. PV#854697. PIC does not allow writes just to [31:0]
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* of a 64-bit register. When writing PIC registers, always write the
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* of a 64-bit register. When writing PIC registers, always write the
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* entire 64 bits.
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*/
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@ -164,7 +164,7 @@ struct pic {
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uint64_t clear_all; /* 0x000{438,,,5F8} */
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} p_buf_count[8];
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/* 0x000600-0x0009FF -- PCI/X registers */
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uint64_t p_pcix_bus_err_addr; /* 0x000600 */
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uint64_t p_pcix_bus_err_attr; /* 0x000608 */
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@ -111,7 +111,7 @@ struct tiocp{
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uint64_t clear_all; /* 0x000{438,,,5F8} */
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} cp_buf_count[8];
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/* 0x000600-0x0009FF -- PCI/X registers */
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uint64_t cp_pcix_bus_err_addr; /* 0x000600 */
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uint64_t cp_pcix_bus_err_attr; /* 0x000608 */
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