drm/i915/guc: use for_each_engine_id() where appropriate
Now that host structures are indexed by host engine-id rather than guc_id, we can usefully convert some for_each_engine() loops to use for_each_engine_id() and avoid multiple dereferences of engine->id. Also a few related tweaks to cache structure members locally wherever they're used more than once or twice, hopefully eliminating memory references. Signed-off-by: Dave Gordon <david.s.gordon@intel.com> Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
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@ -2544,6 +2544,7 @@ static void i915_guc_client_info(struct seq_file *m,
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struct i915_guc_client *client)
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{
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struct intel_engine_cs *engine;
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enum intel_engine_id id;
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uint64_t tot = 0;
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seq_printf(m, "\tPriority %d, GuC ctx index: %u, PD offset 0x%x\n",
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@ -2558,11 +2559,11 @@ static void i915_guc_client_info(struct seq_file *m,
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seq_printf(m, "\tFailed doorbell: %u\n", client->b_fail);
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seq_printf(m, "\tLast submission result: %d\n", client->retcode);
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for_each_engine(engine, dev_priv) {
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for_each_engine_id(engine, dev_priv, id) {
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u64 submissions = client->submissions[id];
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tot += submissions;
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seq_printf(m, "\tSubmissions: %llu %s\n",
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client->submissions[engine->id],
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engine->name);
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tot += client->submissions[engine->id];
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submissions, engine->name);
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}
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seq_printf(m, "\tTotal: %llu\n", tot);
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}
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@ -2575,6 +2576,7 @@ static int i915_guc_info(struct seq_file *m, void *data)
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struct intel_guc guc;
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struct i915_guc_client client = {};
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struct intel_engine_cs *engine;
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enum intel_engine_id id;
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u64 total = 0;
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if (!HAS_GUC_SCHED(dev_priv))
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@ -2601,11 +2603,11 @@ static int i915_guc_info(struct seq_file *m, void *data)
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seq_printf(m, "GuC last action error code: %d\n", guc.action_err);
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seq_printf(m, "\nGuC submissions:\n");
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for_each_engine(engine, dev_priv) {
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for_each_engine_id(engine, dev_priv, id) {
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u64 submissions = guc.submissions[id];
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total += submissions;
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seq_printf(m, "\t%-24s: %10llu, last seqno 0x%08x\n",
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engine->name, guc.submissions[engine->id],
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guc.last_seqno[engine->id]);
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total += guc.submissions[engine->id];
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engine->name, submissions, guc.last_seqno[id]);
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}
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seq_printf(m, "\t%s: %llu\n", "Total", total);
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@ -342,7 +342,8 @@ static void guc_init_ctx_desc(struct intel_guc *guc,
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for_each_engine_masked(engine, dev_priv, client->engines) {
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struct intel_context *ce = &ctx->engine[engine->id];
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struct guc_execlist_context *lrc = &desc.lrc[engine->guc_id];
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uint32_t guc_engine_id = engine->guc_id;
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struct guc_execlist_context *lrc = &desc.lrc[guc_engine_id];
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struct drm_i915_gem_object *obj;
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/* TODO: We have a design issue to be solved here. Only when we
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@ -361,7 +362,7 @@ static void guc_init_ctx_desc(struct intel_guc *guc,
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gfx_addr = i915_gem_obj_ggtt_offset(ce->state);
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lrc->ring_lcra = gfx_addr + LRC_STATE_PN * PAGE_SIZE;
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lrc->context_id = (client->ctx_index << GUC_ELC_CTXID_OFFSET) |
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(engine->guc_id << GUC_ELC_ENGINE_OFFSET);
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(guc_engine_id << GUC_ELC_ENGINE_OFFSET);
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obj = ce->ring->obj;
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gfx_addr = i915_gem_obj_ggtt_offset(obj);
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@ -371,7 +372,7 @@ static void guc_init_ctx_desc(struct intel_guc *guc,
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lrc->ring_next_free_location = gfx_addr;
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lrc->ring_current_tail_pointer_value = 0;
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desc.engines_used |= (1 << engine->guc_id);
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desc.engines_used |= (1 << guc_engine_id);
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}
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DRM_DEBUG_DRIVER("Host engines 0x%x => GuC engines used 0x%x\n",
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@ -459,6 +460,7 @@ static void guc_add_workqueue_item(struct i915_guc_client *gc,
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/* wqi_len is in DWords, and does not include the one-word header */
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const size_t wqi_size = sizeof(struct guc_wq_item);
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const u32 wqi_len = wqi_size/sizeof(u32) - 1;
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struct intel_engine_cs *engine = rq->engine;
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struct guc_process_desc *desc;
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struct guc_wq_item *wqi;
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void *base;
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@ -500,12 +502,11 @@ static void guc_add_workqueue_item(struct i915_guc_client *gc,
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/* Now fill in the 4-word work queue item */
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wqi->header = WQ_TYPE_INORDER |
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(wqi_len << WQ_LEN_SHIFT) |
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(rq->engine->guc_id << WQ_TARGET_SHIFT) |
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(engine->guc_id << WQ_TARGET_SHIFT) |
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WQ_NO_WCFLUSH_WAIT;
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/* The GuC wants only the low-order word of the context descriptor */
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wqi->context_desc = (u32)intel_lr_context_descriptor(rq->ctx,
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rq->engine);
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wqi->context_desc = (u32)intel_lr_context_descriptor(rq->ctx, engine);
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wqi->ring_tail = tail << WQ_RING_TAIL_SHIFT;
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wqi->fence_id = rq->fence.seqno;
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