drm/radeon/cayman: set VM max pfn at MC init
No need to emit them at VM flush as we no longer use variable sized page tables now that we support 2 level page tables. This matches the behavior of SI (which does not support variable sized page tables). Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com>
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@ -776,7 +776,7 @@ static int cayman_pcie_gart_enable(struct radeon_device *rdev)
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*/
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for (i = 1; i < 8; i++) {
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WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR + (i << 2), 0);
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WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR + (i << 2), 0);
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WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR + (i << 2), rdev->vm_manager.max_pfn);
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WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (i << 2),
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rdev->gart.table_addr >> 12);
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}
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@ -1576,12 +1576,6 @@ void cayman_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm)
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if (vm == NULL)
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return;
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radeon_ring_write(ring, PACKET0(VM_CONTEXT0_PAGE_TABLE_START_ADDR + (vm->id << 2), 0));
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radeon_ring_write(ring, 0);
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radeon_ring_write(ring, PACKET0(VM_CONTEXT0_PAGE_TABLE_END_ADDR + (vm->id << 2), 0));
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radeon_ring_write(ring, rdev->vm_manager.max_pfn);
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radeon_ring_write(ring, PACKET0(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm->id << 2), 0));
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radeon_ring_write(ring, vm->pd_gpu_addr >> 12);
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